5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL)
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
32 The ARM series is a line of low-power-consumption RISC chip designs
33 licensed by ARM Ltd and targeted at embedded applications and
34 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
35 manufactured, but legacy ARM-based PC hardware remains popular in
36 Europe. There is an ARM Linux project with a web page at
37 <http://www.arm.linux.org.uk/>.
45 config SYS_SUPPORTS_APM_EMULATION
48 config HAVE_SCHED_CLOCK
54 config ARCH_USES_GETTIMEOFFSET
58 config GENERIC_CLOCKEVENTS
61 config GENERIC_CLOCKEVENTS_BROADCAST
63 depends on GENERIC_CLOCKEVENTS
72 select GENERIC_ALLOCATOR
83 The Extended Industry Standard Architecture (EISA) bus was
84 developed as an open alternative to the IBM MicroChannel bus.
86 The EISA bus provided some of the features of the IBM MicroChannel
87 bus while maintaining backward compatibility with cards made for
88 the older ISA bus. The EISA bus saw limited use between 1988 and
89 1995 when it was made obsolete by the PCI bus.
91 Say Y here if you are building a kernel for an EISA-based machine.
101 MicroChannel Architecture is found in some IBM PS/2 machines and
102 laptops. It is a bus system similar to PCI or ISA. See
103 <file:Documentation/mca.txt> (and especially the web page given
104 there) before attempting to build an MCA bus kernel.
106 config STACKTRACE_SUPPORT
110 config HAVE_LATENCYTOP_SUPPORT
115 config LOCKDEP_SUPPORT
119 config TRACE_IRQFLAGS_SUPPORT
123 config HARDIRQS_SW_RESEND
127 config GENERIC_IRQ_PROBE
131 config GENERIC_LOCKBREAK
134 depends on SMP && PREEMPT
136 config RWSEM_GENERIC_SPINLOCK
140 config RWSEM_XCHGADD_ALGORITHM
143 config ARCH_HAS_ILOG2_U32
146 config ARCH_HAS_ILOG2_U64
149 config ARCH_HAS_CPUFREQ
152 Internal node to signify that the ARCH has CPUFREQ support
153 and that the relevant menu configurations are displayed for
156 config ARCH_HAS_CPU_IDLE_WAIT
159 config GENERIC_HWEIGHT
163 config GENERIC_CALIBRATE_DELAY
167 config ARCH_MAY_HAVE_PC_FDC
173 config NEED_DMA_MAP_STATE
176 config GENERIC_ISA_DMA
187 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
188 default DRAM_BASE if REMAP_VECTORS_TO_RAM
191 The base address of exception vectors.
193 config ARM_PATCH_PHYS_VIRT
194 bool "Patch physical to virtual translations at runtime (EXPERIMENTAL)"
195 depends on EXPERIMENTAL
196 depends on !XIP_KERNEL && MMU
197 depends on !ARCH_REALVIEW || !SPARSEMEM
199 Patch phys-to-virt translation functions at runtime according to
200 the position of the kernel in system memory.
202 This can only be used with non-XIP with MMU kernels where
203 the base of physical memory is at a 16MB boundary.
205 config ARM_PATCH_PHYS_VIRT_16BIT
207 depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM
209 source "init/Kconfig"
211 source "kernel/Kconfig.freezer"
216 bool "MMU-based Paged Memory Management Support"
219 Select if you want MMU-based virtualised addressing space
220 support by paged memory management. If unsure, say 'Y'.
223 # The "ARM system type" choice list is ordered alphabetically by option
224 # text. Please add new entries in the option alphabetic order.
227 prompt "ARM system type"
228 default ARCH_VERSATILE
230 config ARCH_INTEGRATOR
231 bool "ARM Ltd. Integrator family"
233 select ARCH_HAS_CPUFREQ
236 select GENERIC_CLOCKEVENTS
237 select PLAT_VERSATILE
239 Support for ARM's Integrator platform.
242 bool "ARM Ltd. RealView family"
245 select HAVE_SCHED_CLOCK
247 select GENERIC_CLOCKEVENTS
248 select ARCH_WANT_OPTIONAL_GPIOLIB
249 select PLAT_VERSATILE
250 select ARM_TIMER_SP804
251 select GPIO_PL061 if GPIOLIB
253 This enables support for ARM Ltd RealView boards.
255 config ARCH_VERSATILE
256 bool "ARM Ltd. Versatile family"
260 select HAVE_SCHED_CLOCK
262 select GENERIC_CLOCKEVENTS
263 select ARCH_WANT_OPTIONAL_GPIOLIB
264 select PLAT_VERSATILE
265 select ARM_TIMER_SP804
267 This enables support for ARM Ltd Versatile board.
270 bool "ARM Ltd. Versatile Express family"
271 select ARCH_WANT_OPTIONAL_GPIOLIB
273 select ARM_TIMER_SP804
275 select GENERIC_CLOCKEVENTS
277 select HAVE_SCHED_CLOCK
279 select PLAT_VERSATILE
281 This enables support for the ARM Ltd Versatile Express boards.
285 select ARCH_REQUIRE_GPIOLIB
288 This enables support for systems based on the Atmel AT91RM9200,
289 AT91SAM9 and AT91CAP9 processors.
292 bool "Broadcom BCMRING"
297 select GENERIC_CLOCKEVENTS
298 select ARCH_WANT_OPTIONAL_GPIOLIB
300 Support for Broadcom's BCMRing platform.
303 bool "Cirrus Logic CLPS711x/EP721x-based"
305 select ARCH_USES_GETTIMEOFFSET
307 Support for Cirrus Logic 711x/721x based boards.
310 bool "Cavium Networks CNS3XXX family"
312 select GENERIC_CLOCKEVENTS
314 select MIGHT_HAVE_PCI
315 select PCI_DOMAINS if PCI
317 Support for Cavium Networks CNS3XXX platform.
320 bool "Cortina Systems Gemini"
322 select ARCH_REQUIRE_GPIOLIB
323 select ARCH_USES_GETTIMEOFFSET
325 Support for the Cortina Systems Gemini family SoCs
332 select ARCH_USES_GETTIMEOFFSET
334 This is an evaluation board for the StrongARM processor available
335 from Digital. It has limited hardware on-board, including an
336 Ethernet interface, two PCMCIA sockets, two serial ports and a
345 select ARCH_REQUIRE_GPIOLIB
346 select ARCH_HAS_HOLES_MEMORYMODEL
347 select ARCH_USES_GETTIMEOFFSET
349 This enables support for the Cirrus EP93xx series of CPUs.
351 config ARCH_FOOTBRIDGE
355 select GENERIC_CLOCKEVENTS
357 Support for systems based on the DC21285 companion chip
358 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
361 bool "Freescale MXC/iMX-based"
362 select GENERIC_CLOCKEVENTS
363 select ARCH_REQUIRE_GPIOLIB
366 Support for Freescale MXC/iMX-based family of processors
369 bool "Freescale MXS-based"
370 select GENERIC_CLOCKEVENTS
371 select ARCH_REQUIRE_GPIOLIB
374 Support for Freescale MXS-based family of processors
377 bool "Freescale STMP3xxx"
380 select ARCH_REQUIRE_GPIOLIB
381 select GENERIC_CLOCKEVENTS
382 select USB_ARCH_HAS_EHCI
384 Support for systems based on the Freescale 3xxx CPUs.
387 bool "Hilscher NetX based"
390 select GENERIC_CLOCKEVENTS
392 This enables support for systems based on the Hilscher NetX Soc
395 bool "Hynix HMS720x-based"
398 select ARCH_USES_GETTIMEOFFSET
400 This enables support for systems based on the Hynix HMS720x
408 select ARCH_SUPPORTS_MSI
411 Support for Intel's IOP13XX (XScale) family of processors.
419 select ARCH_REQUIRE_GPIOLIB
421 Support for Intel's 80219 and IOP32X (XScale) family of
430 select ARCH_REQUIRE_GPIOLIB
432 Support for Intel's IOP33X (XScale) family of processors.
439 select ARCH_USES_GETTIMEOFFSET
441 Support for Intel's IXP23xx (XScale) family of processors.
444 bool "IXP2400/2800-based"
448 select ARCH_USES_GETTIMEOFFSET
450 Support for Intel's IXP2400/2800 (XScale) family of processors.
457 select GENERIC_CLOCKEVENTS
458 select HAVE_SCHED_CLOCK
459 select MIGHT_HAVE_PCI
460 select DMABOUNCE if PCI
462 Support for Intel's IXP4XX (XScale) family of processors.
468 select ARCH_REQUIRE_GPIOLIB
469 select GENERIC_CLOCKEVENTS
472 Support for the Marvell Dove SoC 88AP510
475 bool "Marvell Kirkwood"
478 select ARCH_REQUIRE_GPIOLIB
479 select GENERIC_CLOCKEVENTS
482 Support for the following Marvell Kirkwood series SoCs:
483 88F6180, 88F6192 and 88F6281.
486 bool "Marvell Loki (88RC8480)"
488 select GENERIC_CLOCKEVENTS
491 Support for the Marvell Loki (88RC8480) SoC.
496 select ARCH_REQUIRE_GPIOLIB
499 select USB_ARCH_HAS_OHCI
502 select GENERIC_CLOCKEVENTS
504 Support for the NXP LPC32XX family of processors
507 bool "Marvell MV78xx0"
510 select ARCH_REQUIRE_GPIOLIB
511 select GENERIC_CLOCKEVENTS
514 Support for the following Marvell MV78xx0 series SoCs:
522 select ARCH_REQUIRE_GPIOLIB
523 select GENERIC_CLOCKEVENTS
526 Support for the following Marvell Orion 5x series SoCs:
527 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
528 Orion-2 (5281), Orion-1-90 (6183).
531 bool "Marvell PXA168/910/MMP2"
533 select ARCH_REQUIRE_GPIOLIB
535 select GENERIC_CLOCKEVENTS
536 select HAVE_SCHED_CLOCK
541 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
544 bool "Micrel/Kendin KS8695"
546 select ARCH_REQUIRE_GPIOLIB
547 select ARCH_USES_GETTIMEOFFSET
549 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
550 System-on-Chip devices.
553 bool "NetSilicon NS9xxx"
556 select GENERIC_CLOCKEVENTS
559 Say Y here if you intend to run this kernel on a NetSilicon NS9xxx
562 <http://www.digi.com/products/microprocessors/index.jsp>
565 bool "Nuvoton W90X900 CPU"
567 select ARCH_REQUIRE_GPIOLIB
569 select GENERIC_CLOCKEVENTS
571 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
572 At present, the w90x900 has been renamed nuc900, regarding
573 the ARM series product line, you can login the following
574 link address to know more.
576 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
577 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
580 bool "Nuvoton NUC93X CPU"
584 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
585 low-power and high performance MPEG-4/JPEG multimedia controller chip.
591 select GENERIC_CLOCKEVENTS
594 select HAVE_SCHED_CLOCK
595 select ARCH_HAS_BARRIERS if CACHE_L2X0
596 select ARCH_HAS_CPUFREQ
598 This enables support for NVIDIA Tegra based systems (Tegra APX,
599 Tegra 6xx and Tegra 2 series).
602 bool "Philips Nexperia PNX4008 Mobile"
605 select ARCH_USES_GETTIMEOFFSET
607 This enables support for Philips PNX4008 mobile platform.
610 bool "PXA2xx/PXA3xx-based"
613 select ARCH_HAS_CPUFREQ
615 select ARCH_REQUIRE_GPIOLIB
616 select GENERIC_CLOCKEVENTS
617 select HAVE_SCHED_CLOCK
622 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
627 select GENERIC_CLOCKEVENTS
628 select ARCH_REQUIRE_GPIOLIB
631 Support for Qualcomm MSM/QSD based systems. This runs on the
632 apps processor of the MSM/QSD and depends on a shared memory
633 interface to the modem processor which runs the baseband
634 stack and controls some vital subsystems
635 (clock and power control, etc).
638 bool "Renesas SH-Mobile / R-Mobile"
641 select GENERIC_CLOCKEVENTS
644 select MULTI_IRQ_HANDLER
646 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
653 select ARCH_MAY_HAVE_PC_FDC
654 select HAVE_PATA_PLATFORM
657 select ARCH_SPARSEMEM_ENABLE
658 select ARCH_USES_GETTIMEOFFSET
660 On the Acorn Risc-PC, Linux can support the internal IDE disk and
661 CD-ROM interface, serial and parallel port, and the floppy drive.
667 select ARCH_SPARSEMEM_ENABLE
669 select ARCH_HAS_CPUFREQ
671 select GENERIC_CLOCKEVENTS
673 select HAVE_SCHED_CLOCK
675 select ARCH_REQUIRE_GPIOLIB
677 Support for StrongARM 11x0 based boards.
680 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
682 select ARCH_HAS_CPUFREQ
684 select ARCH_USES_GETTIMEOFFSET
685 select HAVE_S3C2410_I2C if I2C
687 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
688 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
689 the Samsung SMDK2410 development board (and derivatives).
691 Note, the S3C2416 and the S3C2450 are so close that they even share
692 the same SoC ID code. This means that there is no seperate machine
693 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
696 bool "Samsung S3C64XX"
702 select ARCH_USES_GETTIMEOFFSET
703 select ARCH_HAS_CPUFREQ
704 select ARCH_REQUIRE_GPIOLIB
705 select SAMSUNG_CLKSRC
706 select SAMSUNG_IRQ_VIC_TIMER
707 select SAMSUNG_IRQ_UART
708 select S3C_GPIO_TRACK
709 select S3C_GPIO_PULL_UPDOWN
710 select S3C_GPIO_CFG_S3C24XX
711 select S3C_GPIO_CFG_S3C64XX
713 select USB_ARCH_HAS_OHCI
714 select SAMSUNG_GPIOLIB_4BIT
715 select HAVE_S3C2410_I2C if I2C
716 select HAVE_S3C2410_WATCHDOG if WATCHDOG
718 Samsung S3C64XX series based systems
721 bool "Samsung S5P6440 S5P6450"
725 select HAVE_S3C2410_WATCHDOG if WATCHDOG
726 select GENERIC_CLOCKEVENTS
727 select HAVE_SCHED_CLOCK
728 select HAVE_S3C2410_I2C if I2C
729 select HAVE_S3C_RTC if RTC_CLASS
731 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
735 bool "Samsung S5P6442"
739 select ARCH_USES_GETTIMEOFFSET
740 select HAVE_S3C2410_WATCHDOG if WATCHDOG
742 Samsung S5P6442 CPU based systems
745 bool "Samsung S5PC100"
749 select ARM_L1_CACHE_SHIFT_6
750 select ARCH_USES_GETTIMEOFFSET
751 select HAVE_S3C2410_I2C if I2C
752 select HAVE_S3C_RTC if RTC_CLASS
753 select HAVE_S3C2410_WATCHDOG if WATCHDOG
755 Samsung S5PC100 series based systems
758 bool "Samsung S5PV210/S5PC110"
760 select ARCH_SPARSEMEM_ENABLE
763 select ARM_L1_CACHE_SHIFT_6
764 select ARCH_HAS_CPUFREQ
765 select GENERIC_CLOCKEVENTS
766 select HAVE_SCHED_CLOCK
767 select HAVE_S3C2410_I2C if I2C
768 select HAVE_S3C_RTC if RTC_CLASS
769 select HAVE_S3C2410_WATCHDOG if WATCHDOG
771 Samsung S5PV210/S5PC110 series based systems
774 bool "Samsung EXYNOS4"
776 select ARCH_SPARSEMEM_ENABLE
779 select ARCH_HAS_CPUFREQ
780 select GENERIC_CLOCKEVENTS
781 select HAVE_S3C_RTC if RTC_CLASS
782 select HAVE_S3C2410_I2C if I2C
783 select HAVE_S3C2410_WATCHDOG if WATCHDOG
785 Samsung EXYNOS4 series based systems
794 select ARCH_USES_GETTIMEOFFSET
796 Support for the StrongARM based Digital DNARD machine, also known
797 as "Shark" (<http://www.shark-linux.de/shark.html>).
800 bool "Telechips TCC ARM926-based systems"
804 select GENERIC_CLOCKEVENTS
806 Support for Telechips TCC ARM926-based systems.
809 bool "ST-Ericsson U300 Series"
812 select HAVE_SCHED_CLOCK
816 select GENERIC_CLOCKEVENTS
820 Support for ST-Ericsson U300 series mobile platforms.
823 bool "ST-Ericsson U8500 Series"
826 select GENERIC_CLOCKEVENTS
828 select ARCH_REQUIRE_GPIOLIB
829 select ARCH_HAS_CPUFREQ
831 Support for ST-Ericsson's Ux500 architecture
834 bool "STMicroelectronics Nomadik"
839 select GENERIC_CLOCKEVENTS
840 select ARCH_REQUIRE_GPIOLIB
842 Support for the Nomadik platform by ST-Ericsson
846 select GENERIC_CLOCKEVENTS
847 select ARCH_REQUIRE_GPIOLIB
851 select GENERIC_ALLOCATOR
852 select ARCH_HAS_HOLES_MEMORYMODEL
854 Support for TI's DaVinci platform.
859 select ARCH_REQUIRE_GPIOLIB
860 select ARCH_HAS_CPUFREQ
861 select GENERIC_CLOCKEVENTS
862 select HAVE_SCHED_CLOCK
863 select ARCH_HAS_HOLES_MEMORYMODEL
865 Support for TI's OMAP platform (OMAP1/2/3/4).
870 select ARCH_REQUIRE_GPIOLIB
872 select GENERIC_CLOCKEVENTS
875 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
878 bool "VIA/WonderMedia 85xx"
881 select ARCH_HAS_CPUFREQ
882 select GENERIC_CLOCKEVENTS
883 select ARCH_REQUIRE_GPIOLIB
886 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
890 # This is sorted alphabetically by mach-* pathname. However, plat-*
891 # Kconfigs may be included either alphabetically (according to the
892 # plat- suffix) or along side the corresponding mach-* source.
894 source "arch/arm/mach-at91/Kconfig"
896 source "arch/arm/mach-bcmring/Kconfig"
898 source "arch/arm/mach-clps711x/Kconfig"
900 source "arch/arm/mach-cns3xxx/Kconfig"
902 source "arch/arm/mach-davinci/Kconfig"
904 source "arch/arm/mach-dove/Kconfig"
906 source "arch/arm/mach-ep93xx/Kconfig"
908 source "arch/arm/mach-footbridge/Kconfig"
910 source "arch/arm/mach-gemini/Kconfig"
912 source "arch/arm/mach-h720x/Kconfig"
914 source "arch/arm/mach-integrator/Kconfig"
916 source "arch/arm/mach-iop32x/Kconfig"
918 source "arch/arm/mach-iop33x/Kconfig"
920 source "arch/arm/mach-iop13xx/Kconfig"
922 source "arch/arm/mach-ixp4xx/Kconfig"
924 source "arch/arm/mach-ixp2000/Kconfig"
926 source "arch/arm/mach-ixp23xx/Kconfig"
928 source "arch/arm/mach-kirkwood/Kconfig"
930 source "arch/arm/mach-ks8695/Kconfig"
932 source "arch/arm/mach-loki/Kconfig"
934 source "arch/arm/mach-lpc32xx/Kconfig"
936 source "arch/arm/mach-msm/Kconfig"
938 source "arch/arm/mach-mv78xx0/Kconfig"
940 source "arch/arm/plat-mxc/Kconfig"
942 source "arch/arm/mach-mxs/Kconfig"
944 source "arch/arm/mach-netx/Kconfig"
946 source "arch/arm/mach-nomadik/Kconfig"
947 source "arch/arm/plat-nomadik/Kconfig"
949 source "arch/arm/mach-ns9xxx/Kconfig"
951 source "arch/arm/mach-nuc93x/Kconfig"
953 source "arch/arm/plat-omap/Kconfig"
955 source "arch/arm/mach-omap1/Kconfig"
957 source "arch/arm/mach-omap2/Kconfig"
959 source "arch/arm/mach-orion5x/Kconfig"
961 source "arch/arm/mach-pxa/Kconfig"
962 source "arch/arm/plat-pxa/Kconfig"
964 source "arch/arm/mach-mmp/Kconfig"
966 source "arch/arm/mach-realview/Kconfig"
968 source "arch/arm/mach-sa1100/Kconfig"
970 source "arch/arm/plat-samsung/Kconfig"
971 source "arch/arm/plat-s3c24xx/Kconfig"
972 source "arch/arm/plat-s5p/Kconfig"
974 source "arch/arm/plat-spear/Kconfig"
976 source "arch/arm/plat-tcc/Kconfig"
979 source "arch/arm/mach-s3c2400/Kconfig"
980 source "arch/arm/mach-s3c2410/Kconfig"
981 source "arch/arm/mach-s3c2412/Kconfig"
982 source "arch/arm/mach-s3c2416/Kconfig"
983 source "arch/arm/mach-s3c2440/Kconfig"
984 source "arch/arm/mach-s3c2443/Kconfig"
988 source "arch/arm/mach-s3c64xx/Kconfig"
991 source "arch/arm/mach-s5p64x0/Kconfig"
993 source "arch/arm/mach-s5p6442/Kconfig"
995 source "arch/arm/mach-s5pc100/Kconfig"
997 source "arch/arm/mach-s5pv210/Kconfig"
999 source "arch/arm/mach-exynos4/Kconfig"
1001 source "arch/arm/mach-shmobile/Kconfig"
1003 source "arch/arm/plat-stmp3xxx/Kconfig"
1005 source "arch/arm/mach-tegra/Kconfig"
1007 source "arch/arm/mach-u300/Kconfig"
1009 source "arch/arm/mach-ux500/Kconfig"
1011 source "arch/arm/mach-versatile/Kconfig"
1013 source "arch/arm/mach-vexpress/Kconfig"
1015 source "arch/arm/mach-vt8500/Kconfig"
1017 source "arch/arm/mach-w90x900/Kconfig"
1019 # Definitions to make life easier
1025 select GENERIC_CLOCKEVENTS
1026 select HAVE_SCHED_CLOCK
1030 select HAVE_SCHED_CLOCK
1035 config PLAT_VERSATILE
1038 config ARM_TIMER_SP804
1041 source arch/arm/mm/Kconfig
1044 bool "Enable iWMMXt support"
1045 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1046 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1048 Enable support for iWMMXt context switching at run time if
1049 running on a CPU that supports it.
1051 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1054 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1058 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1059 (!ARCH_OMAP3 || OMAP3_EMU)
1063 config MULTI_IRQ_HANDLER
1066 Allow each machine to specify it's own IRQ handler at run time.
1069 source "arch/arm/Kconfig-nommu"
1072 config ARM_ERRATA_411920
1073 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1074 depends on CPU_V6 || CPU_V6K
1076 Invalidation of the Instruction Cache operation can
1077 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1078 It does not affect the MPCore. This option enables the ARM Ltd.
1079 recommended workaround.
1081 config ARM_ERRATA_430973
1082 bool "ARM errata: Stale prediction on replaced interworking branch"
1085 This option enables the workaround for the 430973 Cortex-A8
1086 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1087 interworking branch is replaced with another code sequence at the
1088 same virtual address, whether due to self-modifying code or virtual
1089 to physical address re-mapping, Cortex-A8 does not recover from the
1090 stale interworking branch prediction. This results in Cortex-A8
1091 executing the new code sequence in the incorrect ARM or Thumb state.
1092 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1093 and also flushes the branch target cache at every context switch.
1094 Note that setting specific bits in the ACTLR register may not be
1095 available in non-secure mode.
1097 config ARM_ERRATA_458693
1098 bool "ARM errata: Processor deadlock when a false hazard is created"
1101 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1102 erratum. For very specific sequences of memory operations, it is
1103 possible for a hazard condition intended for a cache line to instead
1104 be incorrectly associated with a different cache line. This false
1105 hazard might then cause a processor deadlock. The workaround enables
1106 the L1 caching of the NEON accesses and disables the PLD instruction
1107 in the ACTLR register. Note that setting specific bits in the ACTLR
1108 register may not be available in non-secure mode.
1110 config ARM_ERRATA_460075
1111 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1114 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1115 erratum. Any asynchronous access to the L2 cache may encounter a
1116 situation in which recent store transactions to the L2 cache are lost
1117 and overwritten with stale memory contents from external memory. The
1118 workaround disables the write-allocate mode for the L2 cache via the
1119 ACTLR register. Note that setting specific bits in the ACTLR register
1120 may not be available in non-secure mode.
1122 config ARM_ERRATA_742230
1123 bool "ARM errata: DMB operation may be faulty"
1124 depends on CPU_V7 && SMP
1126 This option enables the workaround for the 742230 Cortex-A9
1127 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1128 between two write operations may not ensure the correct visibility
1129 ordering of the two writes. This workaround sets a specific bit in
1130 the diagnostic register of the Cortex-A9 which causes the DMB
1131 instruction to behave as a DSB, ensuring the correct behaviour of
1134 config ARM_ERRATA_742231
1135 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1136 depends on CPU_V7 && SMP
1138 This option enables the workaround for the 742231 Cortex-A9
1139 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1140 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1141 accessing some data located in the same cache line, may get corrupted
1142 data due to bad handling of the address hazard when the line gets
1143 replaced from one of the CPUs at the same time as another CPU is
1144 accessing it. This workaround sets specific bits in the diagnostic
1145 register of the Cortex-A9 which reduces the linefill issuing
1146 capabilities of the processor.
1148 config PL310_ERRATA_588369
1149 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1150 depends on CACHE_L2X0
1152 The PL310 L2 cache controller implements three types of Clean &
1153 Invalidate maintenance operations: by Physical Address
1154 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1155 They are architecturally defined to behave as the execution of a
1156 clean operation followed immediately by an invalidate operation,
1157 both performing to the same memory location. This functionality
1158 is not correctly implemented in PL310 as clean lines are not
1159 invalidated as a result of these operations.
1161 config ARM_ERRATA_720789
1162 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1163 depends on CPU_V7 && SMP
1165 This option enables the workaround for the 720789 Cortex-A9 (prior to
1166 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1167 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1168 As a consequence of this erratum, some TLB entries which should be
1169 invalidated are not, resulting in an incoherency in the system page
1170 tables. The workaround changes the TLB flushing routines to invalidate
1171 entries regardless of the ASID.
1173 config PL310_ERRATA_727915
1174 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1175 depends on CACHE_L2X0
1177 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1178 operation (offset 0x7FC). This operation runs in background so that
1179 PL310 can handle normal accesses while it is in progress. Under very
1180 rare circumstances, due to this erratum, write data can be lost when
1181 PL310 treats a cacheable write transaction during a Clean &
1182 Invalidate by Way operation.
1184 config ARM_ERRATA_743622
1185 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1188 This option enables the workaround for the 743622 Cortex-A9
1189 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1190 optimisation in the Cortex-A9 Store Buffer may lead to data
1191 corruption. This workaround sets a specific bit in the diagnostic
1192 register of the Cortex-A9 which disables the Store Buffer
1193 optimisation, preventing the defect from occurring. This has no
1194 visible impact on the overall performance or power consumption of the
1197 config ARM_ERRATA_751472
1198 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1199 depends on CPU_V7 && SMP
1201 This option enables the workaround for the 751472 Cortex-A9 (prior
1202 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1203 completion of a following broadcasted operation if the second
1204 operation is received by a CPU before the ICIALLUIS has completed,
1205 potentially leading to corrupted entries in the cache or TLB.
1207 config ARM_ERRATA_753970
1208 bool "ARM errata: cache sync operation may be faulty"
1209 depends on CACHE_PL310
1211 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1213 Under some condition the effect of cache sync operation on
1214 the store buffer still remains when the operation completes.
1215 This means that the store buffer is always asked to drain and
1216 this prevents it from merging any further writes. The workaround
1217 is to replace the normal offset of cache sync operation (0x730)
1218 by another offset targeting an unmapped PL310 register 0x740.
1219 This has the same effect as the cache sync operation: store buffer
1220 drain and waiting for all buffers empty.
1222 config ARM_ERRATA_754322
1223 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1226 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1227 r3p*) erratum. A speculative memory access may cause a page table walk
1228 which starts prior to an ASID switch but completes afterwards. This
1229 can populate the micro-TLB with a stale entry which may be hit with
1230 the new ASID. This workaround places two dsb instructions in the mm
1231 switching code so that no page table walks can cross the ASID switch.
1233 config ARM_ERRATA_754327
1234 bool "ARM errata: no automatic Store Buffer drain"
1235 depends on CPU_V7 && SMP
1237 This option enables the workaround for the 754327 Cortex-A9 (prior to
1238 r2p0) erratum. The Store Buffer does not have any automatic draining
1239 mechanism and therefore a livelock may occur if an external agent
1240 continuously polls a memory location waiting to observe an update.
1241 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1242 written polling loops from denying visibility of updates to memory.
1246 source "arch/arm/common/Kconfig"
1256 Find out whether you have ISA slots on your motherboard. ISA is the
1257 name of a bus system, i.e. the way the CPU talks to the other stuff
1258 inside your box. Other bus systems are PCI, EISA, MicroChannel
1259 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1260 newer boards don't support it. If you have ISA, say Y, otherwise N.
1262 # Select ISA DMA controller support
1267 # Select ISA DMA interface
1272 bool "PCI support" if MIGHT_HAVE_PCI
1274 Find out whether you have a PCI motherboard. PCI is the name of a
1275 bus system, i.e. the way the CPU talks to the other stuff inside
1276 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1277 VESA. If you have PCI, say Y, otherwise N.
1283 config PCI_NANOENGINE
1284 bool "BSE nanoEngine PCI support"
1285 depends on SA1100_NANOENGINE
1287 Enable PCI on the BSE nanoEngine board.
1292 # Select the host bridge type
1293 config PCI_HOST_VIA82C505
1295 depends on PCI && ARCH_SHARK
1298 config PCI_HOST_ITE8152
1300 depends on PCI && MACH_ARMCORE
1304 source "drivers/pci/Kconfig"
1306 source "drivers/pcmcia/Kconfig"
1310 menu "Kernel Features"
1312 source "kernel/time/Kconfig"
1315 bool "Symmetric Multi-Processing (EXPERIMENTAL)"
1316 depends on EXPERIMENTAL
1317 depends on CPU_V6K || CPU_V7
1318 depends on GENERIC_CLOCKEVENTS
1319 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1320 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1321 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1322 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1323 select USE_GENERIC_SMP_HELPERS
1324 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1326 This enables support for systems with more than one CPU. If you have
1327 a system with only one CPU, like most personal computers, say N. If
1328 you have a system with more than one CPU, say Y.
1330 If you say N here, the kernel will run on single and multiprocessor
1331 machines, but will use only one CPU of a multiprocessor machine. If
1332 you say Y here, the kernel will run on many, but not all, single
1333 processor machines. On a single processor machine, the kernel will
1334 run faster if you say N here.
1336 See also <file:Documentation/i386/IO-APIC.txt>,
1337 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1338 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1340 If you don't know what to do here, say N.
1343 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1344 depends on EXPERIMENTAL
1345 depends on SMP && !XIP_KERNEL
1348 SMP kernels contain instructions which fail on non-SMP processors.
1349 Enabling this option allows the kernel to modify itself to make
1350 these instructions safe. Disabling it allows about 1K of space
1353 If you don't know what to do here, say Y.
1359 This option enables support for the ARM system coherency unit
1366 This options enables support for the ARM timer and watchdog unit
1369 prompt "Memory split"
1372 Select the desired split between kernel and user memory.
1374 If you are not absolutely sure what you are doing, leave this
1378 bool "3G/1G user/kernel split"
1380 bool "2G/2G user/kernel split"
1382 bool "1G/3G user/kernel split"
1387 default 0x40000000 if VMSPLIT_1G
1388 default 0x80000000 if VMSPLIT_2G
1392 int "Maximum number of CPUs (2-32)"
1398 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1399 depends on SMP && HOTPLUG && EXPERIMENTAL
1400 depends on !ARCH_MSM
1402 Say Y here to experiment with turning CPUs off and on. CPUs
1403 can be controlled through /sys/devices/system/cpu.
1406 bool "Use local timer interrupts"
1409 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1411 Enable support for local timers on SMP platforms, rather then the
1412 legacy IPI broadcast method. Local timers allows the system
1413 accounting to be spread across the timer interval, preventing a
1414 "thundering herd" at every timer tick.
1416 source kernel/Kconfig.preempt
1420 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1421 ARCH_S5P6442 || ARCH_S5PV210 || ARCH_EXYNOS4
1422 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1423 default AT91_TIMER_HZ if ARCH_AT91
1424 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1427 config THUMB2_KERNEL
1428 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1429 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1431 select ARM_ASM_UNIFIED
1433 By enabling this option, the kernel will be compiled in
1434 Thumb-2 mode. A compiler/assembler that understand the unified
1435 ARM-Thumb syntax is needed.
1439 config THUMB2_AVOID_R_ARM_THM_JUMP11
1440 bool "Work around buggy Thumb-2 short branch relocations in gas"
1441 depends on THUMB2_KERNEL && MODULES
1444 Various binutils versions can resolve Thumb-2 branches to
1445 locally-defined, preemptible global symbols as short-range "b.n"
1446 branch instructions.
1448 This is a problem, because there's no guarantee the final
1449 destination of the symbol, or any candidate locations for a
1450 trampoline, are within range of the branch. For this reason, the
1451 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1452 relocation in modules at all, and it makes little sense to add
1455 The symptom is that the kernel fails with an "unsupported
1456 relocation" error when loading some modules.
1458 Until fixed tools are available, passing
1459 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1460 code which hits this problem, at the cost of a bit of extra runtime
1461 stack usage in some cases.
1463 The problem is described in more detail at:
1464 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1466 Only Thumb-2 kernels are affected.
1468 Unless you are sure your tools don't have this problem, say Y.
1470 config ARM_ASM_UNIFIED
1474 bool "Use the ARM EABI to compile the kernel"
1476 This option allows for the kernel to be compiled using the latest
1477 ARM ABI (aka EABI). This is only useful if you are using a user
1478 space environment that is also compiled with EABI.
1480 Since there are major incompatibilities between the legacy ABI and
1481 EABI, especially with regard to structure member alignment, this
1482 option also changes the kernel syscall calling convention to
1483 disambiguate both ABIs and allow for backward compatibility support
1484 (selected with CONFIG_OABI_COMPAT).
1486 To use this you need GCC version 4.0.0 or later.
1489 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1490 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1493 This option preserves the old syscall interface along with the
1494 new (ARM EABI) one. It also provides a compatibility layer to
1495 intercept syscalls that have structure arguments which layout
1496 in memory differs between the legacy ABI and the new ARM EABI
1497 (only for non "thumb" binaries). This option adds a tiny
1498 overhead to all syscalls and produces a slightly larger kernel.
1499 If you know you'll be using only pure EABI user space then you
1500 can say N here. If this option is not selected and you attempt
1501 to execute a legacy ABI binary then the result will be
1502 UNPREDICTABLE (in fact it can be predicted that it won't work
1503 at all). If in doubt say Y.
1505 config ARCH_HAS_HOLES_MEMORYMODEL
1508 config ARCH_SPARSEMEM_ENABLE
1511 config ARCH_SPARSEMEM_DEFAULT
1512 def_bool ARCH_SPARSEMEM_ENABLE
1514 config ARCH_SELECT_MEMORY_MODEL
1515 def_bool ARCH_SPARSEMEM_ENABLE
1518 bool "High Memory Support (EXPERIMENTAL)"
1519 depends on MMU && EXPERIMENTAL
1521 The address space of ARM processors is only 4 Gigabytes large
1522 and it has to accommodate user address space, kernel address
1523 space as well as some memory mapped IO. That means that, if you
1524 have a large amount of physical memory and/or IO, not all of the
1525 memory can be "permanently mapped" by the kernel. The physical
1526 memory that is not permanently mapped is called "high memory".
1528 Depending on the selected kernel/user memory split, minimum
1529 vmalloc space and actual amount of RAM, you may not need this
1530 option which should result in a slightly faster kernel.
1535 bool "Allocate 2nd-level pagetables from highmem"
1537 depends on !OUTER_CACHE
1539 config HW_PERF_EVENTS
1540 bool "Enable hardware performance counter support for perf events"
1541 depends on PERF_EVENTS && CPU_HAS_PMU
1544 Enable hardware performance counter support for perf events. If
1545 disabled, perf events will use software events only.
1549 config FORCE_MAX_ZONEORDER
1550 int "Maximum zone order" if ARCH_SHMOBILE
1551 range 11 64 if ARCH_SHMOBILE
1552 default "9" if SA1111
1555 The kernel memory allocator divides physically contiguous memory
1556 blocks into "zones", where each zone is a power of two number of
1557 pages. This option selects the largest power of two that the kernel
1558 keeps in the memory allocator. If you need to allocate very large
1559 blocks of physically contiguous memory, then you may need to
1560 increase this value.
1562 This config option is actually maximum order plus one. For example,
1563 a value of 11 means that the largest free memory block is 2^10 pages.
1566 bool "Timer and CPU usage LEDs"
1567 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1568 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1569 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1570 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1571 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1572 ARCH_AT91 || ARCH_DAVINCI || \
1573 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1575 If you say Y here, the LEDs on your machine will be used
1576 to provide useful information about your current system status.
1578 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1579 be able to select which LEDs are active using the options below. If
1580 you are compiling a kernel for the EBSA-110 or the LART however, the
1581 red LED will simply flash regularly to indicate that the system is
1582 still functional. It is safe to say Y here if you have a CATS
1583 system, but the driver will do nothing.
1586 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1587 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1588 || MACH_OMAP_PERSEUS2
1590 depends on !GENERIC_CLOCKEVENTS
1591 default y if ARCH_EBSA110
1593 If you say Y here, one of the system LEDs (the green one on the
1594 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1595 will flash regularly to indicate that the system is still
1596 operational. This is mainly useful to kernel hackers who are
1597 debugging unstable kernels.
1599 The LART uses the same LED for both Timer LED and CPU usage LED
1600 functions. You may choose to use both, but the Timer LED function
1601 will overrule the CPU usage LED.
1604 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1606 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1607 || MACH_OMAP_PERSEUS2
1610 If you say Y here, the red LED will be used to give a good real
1611 time indication of CPU usage, by lighting whenever the idle task
1612 is not currently executing.
1614 The LART uses the same LED for both Timer LED and CPU usage LED
1615 functions. You may choose to use both, but the Timer LED function
1616 will overrule the CPU usage LED.
1618 config ALIGNMENT_TRAP
1620 depends on CPU_CP15_MMU
1621 default y if !ARCH_EBSA110
1622 select HAVE_PROC_CPU if PROC_FS
1624 ARM processors cannot fetch/store information which is not
1625 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1626 address divisible by 4. On 32-bit ARM processors, these non-aligned
1627 fetch/store instructions will be emulated in software if you say
1628 here, which has a severe performance impact. This is necessary for
1629 correct operation of some network protocols. With an IP-only
1630 configuration it is safe to say N, otherwise say Y.
1632 config UACCESS_WITH_MEMCPY
1633 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1634 depends on MMU && EXPERIMENTAL
1635 default y if CPU_FEROCEON
1637 Implement faster copy_to_user and clear_user methods for CPU
1638 cores where a 8-word STM instruction give significantly higher
1639 memory write throughput than a sequence of individual 32bit stores.
1641 A possible side effect is a slight increase in scheduling latency
1642 between threads sharing the same address space if they invoke
1643 such copy operations with large buffers.
1645 However, if the CPU data cache is using a write-allocate mode,
1646 this option is unlikely to provide any performance gain.
1650 prompt "Enable seccomp to safely compute untrusted bytecode"
1652 This kernel feature is useful for number crunching applications
1653 that may need to compute untrusted bytecode during their
1654 execution. By using pipes or other transports made available to
1655 the process as file descriptors supporting the read/write
1656 syscalls, it's possible to isolate those applications in
1657 their own address space using seccomp. Once seccomp is
1658 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1659 and the task is only allowed to execute a few safe syscalls
1660 defined by each seccomp mode.
1662 config CC_STACKPROTECTOR
1663 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1664 depends on EXPERIMENTAL
1666 This option turns on the -fstack-protector GCC feature. This
1667 feature puts, at the beginning of functions, a canary value on
1668 the stack just before the return address, and validates
1669 the value just before actually returning. Stack based buffer
1670 overflows (that need to overwrite this return address) now also
1671 overwrite the canary, which gets detected and the attack is then
1672 neutralized via a kernel panic.
1673 This feature requires gcc version 4.2 or above.
1675 config DEPRECATED_PARAM_STRUCT
1676 bool "Provide old way to pass kernel parameters"
1678 This was deprecated in 2001 and announced to live on for 5 years.
1679 Some old boot loaders still use this way.
1685 # Compressed boot loader in ROM. Yes, we really want to ask about
1686 # TEXT and BSS so we preserve their values in the config files.
1687 config ZBOOT_ROM_TEXT
1688 hex "Compressed ROM boot loader base address"
1691 The physical address at which the ROM-able zImage is to be
1692 placed in the target. Platforms which normally make use of
1693 ROM-able zImage formats normally set this to a suitable
1694 value in their defconfig file.
1696 If ZBOOT_ROM is not enabled, this has no effect.
1698 config ZBOOT_ROM_BSS
1699 hex "Compressed ROM boot loader BSS address"
1702 The base address of an area of read/write memory in the target
1703 for the ROM-able zImage which must be available while the
1704 decompressor is running. It must be large enough to hold the
1705 entire decompressed kernel plus an additional 128 KiB.
1706 Platforms which normally make use of ROM-able zImage formats
1707 normally set this to a suitable value in their defconfig file.
1709 If ZBOOT_ROM is not enabled, this has no effect.
1712 bool "Compressed boot loader in ROM/flash"
1713 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1715 Say Y here if you intend to execute your compressed kernel image
1716 (zImage) directly from ROM or flash. If unsure, say N.
1718 config ZBOOT_ROM_MMCIF
1719 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1720 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1722 Say Y here to include experimental MMCIF loading code in the
1723 ROM-able zImage. With this enabled it is possible to write the
1724 the ROM-able zImage kernel image to an MMC card and boot the
1725 kernel straight from the reset vector. At reset the processor
1726 Mask ROM will load the first part of the the ROM-able zImage
1727 which in turn loads the rest the kernel image to RAM using the
1728 MMCIF hardware block.
1731 string "Default kernel command string"
1734 On some architectures (EBSA110 and CATS), there is currently no way
1735 for the boot loader to pass arguments to the kernel. For these
1736 architectures, you should supply some command-line options at build
1737 time by entering them here. As a minimum, you should specify the
1738 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1740 config CMDLINE_FORCE
1741 bool "Always use the default kernel command string"
1742 depends on CMDLINE != ""
1744 Always use the default kernel command string, even if the boot
1745 loader passes other arguments to the kernel.
1746 This is useful if you cannot or don't want to change the
1747 command-line options your boot loader passes to the kernel.
1752 bool "Kernel Execute-In-Place from ROM"
1753 depends on !ZBOOT_ROM
1755 Execute-In-Place allows the kernel to run from non-volatile storage
1756 directly addressable by the CPU, such as NOR flash. This saves RAM
1757 space since the text section of the kernel is not loaded from flash
1758 to RAM. Read-write sections, such as the data section and stack,
1759 are still copied to RAM. The XIP kernel is not compressed since
1760 it has to run directly from flash, so it will take more space to
1761 store it. The flash address used to link the kernel object files,
1762 and for storing it, is configuration dependent. Therefore, if you
1763 say Y here, you must know the proper physical address where to
1764 store the kernel image depending on your own flash memory usage.
1766 Also note that the make target becomes "make xipImage" rather than
1767 "make zImage" or "make Image". The final kernel binary to put in
1768 ROM memory will be arch/arm/boot/xipImage.
1772 config XIP_PHYS_ADDR
1773 hex "XIP Kernel Physical Location"
1774 depends on XIP_KERNEL
1775 default "0x00080000"
1777 This is the physical address in your flash memory the kernel will
1778 be linked for and stored to. This address is dependent on your
1782 bool "Kexec system call (EXPERIMENTAL)"
1783 depends on EXPERIMENTAL
1785 kexec is a system call that implements the ability to shutdown your
1786 current kernel, and to start another kernel. It is like a reboot
1787 but it is independent of the system firmware. And like a reboot
1788 you can start any kernel with it, not just Linux.
1790 It is an ongoing process to be certain the hardware in a machine
1791 is properly shutdown, so do not be surprised if this code does not
1792 initially work for you. It may help to enable device hotplugging
1796 bool "Export atags in procfs"
1800 Should the atags used to boot the kernel be exported in an "atags"
1801 file in procfs. Useful with kexec.
1804 bool "Build kdump crash kernel (EXPERIMENTAL)"
1805 depends on EXPERIMENTAL
1807 Generate crash dump after being started by kexec. This should
1808 be normally only set in special crash dump kernels which are
1809 loaded in the main kernel with kexec-tools into a specially
1810 reserved region and then later executed after a crash by
1811 kdump/kexec. The crash dump kernel must be compiled to a
1812 memory address not used by the main kernel
1814 For more details see Documentation/kdump/kdump.txt
1816 config AUTO_ZRELADDR
1817 bool "Auto calculation of the decompressed kernel image address"
1818 depends on !ZBOOT_ROM && !ARCH_U300
1820 ZRELADDR is the physical address where the decompressed kernel
1821 image will be placed. If AUTO_ZRELADDR is selected, the address
1822 will be determined at run-time by masking the current IP with
1823 0xf8000000. This assumes the zImage being placed in the first 128MB
1824 from start of memory.
1828 menu "CPU Power Management"
1832 source "drivers/cpufreq/Kconfig"
1835 tristate "CPUfreq driver for i.MX CPUs"
1836 depends on ARCH_MXC && CPU_FREQ
1838 This enables the CPUfreq driver for i.MX CPUs.
1840 config CPU_FREQ_SA1100
1843 config CPU_FREQ_SA1110
1846 config CPU_FREQ_INTEGRATOR
1847 tristate "CPUfreq driver for ARM Integrator CPUs"
1848 depends on ARCH_INTEGRATOR && CPU_FREQ
1851 This enables the CPUfreq driver for ARM Integrator CPUs.
1853 For details, take a look at <file:Documentation/cpu-freq>.
1859 depends on CPU_FREQ && ARCH_PXA && PXA25x
1861 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1863 config CPU_FREQ_S3C64XX
1864 bool "CPUfreq support for Samsung S3C64XX CPUs"
1865 depends on CPU_FREQ && CPU_S3C6410
1870 Internal configuration node for common cpufreq on Samsung SoC
1872 config CPU_FREQ_S3C24XX
1873 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
1874 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1877 This enables the CPUfreq driver for the Samsung S3C24XX family
1880 For details, take a look at <file:Documentation/cpu-freq>.
1884 config CPU_FREQ_S3C24XX_PLL
1885 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
1886 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
1888 Compile in support for changing the PLL frequency from the
1889 S3C24XX series CPUfreq driver. The PLL takes time to settle
1890 after a frequency change, so by default it is not enabled.
1892 This also means that the PLL tables for the selected CPU(s) will
1893 be built which may increase the size of the kernel image.
1895 config CPU_FREQ_S3C24XX_DEBUG
1896 bool "Debug CPUfreq Samsung driver core"
1897 depends on CPU_FREQ_S3C24XX
1899 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
1901 config CPU_FREQ_S3C24XX_IODEBUG
1902 bool "Debug CPUfreq Samsung driver IO timing"
1903 depends on CPU_FREQ_S3C24XX
1905 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
1907 config CPU_FREQ_S3C24XX_DEBUGFS
1908 bool "Export debugfs for CPUFreq"
1909 depends on CPU_FREQ_S3C24XX && DEBUG_FS
1911 Export status information via debugfs.
1915 source "drivers/cpuidle/Kconfig"
1919 menu "Floating point emulation"
1921 comment "At least one emulation must be selected"
1924 bool "NWFPE math emulation"
1925 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1927 Say Y to include the NWFPE floating point emulator in the kernel.
1928 This is necessary to run most binaries. Linux does not currently
1929 support floating point hardware so you need to say Y here even if
1930 your machine has an FPA or floating point co-processor podule.
1932 You may say N here if you are going to load the Acorn FPEmulator
1933 early in the bootup.
1936 bool "Support extended precision"
1937 depends on FPE_NWFPE
1939 Say Y to include 80-bit support in the kernel floating-point
1940 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1941 Note that gcc does not generate 80-bit operations by default,
1942 so in most cases this option only enlarges the size of the
1943 floating point emulator without any good reason.
1945 You almost surely want to say N here.
1948 bool "FastFPE math emulation (EXPERIMENTAL)"
1949 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
1951 Say Y here to include the FAST floating point emulator in the kernel.
1952 This is an experimental much faster emulator which now also has full
1953 precision for the mantissa. It does not support any exceptions.
1954 It is very simple, and approximately 3-6 times faster than NWFPE.
1956 It should be sufficient for most programs. It may be not suitable
1957 for scientific calculations, but you have to check this for yourself.
1958 If you do not feel you need a faster FP emulation you should better
1962 bool "VFP-format floating point maths"
1963 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1965 Say Y to include VFP support code in the kernel. This is needed
1966 if your hardware includes a VFP unit.
1968 Please see <file:Documentation/arm/VFP/release-notes.txt> for
1969 release notes and additional status information.
1971 Say N if your target does not have VFP hardware.
1979 bool "Advanced SIMD (NEON) Extension support"
1980 depends on VFPv3 && CPU_V7
1982 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
1987 menu "Userspace binary formats"
1989 source "fs/Kconfig.binfmt"
1992 tristate "RISC OS personality"
1995 Say Y here to include the kernel code necessary if you want to run
1996 Acorn RISC OS/Arthur binaries under Linux. This code is still very
1997 experimental; if this sounds frightening, say N and sleep in peace.
1998 You can also say M here to compile this support as a module (which
1999 will be called arthur).
2003 menu "Power management options"
2005 source "kernel/power/Kconfig"
2007 config ARCH_SUSPEND_POSSIBLE
2012 source "net/Kconfig"
2014 source "drivers/Kconfig"
2018 source "arch/arm/Kconfig.debug"
2020 source "security/Kconfig"
2022 source "crypto/Kconfig"
2024 source "lib/Kconfig"