4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
5 select ARCH_HAS_ELF_RANDOMIZE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_MIGHT_HAVE_PC_PARPORT
10 select ARCH_SUPPORTS_ATOMIC_RMW
11 select ARCH_USE_BUILTIN_BSWAP
12 select ARCH_USE_CMPXCHG_LOCKREF
13 select ARCH_WANT_IPC_PARSE_VERSION
14 select BUILDTIME_EXTABLE_SORT if MMU
15 select CLONE_BACKWARDS
16 select CPU_PM if (SUSPEND || CPU_IDLE)
17 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
19 select EDAC_ATOMIC_SCRUB
20 select GENERIC_ALLOCATOR
21 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
22 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
23 select GENERIC_EARLY_IOREMAP
24 select GENERIC_IDLE_POLL_SETUP
25 select GENERIC_IRQ_PROBE
26 select GENERIC_IRQ_SHOW
27 select GENERIC_IRQ_SHOW_LEVEL
28 select GENERIC_PCI_IOMAP
29 select GENERIC_SCHED_CLOCK
30 select GENERIC_SMP_IDLE_THREAD
31 select GENERIC_STRNCPY_FROM_USER
32 select GENERIC_STRNLEN_USER
33 select HANDLE_DOMAIN_IRQ
34 select HARDIRQS_SW_RESEND
35 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
36 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
37 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
38 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
39 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
40 select HAVE_ARCH_TRACEHOOK
41 select HAVE_ARM_SMCCC if CPU_V7
43 select HAVE_CC_STACKPROTECTOR
44 select HAVE_CONTEXT_TRACKING
45 select HAVE_C_RECORDMCOUNT
46 select HAVE_DEBUG_KMEMLEAK
47 select HAVE_DMA_API_DEBUG
49 select HAVE_DMA_CONTIGUOUS if MMU
50 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
51 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
52 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
53 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
54 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
55 select HAVE_GENERIC_DMA_COHERENT
56 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
57 select HAVE_IDE if PCI || ISA || PCMCIA
58 select HAVE_IRQ_TIME_ACCOUNTING
59 select HAVE_KERNEL_GZIP
60 select HAVE_KERNEL_LZ4
61 select HAVE_KERNEL_LZMA
62 select HAVE_KERNEL_LZO
64 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
65 select HAVE_KRETPROBES if (HAVE_KPROBES)
67 select HAVE_MOD_ARCH_SPECIFIC
68 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
69 select HAVE_OPTPROBES if !THUMB2_KERNEL
70 select HAVE_PERF_EVENTS
72 select HAVE_PERF_USER_STACK_DUMP
73 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
74 select HAVE_REGS_AND_STACK_ACCESS_API
75 select HAVE_SYSCALL_TRACEPOINTS
77 select HAVE_VIRT_CPU_ACCOUNTING_GEN
78 select IRQ_FORCED_THREADING
79 select MODULES_USE_ELF_REL
81 select OF_EARLY_FLATTREE if OF
82 select OF_RESERVED_MEM if OF
84 select OLD_SIGSUSPEND3
85 select PERF_USE_VMALLOC
87 select SYS_SUPPORTS_APM_EMULATION
88 # Above selects are sorted alphabetically; please add new ones
89 # according to that. Thanks.
91 The ARM series is a line of low-power-consumption RISC chip designs
92 licensed by ARM Ltd and targeted at embedded applications and
93 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
94 manufactured, but legacy ARM-based PC hardware remains popular in
95 Europe. There is an ARM Linux project with a web page at
96 <http://www.arm.linux.org.uk/>.
98 config ARM_HAS_SG_CHAIN
99 select ARCH_HAS_SG_CHAIN
102 config NEED_SG_DMA_LENGTH
105 config ARM_DMA_USE_IOMMU
107 select ARM_HAS_SG_CHAIN
108 select NEED_SG_DMA_LENGTH
112 config ARM_DMA_IOMMU_ALIGNMENT
113 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
117 DMA mapping framework by default aligns all buffers to the smallest
118 PAGE_SIZE order which is greater than or equal to the requested buffer
119 size. This works well for buffers up to a few hundreds kilobytes, but
120 for larger buffers it just a waste of address space. Drivers which has
121 relatively small addressing window (like 64Mib) might run out of
122 virtual space with just a few allocations.
124 With this parameter you can specify the maximum PAGE_SIZE order for
125 DMA IOMMU buffers. Larger buffers will be aligned only to this
126 specified order. The order is expressed as a power of two multiplied
131 config MIGHT_HAVE_PCI
134 config SYS_SUPPORTS_APM_EMULATION
139 select GENERIC_ALLOCATOR
150 The Extended Industry Standard Architecture (EISA) bus was
151 developed as an open alternative to the IBM MicroChannel bus.
153 The EISA bus provided some of the features of the IBM MicroChannel
154 bus while maintaining backward compatibility with cards made for
155 the older ISA bus. The EISA bus saw limited use between 1988 and
156 1995 when it was made obsolete by the PCI bus.
158 Say Y here if you are building a kernel for an EISA-based machine.
165 config STACKTRACE_SUPPORT
169 config HAVE_LATENCYTOP_SUPPORT
174 config LOCKDEP_SUPPORT
178 config TRACE_IRQFLAGS_SUPPORT
182 config RWSEM_XCHGADD_ALGORITHM
186 config ARCH_HAS_ILOG2_U32
189 config ARCH_HAS_ILOG2_U64
192 config ARCH_HAS_BANDGAP
195 config FIX_EARLYCON_MEM
198 config GENERIC_HWEIGHT
202 config GENERIC_CALIBRATE_DELAY
206 config ARCH_MAY_HAVE_PC_FDC
212 config NEED_DMA_MAP_STATE
215 config ARCH_SUPPORTS_UPROBES
218 config ARCH_HAS_DMA_SET_COHERENT_MASK
221 config GENERIC_ISA_DMA
227 config NEED_RET_TO_USER
235 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
236 default DRAM_BASE if REMAP_VECTORS_TO_RAM
239 The base address of exception vectors. This must be two pages
242 config ARM_PATCH_PHYS_VIRT
243 bool "Patch physical to virtual translations at runtime" if EMBEDDED
245 depends on !XIP_KERNEL && MMU
246 depends on !ARCH_REALVIEW || !SPARSEMEM
248 Patch phys-to-virt and virt-to-phys translation functions at
249 boot and module load time according to the position of the
250 kernel in system memory.
252 This can only be used with non-XIP MMU kernels where the base
253 of physical memory is at a 16MB boundary.
255 Only disable this option if you know that you do not require
256 this feature (eg, building a kernel for a single machine) and
257 you need to shrink the kernel to the minimal size.
259 config NEED_MACH_IO_H
262 Select this when mach/io.h is required to provide special
263 definitions for this platform. The need for mach/io.h should
264 be avoided when possible.
266 config NEED_MACH_MEMORY_H
269 Select this when mach/memory.h is required to provide special
270 definitions for this platform. The need for mach/memory.h should
271 be avoided when possible.
274 hex "Physical address of main memory" if MMU
275 depends on !ARM_PATCH_PHYS_VIRT
276 default DRAM_BASE if !MMU
277 default 0x00000000 if ARCH_EBSA110 || \
282 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
283 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
284 default 0x20000000 if ARCH_S5PV210
285 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
286 default 0xc0000000 if ARCH_SA1100
288 Please provide the physical address corresponding to the
289 location of main memory in your system.
295 config PGTABLE_LEVELS
297 default 3 if ARM_LPAE
300 source "init/Kconfig"
302 source "kernel/Kconfig.freezer"
307 bool "MMU-based Paged Memory Management Support"
310 Select if you want MMU-based virtualised addressing space
311 support by paged memory management. If unsure, say 'Y'.
314 # The "ARM system type" choice list is ordered alphabetically by option
315 # text. Please add new entries in the option alphabetic order.
318 prompt "ARM system type"
319 default ARCH_VERSATILE if !MMU
320 default ARCH_MULTIPLATFORM if MMU
322 config ARCH_MULTIPLATFORM
323 bool "Allow multiple platforms to be selected"
325 select ARCH_WANT_OPTIONAL_GPIOLIB
326 select ARM_HAS_SG_CHAIN
327 select ARM_PATCH_PHYS_VIRT
331 select GENERIC_CLOCKEVENTS
332 select MIGHT_HAVE_PCI
333 select MULTI_IRQ_HANDLER
337 config ARM_SINGLE_ARMV7M
338 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
340 select ARCH_WANT_OPTIONAL_GPIOLIB
346 select GENERIC_CLOCKEVENTS
352 bool "ARM Ltd. RealView family"
353 select ARCH_WANT_OPTIONAL_GPIOLIB
355 select ARM_TIMER_SP804
357 select COMMON_CLK_VERSATILE
358 select GENERIC_CLOCKEVENTS
359 select GPIO_PL061 if GPIOLIB
361 select NEED_MACH_MEMORY_H
362 select PLAT_VERSATILE
363 select PLAT_VERSATILE_SCHED_CLOCK
365 This enables support for ARM Ltd RealView boards.
367 config ARCH_VERSATILE
368 bool "ARM Ltd. Versatile family"
369 select ARCH_WANT_OPTIONAL_GPIOLIB
371 select ARM_TIMER_SP804
374 select GENERIC_CLOCKEVENTS
375 select HAVE_MACH_CLKDEV
377 select PLAT_VERSATILE
378 select PLAT_VERSATILE_CLOCK
379 select PLAT_VERSATILE_SCHED_CLOCK
380 select VERSATILE_FPGA_IRQ
382 This enables support for ARM Ltd Versatile board.
385 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
386 select ARCH_REQUIRE_GPIOLIB
391 select GENERIC_CLOCKEVENTS
395 Support for Cirrus Logic 711x/721x/731x based boards.
398 bool "Cortina Systems Gemini"
399 select ARCH_REQUIRE_GPIOLIB
402 select GENERIC_CLOCKEVENTS
404 Support for the Cortina Systems Gemini family SoCs
408 select ARCH_USES_GETTIMEOFFSET
411 select NEED_MACH_IO_H
412 select NEED_MACH_MEMORY_H
415 This is an evaluation board for the StrongARM processor available
416 from Digital. It has limited hardware on-board, including an
417 Ethernet interface, two PCMCIA sockets, two serial ports and a
422 select ARCH_HAS_HOLES_MEMORYMODEL
423 select ARCH_REQUIRE_GPIOLIB
425 select ARM_PATCH_PHYS_VIRT
431 select GENERIC_CLOCKEVENTS
433 This enables support for the Cirrus EP93xx series of CPUs.
435 config ARCH_FOOTBRIDGE
439 select GENERIC_CLOCKEVENTS
441 select NEED_MACH_IO_H if !MMU
442 select NEED_MACH_MEMORY_H
444 Support for systems based on the DC21285 companion chip
445 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
448 bool "Hilscher NetX based"
452 select GENERIC_CLOCKEVENTS
454 This enables support for systems based on the Hilscher NetX Soc
460 select NEED_MACH_MEMORY_H
461 select NEED_RET_TO_USER
467 Support for Intel's IOP13XX (XScale) family of processors.
472 select ARCH_REQUIRE_GPIOLIB
475 select NEED_RET_TO_USER
479 Support for Intel's 80219 and IOP32X (XScale) family of
485 select ARCH_REQUIRE_GPIOLIB
488 select NEED_RET_TO_USER
492 Support for Intel's IOP33X (XScale) family of processors.
497 select ARCH_HAS_DMA_SET_COHERENT_MASK
498 select ARCH_REQUIRE_GPIOLIB
499 select ARCH_SUPPORTS_BIG_ENDIAN
502 select DMABOUNCE if PCI
503 select GENERIC_CLOCKEVENTS
504 select MIGHT_HAVE_PCI
505 select NEED_MACH_IO_H
506 select USB_EHCI_BIG_ENDIAN_DESC
507 select USB_EHCI_BIG_ENDIAN_MMIO
509 Support for Intel's IXP4XX (XScale) family of processors.
513 select ARCH_REQUIRE_GPIOLIB
515 select GENERIC_CLOCKEVENTS
516 select MIGHT_HAVE_PCI
520 select PLAT_ORION_LEGACY
522 Support for the Marvell Dove SoC 88AP510
525 bool "Marvell MV78xx0"
526 select ARCH_REQUIRE_GPIOLIB
528 select GENERIC_CLOCKEVENTS
531 select PLAT_ORION_LEGACY
533 Support for the following Marvell MV78xx0 series SoCs:
539 select ARCH_REQUIRE_GPIOLIB
541 select GENERIC_CLOCKEVENTS
544 select PLAT_ORION_LEGACY
545 select MULTI_IRQ_HANDLER
547 Support for the following Marvell Orion 5x series SoCs:
548 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
549 Orion-2 (5281), Orion-1-90 (6183).
552 bool "Marvell PXA168/910/MMP2"
554 select ARCH_REQUIRE_GPIOLIB
556 select GENERIC_ALLOCATOR
557 select GENERIC_CLOCKEVENTS
560 select MULTI_IRQ_HANDLER
565 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
568 bool "Micrel/Kendin KS8695"
569 select ARCH_REQUIRE_GPIOLIB
572 select GENERIC_CLOCKEVENTS
573 select NEED_MACH_MEMORY_H
575 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
576 System-on-Chip devices.
579 bool "Nuvoton W90X900 CPU"
580 select ARCH_REQUIRE_GPIOLIB
584 select GENERIC_CLOCKEVENTS
586 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
587 At present, the w90x900 has been renamed nuc900, regarding
588 the ARM series product line, you can login the following
589 link address to know more.
591 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
592 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
596 select ARCH_REQUIRE_GPIOLIB
601 select GENERIC_CLOCKEVENTS
605 Support for the NXP LPC32XX family of processors
608 bool "PXA2xx/PXA3xx-based"
611 select ARCH_REQUIRE_GPIOLIB
612 select ARM_CPU_SUSPEND if PM
618 select GENERIC_CLOCKEVENTS
622 select MULTI_IRQ_HANDLER
626 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
632 select ARCH_MAY_HAVE_PC_FDC
633 select ARCH_SPARSEMEM_ENABLE
634 select ARCH_USES_GETTIMEOFFSET
638 select HAVE_PATA_PLATFORM
640 select NEED_MACH_IO_H
641 select NEED_MACH_MEMORY_H
645 On the Acorn Risc-PC, Linux can support the internal IDE disk and
646 CD-ROM interface, serial and parallel port, and the floppy drive.
651 select ARCH_REQUIRE_GPIOLIB
652 select ARCH_SPARSEMEM_ENABLE
657 select GENERIC_CLOCKEVENTS
661 select MULTI_IRQ_HANDLER
662 select NEED_MACH_MEMORY_H
665 Support for StrongARM 11x0 based boards.
668 bool "Samsung S3C24XX SoCs"
669 select ARCH_REQUIRE_GPIOLIB
672 select CLKSRC_SAMSUNG_PWM
673 select GENERIC_CLOCKEVENTS
675 select HAVE_S3C2410_I2C if I2C
676 select HAVE_S3C2410_WATCHDOG if WATCHDOG
677 select HAVE_S3C_RTC if RTC_CLASS
678 select MULTI_IRQ_HANDLER
679 select NEED_MACH_IO_H
682 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
683 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
684 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
685 Samsung SMDK2410 development board (and derivatives).
688 bool "Samsung S3C64XX"
689 select ARCH_REQUIRE_GPIOLIB
694 select CLKSRC_SAMSUNG_PWM
695 select COMMON_CLK_SAMSUNG
697 select GENERIC_CLOCKEVENTS
699 select HAVE_S3C2410_I2C if I2C
700 select HAVE_S3C2410_WATCHDOG if WATCHDOG
704 select PM_GENERIC_DOMAINS if PM
706 select S3C_GPIO_TRACK
708 select SAMSUNG_WAKEMASK
709 select SAMSUNG_WDT_RESET
711 Samsung S3C64XX series based systems
715 select ARCH_HAS_HOLES_MEMORYMODEL
716 select ARCH_REQUIRE_GPIOLIB
718 select GENERIC_ALLOCATOR
719 select GENERIC_CLOCKEVENTS
720 select GENERIC_IRQ_CHIP
725 Support for TI's DaVinci platform.
730 select ARCH_HAS_HOLES_MEMORYMODEL
732 select ARCH_REQUIRE_GPIOLIB
735 select GENERIC_CLOCKEVENTS
736 select GENERIC_IRQ_CHIP
739 select MULTI_IRQ_HANDLER
740 select NEED_MACH_IO_H if PCCARD
741 select NEED_MACH_MEMORY_H
744 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
748 menu "Multiple platform selection"
749 depends on ARCH_MULTIPLATFORM
751 comment "CPU Core family selection"
754 bool "ARMv4 based platforms (FA526)"
755 depends on !ARCH_MULTI_V6_V7
756 select ARCH_MULTI_V4_V5
759 config ARCH_MULTI_V4T
760 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
761 depends on !ARCH_MULTI_V6_V7
762 select ARCH_MULTI_V4_V5
763 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
764 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
765 CPU_ARM925T || CPU_ARM940T)
768 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
769 depends on !ARCH_MULTI_V6_V7
770 select ARCH_MULTI_V4_V5
771 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
772 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
773 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
775 config ARCH_MULTI_V4_V5
779 bool "ARMv6 based platforms (ARM11)"
780 select ARCH_MULTI_V6_V7
784 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
786 select ARCH_MULTI_V6_V7
790 config ARCH_MULTI_V6_V7
792 select MIGHT_HAVE_CACHE_L2X0
794 config ARCH_MULTI_CPU_AUTO
795 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
801 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
804 select ARM_GIC_V2M if PCI_MSI
807 select HAVE_ARM_ARCH_TIMER
810 # This is sorted alphabetically by mach-* pathname. However, plat-*
811 # Kconfigs may be included either alphabetically (according to the
812 # plat- suffix) or along side the corresponding mach-* source.
814 source "arch/arm/mach-mvebu/Kconfig"
816 source "arch/arm/mach-alpine/Kconfig"
818 source "arch/arm/mach-asm9260/Kconfig"
820 source "arch/arm/mach-at91/Kconfig"
822 source "arch/arm/mach-axxia/Kconfig"
824 source "arch/arm/mach-bcm/Kconfig"
826 source "arch/arm/mach-berlin/Kconfig"
828 source "arch/arm/mach-clps711x/Kconfig"
830 source "arch/arm/mach-cns3xxx/Kconfig"
832 source "arch/arm/mach-davinci/Kconfig"
834 source "arch/arm/mach-digicolor/Kconfig"
836 source "arch/arm/mach-dove/Kconfig"
838 source "arch/arm/mach-ep93xx/Kconfig"
840 source "arch/arm/mach-footbridge/Kconfig"
842 source "arch/arm/mach-gemini/Kconfig"
844 source "arch/arm/mach-highbank/Kconfig"
846 source "arch/arm/mach-hisi/Kconfig"
848 source "arch/arm/mach-integrator/Kconfig"
850 source "arch/arm/mach-iop32x/Kconfig"
852 source "arch/arm/mach-iop33x/Kconfig"
854 source "arch/arm/mach-iop13xx/Kconfig"
856 source "arch/arm/mach-ixp4xx/Kconfig"
858 source "arch/arm/mach-keystone/Kconfig"
860 source "arch/arm/mach-ks8695/Kconfig"
862 source "arch/arm/mach-meson/Kconfig"
864 source "arch/arm/mach-moxart/Kconfig"
866 source "arch/arm/mach-mv78xx0/Kconfig"
868 source "arch/arm/mach-imx/Kconfig"
870 source "arch/arm/mach-mediatek/Kconfig"
872 source "arch/arm/mach-mxs/Kconfig"
874 source "arch/arm/mach-netx/Kconfig"
876 source "arch/arm/mach-nomadik/Kconfig"
878 source "arch/arm/mach-nspire/Kconfig"
880 source "arch/arm/plat-omap/Kconfig"
882 source "arch/arm/mach-omap1/Kconfig"
884 source "arch/arm/mach-omap2/Kconfig"
886 source "arch/arm/mach-orion5x/Kconfig"
888 source "arch/arm/mach-picoxcell/Kconfig"
890 source "arch/arm/mach-pxa/Kconfig"
891 source "arch/arm/plat-pxa/Kconfig"
893 source "arch/arm/mach-mmp/Kconfig"
895 source "arch/arm/mach-qcom/Kconfig"
897 source "arch/arm/mach-realview/Kconfig"
899 source "arch/arm/mach-rockchip/Kconfig"
901 source "arch/arm/mach-sa1100/Kconfig"
903 source "arch/arm/mach-socfpga/Kconfig"
905 source "arch/arm/mach-spear/Kconfig"
907 source "arch/arm/mach-sti/Kconfig"
909 source "arch/arm/mach-s3c24xx/Kconfig"
911 source "arch/arm/mach-s3c64xx/Kconfig"
913 source "arch/arm/mach-s5pv210/Kconfig"
915 source "arch/arm/mach-exynos/Kconfig"
916 source "arch/arm/plat-samsung/Kconfig"
918 source "arch/arm/mach-shmobile/Kconfig"
920 source "arch/arm/mach-sunxi/Kconfig"
922 source "arch/arm/mach-prima2/Kconfig"
924 source "arch/arm/mach-tegra/Kconfig"
926 source "arch/arm/mach-u300/Kconfig"
928 source "arch/arm/mach-uniphier/Kconfig"
930 source "arch/arm/mach-ux500/Kconfig"
932 source "arch/arm/mach-versatile/Kconfig"
934 source "arch/arm/mach-vexpress/Kconfig"
935 source "arch/arm/plat-versatile/Kconfig"
937 source "arch/arm/mach-vt8500/Kconfig"
939 source "arch/arm/mach-w90x900/Kconfig"
941 source "arch/arm/mach-zx/Kconfig"
943 source "arch/arm/mach-zynq/Kconfig"
945 # ARMv7-M architecture
947 bool "Energy Micro efm32"
948 depends on ARM_SINGLE_ARMV7M
949 select ARCH_REQUIRE_GPIOLIB
951 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
955 bool "NXP LPC18xx/LPC43xx"
956 depends on ARM_SINGLE_ARMV7M
957 select ARCH_HAS_RESET_CONTROLLER
959 select CLKSRC_LPC32XX
962 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
963 high performance microcontrollers.
966 bool "STMicrolectronics STM32"
967 depends on ARM_SINGLE_ARMV7M
968 select ARCH_HAS_RESET_CONTROLLER
969 select ARMV7M_SYSTICK
971 select RESET_CONTROLLER
973 Support for STMicroelectronics STM32 processors.
975 # Definitions to make life easier
981 select GENERIC_CLOCKEVENTS
987 select GENERIC_IRQ_CHIP
990 config PLAT_ORION_LEGACY
997 config PLAT_VERSATILE
1000 source "arch/arm/firmware/Kconfig"
1002 source arch/arm/mm/Kconfig
1005 bool "Enable iWMMXt support"
1006 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1007 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1009 Enable support for iWMMXt context switching at run time if
1010 running on a CPU that supports it.
1012 config MULTI_IRQ_HANDLER
1015 Allow each machine to specify it's own IRQ handler at run time.
1018 source "arch/arm/Kconfig-nommu"
1021 config PJ4B_ERRATA_4742
1022 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1023 depends on CPU_PJ4B && MACH_ARMADA_370
1026 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1027 Event (WFE) IDLE states, a specific timing sensitivity exists between
1028 the retiring WFI/WFE instructions and the newly issued subsequent
1029 instructions. This sensitivity can result in a CPU hang scenario.
1031 The software must insert either a Data Synchronization Barrier (DSB)
1032 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1035 config ARM_ERRATA_326103
1036 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1039 Executing a SWP instruction to read-only memory does not set bit 11
1040 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1041 treat the access as a read, preventing a COW from occurring and
1042 causing the faulting task to livelock.
1044 config ARM_ERRATA_411920
1045 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1046 depends on CPU_V6 || CPU_V6K
1048 Invalidation of the Instruction Cache operation can
1049 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1050 It does not affect the MPCore. This option enables the ARM Ltd.
1051 recommended workaround.
1053 config ARM_ERRATA_430973
1054 bool "ARM errata: Stale prediction on replaced interworking branch"
1057 This option enables the workaround for the 430973 Cortex-A8
1058 r1p* erratum. If a code sequence containing an ARM/Thumb
1059 interworking branch is replaced with another code sequence at the
1060 same virtual address, whether due to self-modifying code or virtual
1061 to physical address re-mapping, Cortex-A8 does not recover from the
1062 stale interworking branch prediction. This results in Cortex-A8
1063 executing the new code sequence in the incorrect ARM or Thumb state.
1064 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1065 and also flushes the branch target cache at every context switch.
1066 Note that setting specific bits in the ACTLR register may not be
1067 available in non-secure mode.
1069 config ARM_ERRATA_458693
1070 bool "ARM errata: Processor deadlock when a false hazard is created"
1072 depends on !ARCH_MULTIPLATFORM
1074 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1075 erratum. For very specific sequences of memory operations, it is
1076 possible for a hazard condition intended for a cache line to instead
1077 be incorrectly associated with a different cache line. This false
1078 hazard might then cause a processor deadlock. The workaround enables
1079 the L1 caching of the NEON accesses and disables the PLD instruction
1080 in the ACTLR register. Note that setting specific bits in the ACTLR
1081 register may not be available in non-secure mode.
1083 config ARM_ERRATA_460075
1084 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1086 depends on !ARCH_MULTIPLATFORM
1088 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1089 erratum. Any asynchronous access to the L2 cache may encounter a
1090 situation in which recent store transactions to the L2 cache are lost
1091 and overwritten with stale memory contents from external memory. The
1092 workaround disables the write-allocate mode for the L2 cache via the
1093 ACTLR register. Note that setting specific bits in the ACTLR register
1094 may not be available in non-secure mode.
1096 config ARM_ERRATA_742230
1097 bool "ARM errata: DMB operation may be faulty"
1098 depends on CPU_V7 && SMP
1099 depends on !ARCH_MULTIPLATFORM
1101 This option enables the workaround for the 742230 Cortex-A9
1102 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1103 between two write operations may not ensure the correct visibility
1104 ordering of the two writes. This workaround sets a specific bit in
1105 the diagnostic register of the Cortex-A9 which causes the DMB
1106 instruction to behave as a DSB, ensuring the correct behaviour of
1109 config ARM_ERRATA_742231
1110 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1111 depends on CPU_V7 && SMP
1112 depends on !ARCH_MULTIPLATFORM
1114 This option enables the workaround for the 742231 Cortex-A9
1115 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1116 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1117 accessing some data located in the same cache line, may get corrupted
1118 data due to bad handling of the address hazard when the line gets
1119 replaced from one of the CPUs at the same time as another CPU is
1120 accessing it. This workaround sets specific bits in the diagnostic
1121 register of the Cortex-A9 which reduces the linefill issuing
1122 capabilities of the processor.
1124 config ARM_ERRATA_643719
1125 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1126 depends on CPU_V7 && SMP
1129 This option enables the workaround for the 643719 Cortex-A9 (prior to
1130 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1131 register returns zero when it should return one. The workaround
1132 corrects this value, ensuring cache maintenance operations which use
1133 it behave as intended and avoiding data corruption.
1135 config ARM_ERRATA_720789
1136 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1139 This option enables the workaround for the 720789 Cortex-A9 (prior to
1140 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1141 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1142 As a consequence of this erratum, some TLB entries which should be
1143 invalidated are not, resulting in an incoherency in the system page
1144 tables. The workaround changes the TLB flushing routines to invalidate
1145 entries regardless of the ASID.
1147 config ARM_ERRATA_743622
1148 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1150 depends on !ARCH_MULTIPLATFORM
1152 This option enables the workaround for the 743622 Cortex-A9
1153 (r2p*) erratum. Under very rare conditions, a faulty
1154 optimisation in the Cortex-A9 Store Buffer may lead to data
1155 corruption. This workaround sets a specific bit in the diagnostic
1156 register of the Cortex-A9 which disables the Store Buffer
1157 optimisation, preventing the defect from occurring. This has no
1158 visible impact on the overall performance or power consumption of the
1161 config ARM_ERRATA_751472
1162 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1164 depends on !ARCH_MULTIPLATFORM
1166 This option enables the workaround for the 751472 Cortex-A9 (prior
1167 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1168 completion of a following broadcasted operation if the second
1169 operation is received by a CPU before the ICIALLUIS has completed,
1170 potentially leading to corrupted entries in the cache or TLB.
1172 config ARM_ERRATA_754322
1173 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1176 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1177 r3p*) erratum. A speculative memory access may cause a page table walk
1178 which starts prior to an ASID switch but completes afterwards. This
1179 can populate the micro-TLB with a stale entry which may be hit with
1180 the new ASID. This workaround places two dsb instructions in the mm
1181 switching code so that no page table walks can cross the ASID switch.
1183 config ARM_ERRATA_754327
1184 bool "ARM errata: no automatic Store Buffer drain"
1185 depends on CPU_V7 && SMP
1187 This option enables the workaround for the 754327 Cortex-A9 (prior to
1188 r2p0) erratum. The Store Buffer does not have any automatic draining
1189 mechanism and therefore a livelock may occur if an external agent
1190 continuously polls a memory location waiting to observe an update.
1191 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1192 written polling loops from denying visibility of updates to memory.
1194 config ARM_ERRATA_364296
1195 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1198 This options enables the workaround for the 364296 ARM1136
1199 r0p2 erratum (possible cache data corruption with
1200 hit-under-miss enabled). It sets the undocumented bit 31 in
1201 the auxiliary control register and the FI bit in the control
1202 register, thus disabling hit-under-miss without putting the
1203 processor into full low interrupt latency mode. ARM11MPCore
1206 config ARM_ERRATA_764369
1207 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1208 depends on CPU_V7 && SMP
1210 This option enables the workaround for erratum 764369
1211 affecting Cortex-A9 MPCore with two or more processors (all
1212 current revisions). Under certain timing circumstances, a data
1213 cache line maintenance operation by MVA targeting an Inner
1214 Shareable memory region may fail to proceed up to either the
1215 Point of Coherency or to the Point of Unification of the
1216 system. This workaround adds a DSB instruction before the
1217 relevant cache maintenance functions and sets a specific bit
1218 in the diagnostic control register of the SCU.
1220 config ARM_ERRATA_775420
1221 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1224 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1225 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1226 operation aborts with MMU exception, it might cause the processor
1227 to deadlock. This workaround puts DSB before executing ISB if
1228 an abort may occur on cache maintenance.
1230 config ARM_ERRATA_798181
1231 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1232 depends on CPU_V7 && SMP
1234 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1235 adequately shooting down all use of the old entries. This
1236 option enables the Linux kernel workaround for this erratum
1237 which sends an IPI to the CPUs that are running the same ASID
1238 as the one being invalidated.
1240 config ARM_ERRATA_773022
1241 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1244 This option enables the workaround for the 773022 Cortex-A15
1245 (up to r0p4) erratum. In certain rare sequences of code, the
1246 loop buffer may deliver incorrect instructions. This
1247 workaround disables the loop buffer to avoid the erratum.
1251 source "arch/arm/common/Kconfig"
1258 Find out whether you have ISA slots on your motherboard. ISA is the
1259 name of a bus system, i.e. the way the CPU talks to the other stuff
1260 inside your box. Other bus systems are PCI, EISA, MicroChannel
1261 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1262 newer boards don't support it. If you have ISA, say Y, otherwise N.
1264 # Select ISA DMA controller support
1269 # Select ISA DMA interface
1274 bool "PCI support" if MIGHT_HAVE_PCI
1276 Find out whether you have a PCI motherboard. PCI is the name of a
1277 bus system, i.e. the way the CPU talks to the other stuff inside
1278 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1279 VESA. If you have PCI, say Y, otherwise N.
1285 config PCI_DOMAINS_GENERIC
1286 def_bool PCI_DOMAINS
1288 config PCI_NANOENGINE
1289 bool "BSE nanoEngine PCI support"
1290 depends on SA1100_NANOENGINE
1292 Enable PCI on the BSE nanoEngine board.
1297 config PCI_HOST_ITE8152
1299 depends on PCI && MACH_ARMCORE
1303 source "drivers/pci/Kconfig"
1304 source "drivers/pci/pcie/Kconfig"
1306 source "drivers/pcmcia/Kconfig"
1310 menu "Kernel Features"
1315 This option should be selected by machines which have an SMP-
1318 The only effect of this option is to make the SMP-related
1319 options available to the user for configuration.
1322 bool "Symmetric Multi-Processing"
1323 depends on CPU_V6K || CPU_V7
1324 depends on GENERIC_CLOCKEVENTS
1326 depends on MMU || ARM_MPU
1329 This enables support for systems with more than one CPU. If you have
1330 a system with only one CPU, say N. If you have a system with more
1331 than one CPU, say Y.
1333 If you say N here, the kernel will run on uni- and multiprocessor
1334 machines, but will use only one CPU of a multiprocessor machine. If
1335 you say Y here, the kernel will run on many, but not all,
1336 uniprocessor machines. On a uniprocessor machine, the kernel
1337 will run faster if you say N here.
1339 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1340 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1341 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1343 If you don't know what to do here, say N.
1346 bool "Allow booting SMP kernel on uniprocessor systems"
1347 depends on SMP && !XIP_KERNEL && MMU
1350 SMP kernels contain instructions which fail on non-SMP processors.
1351 Enabling this option allows the kernel to modify itself to make
1352 these instructions safe. Disabling it allows about 1K of space
1355 If you don't know what to do here, say Y.
1357 config ARM_CPU_TOPOLOGY
1358 bool "Support cpu topology definition"
1359 depends on SMP && CPU_V7
1362 Support ARM cpu topology definition. The MPIDR register defines
1363 affinity between processors which is then used to describe the cpu
1364 topology of an ARM System.
1367 bool "Multi-core scheduler support"
1368 depends on ARM_CPU_TOPOLOGY
1370 Multi-core scheduler support improves the CPU scheduler's decision
1371 making when dealing with multi-core CPU chips at a cost of slightly
1372 increased overhead in some places. If unsure say N here.
1375 bool "SMT scheduler support"
1376 depends on ARM_CPU_TOPOLOGY
1378 Improves the CPU scheduler's decision making when dealing with
1379 MultiThreading at a cost of slightly increased overhead in some
1380 places. If unsure say N here.
1385 This option enables support for the ARM system coherency unit
1387 config HAVE_ARM_ARCH_TIMER
1388 bool "Architected timer support"
1390 select ARM_ARCH_TIMER
1391 select GENERIC_CLOCKEVENTS
1393 This option enables support for the ARM architected timer
1397 select CLKSRC_OF if OF
1399 This options enables support for the ARM timer and watchdog unit
1402 bool "Multi-Cluster Power Management"
1403 depends on CPU_V7 && SMP
1405 This option provides the common power management infrastructure
1406 for (multi-)cluster based systems, such as big.LITTLE based
1409 config MCPM_QUAD_CLUSTER
1413 To avoid wasting resources unnecessarily, MCPM only supports up
1414 to 2 clusters by default.
1415 Platforms with 3 or 4 clusters that use MCPM must select this
1416 option to allow the additional clusters to be managed.
1419 bool "big.LITTLE support (Experimental)"
1420 depends on CPU_V7 && SMP
1423 This option enables support selections for the big.LITTLE
1424 system architecture.
1427 bool "big.LITTLE switcher support"
1428 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1429 select ARM_CPU_SUSPEND
1432 The big.LITTLE "switcher" provides the core functionality to
1433 transparently handle transition between a cluster of A15's
1434 and a cluster of A7's in a big.LITTLE system.
1436 config BL_SWITCHER_DUMMY_IF
1437 tristate "Simple big.LITTLE switcher user interface"
1438 depends on BL_SWITCHER && DEBUG_KERNEL
1440 This is a simple and dummy char dev interface to control
1441 the big.LITTLE switcher core code. It is meant for
1442 debugging purposes only.
1445 prompt "Memory split"
1449 Select the desired split between kernel and user memory.
1451 If you are not absolutely sure what you are doing, leave this
1455 bool "3G/1G user/kernel split"
1456 config VMSPLIT_3G_OPT
1457 bool "3G/1G user/kernel split (for full 1G low memory)"
1459 bool "2G/2G user/kernel split"
1461 bool "1G/3G user/kernel split"
1466 default PHYS_OFFSET if !MMU
1467 default 0x40000000 if VMSPLIT_1G
1468 default 0x80000000 if VMSPLIT_2G
1469 default 0xB0000000 if VMSPLIT_3G_OPT
1473 int "Maximum number of CPUs (2-32)"
1479 bool "Support for hot-pluggable CPUs"
1482 Say Y here to experiment with turning CPUs off and on. CPUs
1483 can be controlled through /sys/devices/system/cpu.
1486 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1487 depends on HAVE_ARM_SMCCC
1490 Say Y here if you want Linux to communicate with system firmware
1491 implementing the PSCI specification for CPU-centric power
1492 management operations described in ARM document number ARM DEN
1493 0022A ("Power State Coordination Interface System Software on
1496 # The GPIO number here must be sorted by descending number. In case of
1497 # a multiplatform kernel, we just want the highest value required by the
1498 # selected platforms.
1501 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1503 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1504 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1505 default 416 if ARCH_SUNXI
1506 default 392 if ARCH_U8500
1507 default 352 if ARCH_VT8500
1508 default 288 if ARCH_ROCKCHIP
1509 default 264 if MACH_H4700
1512 Maximum number of GPIOs in the system.
1514 If unsure, leave the default value.
1516 source kernel/Kconfig.preempt
1520 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1521 ARCH_S5PV210 || ARCH_EXYNOS4
1522 default 128 if SOC_AT91RM9200
1526 depends on HZ_FIXED = 0
1527 prompt "Timer frequency"
1551 default HZ_FIXED if HZ_FIXED != 0
1552 default 100 if HZ_100
1553 default 200 if HZ_200
1554 default 250 if HZ_250
1555 default 300 if HZ_300
1556 default 500 if HZ_500
1560 def_bool HIGH_RES_TIMERS
1562 config THUMB2_KERNEL
1563 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1564 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1565 default y if CPU_THUMBONLY
1567 select ARM_ASM_UNIFIED
1570 By enabling this option, the kernel will be compiled in
1571 Thumb-2 mode. A compiler/assembler that understand the unified
1572 ARM-Thumb syntax is needed.
1576 config THUMB2_AVOID_R_ARM_THM_JUMP11
1577 bool "Work around buggy Thumb-2 short branch relocations in gas"
1578 depends on THUMB2_KERNEL && MODULES
1581 Various binutils versions can resolve Thumb-2 branches to
1582 locally-defined, preemptible global symbols as short-range "b.n"
1583 branch instructions.
1585 This is a problem, because there's no guarantee the final
1586 destination of the symbol, or any candidate locations for a
1587 trampoline, are within range of the branch. For this reason, the
1588 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1589 relocation in modules at all, and it makes little sense to add
1592 The symptom is that the kernel fails with an "unsupported
1593 relocation" error when loading some modules.
1595 Until fixed tools are available, passing
1596 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1597 code which hits this problem, at the cost of a bit of extra runtime
1598 stack usage in some cases.
1600 The problem is described in more detail at:
1601 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1603 Only Thumb-2 kernels are affected.
1605 Unless you are sure your tools don't have this problem, say Y.
1607 config ARM_ASM_UNIFIED
1610 config ARM_PATCH_IDIV
1611 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1612 depends on CPU_32v7 && !XIP_KERNEL
1615 The ARM compiler inserts calls to __aeabi_idiv() and
1616 __aeabi_uidiv() when it needs to perform division on signed
1617 and unsigned integers. Some v7 CPUs have support for the sdiv
1618 and udiv instructions that can be used to implement those
1621 Enabling this option allows the kernel to modify itself to
1622 replace the first two instructions of these library functions
1623 with the sdiv or udiv plus "bx lr" instructions when the CPU
1624 it is running on supports them. Typically this will be faster
1625 and less power intensive than running the original library
1626 code to do integer division.
1629 bool "Use the ARM EABI to compile the kernel"
1631 This option allows for the kernel to be compiled using the latest
1632 ARM ABI (aka EABI). This is only useful if you are using a user
1633 space environment that is also compiled with EABI.
1635 Since there are major incompatibilities between the legacy ABI and
1636 EABI, especially with regard to structure member alignment, this
1637 option also changes the kernel syscall calling convention to
1638 disambiguate both ABIs and allow for backward compatibility support
1639 (selected with CONFIG_OABI_COMPAT).
1641 To use this you need GCC version 4.0.0 or later.
1644 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1645 depends on AEABI && !THUMB2_KERNEL
1647 This option preserves the old syscall interface along with the
1648 new (ARM EABI) one. It also provides a compatibility layer to
1649 intercept syscalls that have structure arguments which layout
1650 in memory differs between the legacy ABI and the new ARM EABI
1651 (only for non "thumb" binaries). This option adds a tiny
1652 overhead to all syscalls and produces a slightly larger kernel.
1654 The seccomp filter system will not be available when this is
1655 selected, since there is no way yet to sensibly distinguish
1656 between calling conventions during filtering.
1658 If you know you'll be using only pure EABI user space then you
1659 can say N here. If this option is not selected and you attempt
1660 to execute a legacy ABI binary then the result will be
1661 UNPREDICTABLE (in fact it can be predicted that it won't work
1662 at all). If in doubt say N.
1664 config ARCH_HAS_HOLES_MEMORYMODEL
1667 config ARCH_SPARSEMEM_ENABLE
1670 config ARCH_SPARSEMEM_DEFAULT
1671 def_bool ARCH_SPARSEMEM_ENABLE
1673 config ARCH_SELECT_MEMORY_MODEL
1674 def_bool ARCH_SPARSEMEM_ENABLE
1676 config HAVE_ARCH_PFN_VALID
1677 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1679 config HAVE_GENERIC_RCU_GUP
1684 bool "High Memory Support"
1687 The address space of ARM processors is only 4 Gigabytes large
1688 and it has to accommodate user address space, kernel address
1689 space as well as some memory mapped IO. That means that, if you
1690 have a large amount of physical memory and/or IO, not all of the
1691 memory can be "permanently mapped" by the kernel. The physical
1692 memory that is not permanently mapped is called "high memory".
1694 Depending on the selected kernel/user memory split, minimum
1695 vmalloc space and actual amount of RAM, you may not need this
1696 option which should result in a slightly faster kernel.
1701 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1705 The VM uses one page of physical memory for each page table.
1706 For systems with a lot of processes, this can use a lot of
1707 precious low memory, eventually leading to low memory being
1708 consumed by page tables. Setting this option will allow
1709 user-space 2nd level page tables to reside in high memory.
1711 config CPU_SW_DOMAIN_PAN
1712 bool "Enable use of CPU domains to implement privileged no-access"
1713 depends on MMU && !ARM_LPAE
1716 Increase kernel security by ensuring that normal kernel accesses
1717 are unable to access userspace addresses. This can help prevent
1718 use-after-free bugs becoming an exploitable privilege escalation
1719 by ensuring that magic values (such as LIST_POISON) will always
1720 fault when dereferenced.
1722 CPUs with low-vector mappings use a best-efforts implementation.
1723 Their lower 1MB needs to remain accessible for the vectors, but
1724 the remainder of userspace will become appropriately inaccessible.
1726 config HW_PERF_EVENTS
1730 config SYS_SUPPORTS_HUGETLBFS
1734 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1738 config ARCH_WANT_GENERAL_HUGETLB
1741 config ARM_MODULE_PLTS
1742 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1745 Allocate PLTs when loading modules so that jumps and calls whose
1746 targets are too far away for their relative offsets to be encoded
1747 in the instructions themselves can be bounced via veneers in the
1748 module's PLT. This allows modules to be allocated in the generic
1749 vmalloc area after the dedicated module memory area has been
1750 exhausted. The modules will use slightly more memory, but after
1751 rounding up to page size, the actual memory footprint is usually
1754 Say y if you are getting out of memory errors while loading modules
1758 config FORCE_MAX_ZONEORDER
1759 int "Maximum zone order"
1760 default "12" if SOC_AM33XX
1761 default "9" if SA1111 || ARCH_EFM32
1764 The kernel memory allocator divides physically contiguous memory
1765 blocks into "zones", where each zone is a power of two number of
1766 pages. This option selects the largest power of two that the kernel
1767 keeps in the memory allocator. If you need to allocate very large
1768 blocks of physically contiguous memory, then you may need to
1769 increase this value.
1771 This config option is actually maximum order plus one. For example,
1772 a value of 11 means that the largest free memory block is 2^10 pages.
1774 config ALIGNMENT_TRAP
1776 depends on CPU_CP15_MMU
1777 default y if !ARCH_EBSA110
1778 select HAVE_PROC_CPU if PROC_FS
1780 ARM processors cannot fetch/store information which is not
1781 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1782 address divisible by 4. On 32-bit ARM processors, these non-aligned
1783 fetch/store instructions will be emulated in software if you say
1784 here, which has a severe performance impact. This is necessary for
1785 correct operation of some network protocols. With an IP-only
1786 configuration it is safe to say N, otherwise say Y.
1788 config UACCESS_WITH_MEMCPY
1789 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1791 default y if CPU_FEROCEON
1793 Implement faster copy_to_user and clear_user methods for CPU
1794 cores where a 8-word STM instruction give significantly higher
1795 memory write throughput than a sequence of individual 32bit stores.
1797 A possible side effect is a slight increase in scheduling latency
1798 between threads sharing the same address space if they invoke
1799 such copy operations with large buffers.
1801 However, if the CPU data cache is using a write-allocate mode,
1802 this option is unlikely to provide any performance gain.
1806 prompt "Enable seccomp to safely compute untrusted bytecode"
1808 This kernel feature is useful for number crunching applications
1809 that may need to compute untrusted bytecode during their
1810 execution. By using pipes or other transports made available to
1811 the process as file descriptors supporting the read/write
1812 syscalls, it's possible to isolate those applications in
1813 their own address space using seccomp. Once seccomp is
1814 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1815 and the task is only allowed to execute a few safe syscalls
1816 defined by each seccomp mode.
1829 bool "Xen guest support on ARM"
1830 depends on ARM && AEABI && OF
1831 depends on CPU_V7 && !CPU_V6
1832 depends on !GENERIC_ATOMIC64
1834 select ARCH_DMA_ADDR_T_64BIT
1838 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1845 bool "Flattened Device Tree support"
1849 Include support for flattened device tree machine descriptions.
1852 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1855 This is the traditional way of passing data to the kernel at boot
1856 time. If you are solely relying on the flattened device tree (or
1857 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1858 to remove ATAGS support from your kernel binary. If unsure,
1861 config DEPRECATED_PARAM_STRUCT
1862 bool "Provide old way to pass kernel parameters"
1865 This was deprecated in 2001 and announced to live on for 5 years.
1866 Some old boot loaders still use this way.
1868 # Compressed boot loader in ROM. Yes, we really want to ask about
1869 # TEXT and BSS so we preserve their values in the config files.
1870 config ZBOOT_ROM_TEXT
1871 hex "Compressed ROM boot loader base address"
1874 The physical address at which the ROM-able zImage is to be
1875 placed in the target. Platforms which normally make use of
1876 ROM-able zImage formats normally set this to a suitable
1877 value in their defconfig file.
1879 If ZBOOT_ROM is not enabled, this has no effect.
1881 config ZBOOT_ROM_BSS
1882 hex "Compressed ROM boot loader BSS address"
1885 The base address of an area of read/write memory in the target
1886 for the ROM-able zImage which must be available while the
1887 decompressor is running. It must be large enough to hold the
1888 entire decompressed kernel plus an additional 128 KiB.
1889 Platforms which normally make use of ROM-able zImage formats
1890 normally set this to a suitable value in their defconfig file.
1892 If ZBOOT_ROM is not enabled, this has no effect.
1895 bool "Compressed boot loader in ROM/flash"
1896 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1897 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1899 Say Y here if you intend to execute your compressed kernel image
1900 (zImage) directly from ROM or flash. If unsure, say N.
1902 config ARM_APPENDED_DTB
1903 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1906 With this option, the boot code will look for a device tree binary
1907 (DTB) appended to zImage
1908 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1910 This is meant as a backward compatibility convenience for those
1911 systems with a bootloader that can't be upgraded to accommodate
1912 the documented boot protocol using a device tree.
1914 Beware that there is very little in terms of protection against
1915 this option being confused by leftover garbage in memory that might
1916 look like a DTB header after a reboot if no actual DTB is appended
1917 to zImage. Do not leave this option active in a production kernel
1918 if you don't intend to always append a DTB. Proper passing of the
1919 location into r2 of a bootloader provided DTB is always preferable
1922 config ARM_ATAG_DTB_COMPAT
1923 bool "Supplement the appended DTB with traditional ATAG information"
1924 depends on ARM_APPENDED_DTB
1926 Some old bootloaders can't be updated to a DTB capable one, yet
1927 they provide ATAGs with memory configuration, the ramdisk address,
1928 the kernel cmdline string, etc. Such information is dynamically
1929 provided by the bootloader and can't always be stored in a static
1930 DTB. To allow a device tree enabled kernel to be used with such
1931 bootloaders, this option allows zImage to extract the information
1932 from the ATAG list and store it at run time into the appended DTB.
1935 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1936 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1938 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1939 bool "Use bootloader kernel arguments if available"
1941 Uses the command-line options passed by the boot loader instead of
1942 the device tree bootargs property. If the boot loader doesn't provide
1943 any, the device tree bootargs property will be used.
1945 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1946 bool "Extend with bootloader kernel arguments"
1948 The command-line arguments provided by the boot loader will be
1949 appended to the the device tree bootargs property.
1954 string "Default kernel command string"
1957 On some architectures (EBSA110 and CATS), there is currently no way
1958 for the boot loader to pass arguments to the kernel. For these
1959 architectures, you should supply some command-line options at build
1960 time by entering them here. As a minimum, you should specify the
1961 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1964 prompt "Kernel command line type" if CMDLINE != ""
1965 default CMDLINE_FROM_BOOTLOADER
1968 config CMDLINE_FROM_BOOTLOADER
1969 bool "Use bootloader kernel arguments if available"
1971 Uses the command-line options passed by the boot loader. If
1972 the boot loader doesn't provide any, the default kernel command
1973 string provided in CMDLINE will be used.
1975 config CMDLINE_EXTEND
1976 bool "Extend bootloader kernel arguments"
1978 The command-line arguments provided by the boot loader will be
1979 appended to the default kernel command string.
1981 config CMDLINE_FORCE
1982 bool "Always use the default kernel command string"
1984 Always use the default kernel command string, even if the boot
1985 loader passes other arguments to the kernel.
1986 This is useful if you cannot or don't want to change the
1987 command-line options your boot loader passes to the kernel.
1991 bool "Kernel Execute-In-Place from ROM"
1992 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1994 Execute-In-Place allows the kernel to run from non-volatile storage
1995 directly addressable by the CPU, such as NOR flash. This saves RAM
1996 space since the text section of the kernel is not loaded from flash
1997 to RAM. Read-write sections, such as the data section and stack,
1998 are still copied to RAM. The XIP kernel is not compressed since
1999 it has to run directly from flash, so it will take more space to
2000 store it. The flash address used to link the kernel object files,
2001 and for storing it, is configuration dependent. Therefore, if you
2002 say Y here, you must know the proper physical address where to
2003 store the kernel image depending on your own flash memory usage.
2005 Also note that the make target becomes "make xipImage" rather than
2006 "make zImage" or "make Image". The final kernel binary to put in
2007 ROM memory will be arch/arm/boot/xipImage.
2011 config XIP_PHYS_ADDR
2012 hex "XIP Kernel Physical Location"
2013 depends on XIP_KERNEL
2014 default "0x00080000"
2016 This is the physical address in your flash memory the kernel will
2017 be linked for and stored to. This address is dependent on your
2021 bool "Kexec system call (EXPERIMENTAL)"
2022 depends on (!SMP || PM_SLEEP_SMP)
2026 kexec is a system call that implements the ability to shutdown your
2027 current kernel, and to start another kernel. It is like a reboot
2028 but it is independent of the system firmware. And like a reboot
2029 you can start any kernel with it, not just Linux.
2031 It is an ongoing process to be certain the hardware in a machine
2032 is properly shutdown, so do not be surprised if this code does not
2033 initially work for you.
2036 bool "Export atags in procfs"
2037 depends on ATAGS && KEXEC
2040 Should the atags used to boot the kernel be exported in an "atags"
2041 file in procfs. Useful with kexec.
2044 bool "Build kdump crash kernel (EXPERIMENTAL)"
2046 Generate crash dump after being started by kexec. This should
2047 be normally only set in special crash dump kernels which are
2048 loaded in the main kernel with kexec-tools into a specially
2049 reserved region and then later executed after a crash by
2050 kdump/kexec. The crash dump kernel must be compiled to a
2051 memory address not used by the main kernel
2053 For more details see Documentation/kdump/kdump.txt
2055 config AUTO_ZRELADDR
2056 bool "Auto calculation of the decompressed kernel image address"
2058 ZRELADDR is the physical address where the decompressed kernel
2059 image will be placed. If AUTO_ZRELADDR is selected, the address
2060 will be determined at run-time by masking the current IP with
2061 0xf8000000. This assumes the zImage being placed in the first 128MB
2062 from start of memory.
2068 bool "UEFI runtime support"
2069 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2071 select EFI_PARAMS_FROM_FDT
2074 select EFI_RUNTIME_WRAPPERS
2076 This option provides support for runtime services provided
2077 by UEFI firmware (such as non-volatile variables, realtime
2078 clock, and platform reset). A UEFI stub is also provided to
2079 allow the kernel to be booted as an EFI application. This
2080 is only useful for kernels that may run on systems that have
2085 menu "CPU Power Management"
2087 source "drivers/cpufreq/Kconfig"
2089 source "drivers/cpuidle/Kconfig"
2093 menu "Floating point emulation"
2095 comment "At least one emulation must be selected"
2098 bool "NWFPE math emulation"
2099 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2101 Say Y to include the NWFPE floating point emulator in the kernel.
2102 This is necessary to run most binaries. Linux does not currently
2103 support floating point hardware so you need to say Y here even if
2104 your machine has an FPA or floating point co-processor podule.
2106 You may say N here if you are going to load the Acorn FPEmulator
2107 early in the bootup.
2110 bool "Support extended precision"
2111 depends on FPE_NWFPE
2113 Say Y to include 80-bit support in the kernel floating-point
2114 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2115 Note that gcc does not generate 80-bit operations by default,
2116 so in most cases this option only enlarges the size of the
2117 floating point emulator without any good reason.
2119 You almost surely want to say N here.
2122 bool "FastFPE math emulation (EXPERIMENTAL)"
2123 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2125 Say Y here to include the FAST floating point emulator in the kernel.
2126 This is an experimental much faster emulator which now also has full
2127 precision for the mantissa. It does not support any exceptions.
2128 It is very simple, and approximately 3-6 times faster than NWFPE.
2130 It should be sufficient for most programs. It may be not suitable
2131 for scientific calculations, but you have to check this for yourself.
2132 If you do not feel you need a faster FP emulation you should better
2136 bool "VFP-format floating point maths"
2137 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2139 Say Y to include VFP support code in the kernel. This is needed
2140 if your hardware includes a VFP unit.
2142 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2143 release notes and additional status information.
2145 Say N if your target does not have VFP hardware.
2153 bool "Advanced SIMD (NEON) Extension support"
2154 depends on VFPv3 && CPU_V7
2156 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2159 config KERNEL_MODE_NEON
2160 bool "Support for NEON in kernel mode"
2161 depends on NEON && AEABI
2163 Say Y to include support for NEON in kernel mode.
2167 menu "Userspace binary formats"
2169 source "fs/Kconfig.binfmt"
2173 menu "Power management options"
2175 source "kernel/power/Kconfig"
2177 config ARCH_SUSPEND_POSSIBLE
2178 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2179 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2182 config ARM_CPU_SUSPEND
2185 config ARCH_HIBERNATION_POSSIBLE
2188 default y if ARCH_SUSPEND_POSSIBLE
2192 source "net/Kconfig"
2194 source "drivers/Kconfig"
2196 source "drivers/firmware/Kconfig"
2200 source "arch/arm/Kconfig.debug"
2202 source "security/Kconfig"
2204 source "crypto/Kconfig"
2206 source "arch/arm/crypto/Kconfig"
2209 source "lib/Kconfig"
2211 source "arch/arm/kvm/Kconfig"