4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_MIGHT_HAVE_PC_PARPORT
10 select ARCH_SUPPORTS_ATOMIC_RMW
11 select ARCH_USE_BUILTIN_BSWAP
12 select ARCH_USE_CMPXCHG_LOCKREF
13 select ARCH_WANT_IPC_PARSE_VERSION
14 select BUILDTIME_EXTABLE_SORT if MMU
15 select CLONE_BACKWARDS
16 select CPU_PM if (SUSPEND || CPU_IDLE)
17 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
18 select GENERIC_ALLOCATOR
19 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
20 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
21 select GENERIC_IDLE_POLL_SETUP
22 select GENERIC_IRQ_PROBE
23 select GENERIC_IRQ_SHOW
24 select GENERIC_IRQ_SHOW_LEVEL
25 select GENERIC_PCI_IOMAP
26 select GENERIC_SCHED_CLOCK
27 select GENERIC_SMP_IDLE_THREAD
28 select GENERIC_STRNCPY_FROM_USER
29 select GENERIC_STRNLEN_USER
30 select HANDLE_DOMAIN_IRQ
31 select HARDIRQS_SW_RESEND
32 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
33 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
34 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
36 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
37 select HAVE_ARCH_TRACEHOOK
39 select HAVE_CC_STACKPROTECTOR
40 select HAVE_CONTEXT_TRACKING
41 select HAVE_C_RECORDMCOUNT
42 select HAVE_DEBUG_KMEMLEAK
43 select HAVE_DMA_API_DEBUG
45 select HAVE_DMA_CONTIGUOUS if MMU
46 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
47 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
48 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
49 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
50 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
51 select HAVE_GENERIC_DMA_COHERENT
52 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
53 select HAVE_IDE if PCI || ISA || PCMCIA
54 select HAVE_IRQ_TIME_ACCOUNTING
55 select HAVE_KERNEL_GZIP
56 select HAVE_KERNEL_LZ4
57 select HAVE_KERNEL_LZMA
58 select HAVE_KERNEL_LZO
60 select HAVE_KPROBES if !XIP_KERNEL
61 select HAVE_KRETPROBES if (HAVE_KPROBES)
63 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
64 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
65 select HAVE_OPTPROBES if !THUMB2_KERNEL
66 select HAVE_PERF_EVENTS
68 select HAVE_PERF_USER_STACK_DUMP
69 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
70 select HAVE_REGS_AND_STACK_ACCESS_API
71 select HAVE_SYSCALL_TRACEPOINTS
73 select HAVE_VIRT_CPU_ACCOUNTING_GEN
74 select IRQ_FORCED_THREADING
75 select MODULES_USE_ELF_REL
78 select OLD_SIGSUSPEND3
79 select PERF_USE_VMALLOC
81 select SYS_SUPPORTS_APM_EMULATION
82 # Above selects are sorted alphabetically; please add new ones
83 # according to that. Thanks.
85 The ARM series is a line of low-power-consumption RISC chip designs
86 licensed by ARM Ltd and targeted at embedded applications and
87 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
88 manufactured, but legacy ARM-based PC hardware remains popular in
89 Europe. There is an ARM Linux project with a web page at
90 <http://www.arm.linux.org.uk/>.
92 config ARM_HAS_SG_CHAIN
93 select ARCH_HAS_SG_CHAIN
96 config NEED_SG_DMA_LENGTH
99 config ARM_DMA_USE_IOMMU
101 select ARM_HAS_SG_CHAIN
102 select NEED_SG_DMA_LENGTH
106 config ARM_DMA_IOMMU_ALIGNMENT
107 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
111 DMA mapping framework by default aligns all buffers to the smallest
112 PAGE_SIZE order which is greater than or equal to the requested buffer
113 size. This works well for buffers up to a few hundreds kilobytes, but
114 for larger buffers it just a waste of address space. Drivers which has
115 relatively small addressing window (like 64Mib) might run out of
116 virtual space with just a few allocations.
118 With this parameter you can specify the maximum PAGE_SIZE order for
119 DMA IOMMU buffers. Larger buffers will be aligned only to this
120 specified order. The order is expressed as a power of two multiplied
125 config MIGHT_HAVE_PCI
128 config SYS_SUPPORTS_APM_EMULATION
133 select GENERIC_ALLOCATOR
144 The Extended Industry Standard Architecture (EISA) bus was
145 developed as an open alternative to the IBM MicroChannel bus.
147 The EISA bus provided some of the features of the IBM MicroChannel
148 bus while maintaining backward compatibility with cards made for
149 the older ISA bus. The EISA bus saw limited use between 1988 and
150 1995 when it was made obsolete by the PCI bus.
152 Say Y here if you are building a kernel for an EISA-based machine.
159 config STACKTRACE_SUPPORT
163 config HAVE_LATENCYTOP_SUPPORT
168 config LOCKDEP_SUPPORT
172 config TRACE_IRQFLAGS_SUPPORT
176 config RWSEM_XCHGADD_ALGORITHM
180 config ARCH_HAS_ILOG2_U32
183 config ARCH_HAS_ILOG2_U64
186 config ARCH_HAS_BANDGAP
189 config GENERIC_HWEIGHT
193 config GENERIC_CALIBRATE_DELAY
197 config ARCH_MAY_HAVE_PC_FDC
203 config NEED_DMA_MAP_STATE
206 config ARCH_SUPPORTS_UPROBES
209 config ARCH_HAS_DMA_SET_COHERENT_MASK
212 config GENERIC_ISA_DMA
218 config NEED_RET_TO_USER
226 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
227 default DRAM_BASE if REMAP_VECTORS_TO_RAM
230 The base address of exception vectors. This must be two pages
233 config ARM_PATCH_PHYS_VIRT
234 bool "Patch physical to virtual translations at runtime" if EMBEDDED
236 depends on !XIP_KERNEL && MMU
237 depends on !ARCH_REALVIEW || !SPARSEMEM
239 Patch phys-to-virt and virt-to-phys translation functions at
240 boot and module load time according to the position of the
241 kernel in system memory.
243 This can only be used with non-XIP MMU kernels where the base
244 of physical memory is at a 16MB boundary.
246 Only disable this option if you know that you do not require
247 this feature (eg, building a kernel for a single machine) and
248 you need to shrink the kernel to the minimal size.
250 config NEED_MACH_IO_H
253 Select this when mach/io.h is required to provide special
254 definitions for this platform. The need for mach/io.h should
255 be avoided when possible.
257 config NEED_MACH_MEMORY_H
260 Select this when mach/memory.h is required to provide special
261 definitions for this platform. The need for mach/memory.h should
262 be avoided when possible.
265 hex "Physical address of main memory" if MMU
266 depends on !ARM_PATCH_PHYS_VIRT
267 default DRAM_BASE if !MMU
268 default 0x00000000 if ARCH_EBSA110 || \
269 EP93XX_SDCE3_SYNC_PHYS_OFFSET || \
274 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
275 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
276 default 0x20000000 if ARCH_S5PV210
277 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
278 default 0xc0000000 if EP93XX_SDCE0_PHYS_OFFSET || ARCH_SA1100
279 default 0xd0000000 if EP93XX_SDCE1_PHYS_OFFSET
280 default 0xe0000000 if EP93XX_SDCE2_PHYS_OFFSET
281 default 0xf0000000 if EP93XX_SDCE3_ASYNC_PHYS_OFFSET
283 Please provide the physical address corresponding to the
284 location of main memory in your system.
290 source "init/Kconfig"
292 source "kernel/Kconfig.freezer"
297 bool "MMU-based Paged Memory Management Support"
300 Select if you want MMU-based virtualised addressing space
301 support by paged memory management. If unsure, say 'Y'.
304 # The "ARM system type" choice list is ordered alphabetically by option
305 # text. Please add new entries in the option alphabetic order.
308 prompt "ARM system type"
309 default ARCH_VERSATILE if !MMU
310 default ARCH_MULTIPLATFORM if MMU
312 config ARCH_MULTIPLATFORM
313 bool "Allow multiple platforms to be selected"
315 select ARCH_WANT_OPTIONAL_GPIOLIB
316 select ARM_HAS_SG_CHAIN
317 select ARM_PATCH_PHYS_VIRT
321 select GENERIC_CLOCKEVENTS
322 select MIGHT_HAVE_PCI
323 select MULTI_IRQ_HANDLER
328 bool "ARM Ltd. RealView family"
329 select ARCH_WANT_OPTIONAL_GPIOLIB
331 select ARM_TIMER_SP804
333 select COMMON_CLK_VERSATILE
334 select GENERIC_CLOCKEVENTS
335 select GPIO_PL061 if GPIOLIB
337 select NEED_MACH_MEMORY_H
338 select PLAT_VERSATILE
339 select PLAT_VERSATILE_SCHED_CLOCK
341 This enables support for ARM Ltd RealView boards.
343 config ARCH_VERSATILE
344 bool "ARM Ltd. Versatile family"
345 select ARCH_WANT_OPTIONAL_GPIOLIB
347 select ARM_TIMER_SP804
350 select GENERIC_CLOCKEVENTS
351 select HAVE_MACH_CLKDEV
353 select PLAT_VERSATILE
354 select PLAT_VERSATILE_CLOCK
355 select PLAT_VERSATILE_SCHED_CLOCK
356 select VERSATILE_FPGA_IRQ
358 This enables support for ARM Ltd Versatile board.
362 select ARCH_REQUIRE_GPIOLIB
365 select NEED_MACH_IO_H if PCCARD
370 This enables support for systems based on Atmel
371 AT91RM9200, AT91SAM9 and SAMA5 processors.
374 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
375 select ARCH_REQUIRE_GPIOLIB
380 select GENERIC_CLOCKEVENTS
384 Support for Cirrus Logic 711x/721x/731x based boards.
387 bool "Cortina Systems Gemini"
388 select ARCH_REQUIRE_GPIOLIB
391 select GENERIC_CLOCKEVENTS
393 Support for the Cortina Systems Gemini family SoCs
397 select ARCH_USES_GETTIMEOFFSET
400 select NEED_MACH_IO_H
401 select NEED_MACH_MEMORY_H
404 This is an evaluation board for the StrongARM processor available
405 from Digital. It has limited hardware on-board, including an
406 Ethernet interface, two PCMCIA sockets, two serial ports and a
410 bool "Energy Micro efm32"
412 select ARCH_REQUIRE_GPIOLIB
418 select GENERIC_CLOCKEVENTS
424 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
429 select ARCH_HAS_HOLES_MEMORYMODEL
430 select ARCH_REQUIRE_GPIOLIB
431 select ARCH_USES_GETTIMEOFFSET
437 This enables support for the Cirrus EP93xx series of CPUs.
439 config ARCH_FOOTBRIDGE
443 select GENERIC_CLOCKEVENTS
445 select NEED_MACH_IO_H if !MMU
446 select NEED_MACH_MEMORY_H
448 Support for systems based on the DC21285 companion chip
449 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
452 bool "Hilscher NetX based"
456 select GENERIC_CLOCKEVENTS
458 This enables support for systems based on the Hilscher NetX Soc
464 select NEED_MACH_MEMORY_H
465 select NEED_RET_TO_USER
471 Support for Intel's IOP13XX (XScale) family of processors.
476 select ARCH_REQUIRE_GPIOLIB
479 select NEED_RET_TO_USER
483 Support for Intel's 80219 and IOP32X (XScale) family of
489 select ARCH_REQUIRE_GPIOLIB
492 select NEED_RET_TO_USER
496 Support for Intel's IOP33X (XScale) family of processors.
501 select ARCH_HAS_DMA_SET_COHERENT_MASK
502 select ARCH_REQUIRE_GPIOLIB
503 select ARCH_SUPPORTS_BIG_ENDIAN
506 select DMABOUNCE if PCI
507 select GENERIC_CLOCKEVENTS
508 select MIGHT_HAVE_PCI
509 select NEED_MACH_IO_H
510 select USB_EHCI_BIG_ENDIAN_DESC
511 select USB_EHCI_BIG_ENDIAN_MMIO
513 Support for Intel's IXP4XX (XScale) family of processors.
517 select ARCH_REQUIRE_GPIOLIB
519 select GENERIC_CLOCKEVENTS
520 select MIGHT_HAVE_PCI
524 select PLAT_ORION_LEGACY
526 Support for the Marvell Dove SoC 88AP510
529 bool "Marvell MV78xx0"
530 select ARCH_REQUIRE_GPIOLIB
532 select GENERIC_CLOCKEVENTS
535 select PLAT_ORION_LEGACY
537 Support for the following Marvell MV78xx0 series SoCs:
543 select ARCH_REQUIRE_GPIOLIB
545 select GENERIC_CLOCKEVENTS
548 select PLAT_ORION_LEGACY
550 Support for the following Marvell Orion 5x series SoCs:
551 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
552 Orion-2 (5281), Orion-1-90 (6183).
555 bool "Marvell PXA168/910/MMP2"
557 select ARCH_REQUIRE_GPIOLIB
559 select GENERIC_ALLOCATOR
560 select GENERIC_CLOCKEVENTS
563 select MULTI_IRQ_HANDLER
568 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
571 bool "Micrel/Kendin KS8695"
572 select ARCH_REQUIRE_GPIOLIB
575 select GENERIC_CLOCKEVENTS
576 select NEED_MACH_MEMORY_H
578 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
579 System-on-Chip devices.
582 bool "Nuvoton W90X900 CPU"
583 select ARCH_REQUIRE_GPIOLIB
587 select GENERIC_CLOCKEVENTS
589 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
590 At present, the w90x900 has been renamed nuc900, regarding
591 the ARM series product line, you can login the following
592 link address to know more.
594 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
595 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
599 select ARCH_REQUIRE_GPIOLIB
604 select GENERIC_CLOCKEVENTS
608 Support for the NXP LPC32XX family of processors
611 bool "PXA2xx/PXA3xx-based"
614 select ARCH_REQUIRE_GPIOLIB
615 select ARM_CPU_SUSPEND if PM
620 select GENERIC_CLOCKEVENTS
623 select MULTI_IRQ_HANDLER
627 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
630 bool "Qualcomm MSM (non-multiplatform)"
631 select ARCH_REQUIRE_GPIOLIB
633 select GENERIC_CLOCKEVENTS
635 Support for Qualcomm MSM/QSD based systems. This runs on the
636 apps processor of the MSM/QSD and depends on a shared memory
637 interface to the modem processor which runs the baseband
638 stack and controls some vital subsystems
639 (clock and power control, etc).
641 config ARCH_SHMOBILE_LEGACY
642 bool "Renesas ARM SoCs (non-multiplatform)"
644 select ARM_PATCH_PHYS_VIRT if MMU
647 select GENERIC_CLOCKEVENTS
648 select HAVE_ARM_SCU if SMP
649 select HAVE_ARM_TWD if SMP
650 select HAVE_MACH_CLKDEV
652 select MIGHT_HAVE_CACHE_L2X0
653 select MULTI_IRQ_HANDLER
656 select PM_GENERIC_DOMAINS if PM
660 Support for Renesas ARM SoC platforms using a non-multiplatform
661 kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
667 select ARCH_MAY_HAVE_PC_FDC
668 select ARCH_SPARSEMEM_ENABLE
669 select ARCH_USES_GETTIMEOFFSET
673 select HAVE_PATA_PLATFORM
675 select NEED_MACH_IO_H
676 select NEED_MACH_MEMORY_H
680 On the Acorn Risc-PC, Linux can support the internal IDE disk and
681 CD-ROM interface, serial and parallel port, and the floppy drive.
686 select ARCH_REQUIRE_GPIOLIB
687 select ARCH_SPARSEMEM_ENABLE
692 select GENERIC_CLOCKEVENTS
696 select MULTI_IRQ_HANDLER
697 select NEED_MACH_MEMORY_H
700 Support for StrongARM 11x0 based boards.
703 bool "Samsung S3C24XX SoCs"
704 select ARCH_REQUIRE_GPIOLIB
707 select CLKSRC_SAMSUNG_PWM
708 select GENERIC_CLOCKEVENTS
710 select HAVE_S3C2410_I2C if I2C
711 select HAVE_S3C2410_WATCHDOG if WATCHDOG
712 select HAVE_S3C_RTC if RTC_CLASS
713 select MULTI_IRQ_HANDLER
714 select NEED_MACH_IO_H
717 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
718 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
719 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
720 Samsung SMDK2410 development board (and derivatives).
723 bool "Samsung S3C64XX"
724 select ARCH_REQUIRE_GPIOLIB
729 select CLKSRC_SAMSUNG_PWM
730 select COMMON_CLK_SAMSUNG
732 select GENERIC_CLOCKEVENTS
734 select HAVE_S3C2410_I2C if I2C
735 select HAVE_S3C2410_WATCHDOG if WATCHDOG
739 select PM_GENERIC_DOMAINS if PM
741 select S3C_GPIO_TRACK
743 select SAMSUNG_WAKEMASK
744 select SAMSUNG_WDT_RESET
746 Samsung S3C64XX series based systems
750 select ARCH_HAS_HOLES_MEMORYMODEL
751 select ARCH_REQUIRE_GPIOLIB
753 select GENERIC_ALLOCATOR
754 select GENERIC_CLOCKEVENTS
755 select GENERIC_IRQ_CHIP
761 Support for TI's DaVinci platform.
766 select ARCH_HAS_HOLES_MEMORYMODEL
768 select ARCH_REQUIRE_GPIOLIB
771 select GENERIC_CLOCKEVENTS
772 select GENERIC_IRQ_CHIP
775 select NEED_MACH_IO_H if PCCARD
776 select NEED_MACH_MEMORY_H
778 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
782 menu "Multiple platform selection"
783 depends on ARCH_MULTIPLATFORM
785 comment "CPU Core family selection"
788 bool "ARMv4 based platforms (FA526)"
789 depends on !ARCH_MULTI_V6_V7
790 select ARCH_MULTI_V4_V5
793 config ARCH_MULTI_V4T
794 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
795 depends on !ARCH_MULTI_V6_V7
796 select ARCH_MULTI_V4_V5
797 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
798 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
799 CPU_ARM925T || CPU_ARM940T)
802 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
803 depends on !ARCH_MULTI_V6_V7
804 select ARCH_MULTI_V4_V5
805 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
806 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
807 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
809 config ARCH_MULTI_V4_V5
813 bool "ARMv6 based platforms (ARM11)"
814 select ARCH_MULTI_V6_V7
818 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
820 select ARCH_MULTI_V6_V7
824 config ARCH_MULTI_V6_V7
826 select MIGHT_HAVE_CACHE_L2X0
828 config ARCH_MULTI_CPU_AUTO
829 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
835 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
839 select HAVE_ARM_ARCH_TIMER
842 # This is sorted alphabetically by mach-* pathname. However, plat-*
843 # Kconfigs may be included either alphabetically (according to the
844 # plat- suffix) or along side the corresponding mach-* source.
846 source "arch/arm/mach-mvebu/Kconfig"
848 source "arch/arm/mach-asm9260/Kconfig"
850 source "arch/arm/mach-at91/Kconfig"
852 source "arch/arm/mach-axxia/Kconfig"
854 source "arch/arm/mach-bcm/Kconfig"
856 source "arch/arm/mach-berlin/Kconfig"
858 source "arch/arm/mach-clps711x/Kconfig"
860 source "arch/arm/mach-cns3xxx/Kconfig"
862 source "arch/arm/mach-davinci/Kconfig"
864 source "arch/arm/mach-digicolor/Kconfig"
866 source "arch/arm/mach-dove/Kconfig"
868 source "arch/arm/mach-ep93xx/Kconfig"
870 source "arch/arm/mach-footbridge/Kconfig"
872 source "arch/arm/mach-gemini/Kconfig"
874 source "arch/arm/mach-highbank/Kconfig"
876 source "arch/arm/mach-hisi/Kconfig"
878 source "arch/arm/mach-integrator/Kconfig"
880 source "arch/arm/mach-iop32x/Kconfig"
882 source "arch/arm/mach-iop33x/Kconfig"
884 source "arch/arm/mach-iop13xx/Kconfig"
886 source "arch/arm/mach-ixp4xx/Kconfig"
888 source "arch/arm/mach-keystone/Kconfig"
890 source "arch/arm/mach-ks8695/Kconfig"
892 source "arch/arm/mach-meson/Kconfig"
894 source "arch/arm/mach-msm/Kconfig"
896 source "arch/arm/mach-moxart/Kconfig"
898 source "arch/arm/mach-mv78xx0/Kconfig"
900 source "arch/arm/mach-imx/Kconfig"
902 source "arch/arm/mach-mediatek/Kconfig"
904 source "arch/arm/mach-mxs/Kconfig"
906 source "arch/arm/mach-netx/Kconfig"
908 source "arch/arm/mach-nomadik/Kconfig"
910 source "arch/arm/mach-nspire/Kconfig"
912 source "arch/arm/plat-omap/Kconfig"
914 source "arch/arm/mach-omap1/Kconfig"
916 source "arch/arm/mach-omap2/Kconfig"
918 source "arch/arm/mach-orion5x/Kconfig"
920 source "arch/arm/mach-picoxcell/Kconfig"
922 source "arch/arm/mach-pxa/Kconfig"
923 source "arch/arm/plat-pxa/Kconfig"
925 source "arch/arm/mach-mmp/Kconfig"
927 source "arch/arm/mach-qcom/Kconfig"
929 source "arch/arm/mach-realview/Kconfig"
931 source "arch/arm/mach-rockchip/Kconfig"
933 source "arch/arm/mach-sa1100/Kconfig"
935 source "arch/arm/mach-socfpga/Kconfig"
937 source "arch/arm/mach-spear/Kconfig"
939 source "arch/arm/mach-sti/Kconfig"
941 source "arch/arm/mach-s3c24xx/Kconfig"
943 source "arch/arm/mach-s3c64xx/Kconfig"
945 source "arch/arm/mach-s5pv210/Kconfig"
947 source "arch/arm/mach-exynos/Kconfig"
948 source "arch/arm/plat-samsung/Kconfig"
950 source "arch/arm/mach-shmobile/Kconfig"
952 source "arch/arm/mach-sunxi/Kconfig"
954 source "arch/arm/mach-prima2/Kconfig"
956 source "arch/arm/mach-tegra/Kconfig"
958 source "arch/arm/mach-u300/Kconfig"
960 source "arch/arm/mach-ux500/Kconfig"
962 source "arch/arm/mach-versatile/Kconfig"
964 source "arch/arm/mach-vexpress/Kconfig"
965 source "arch/arm/plat-versatile/Kconfig"
967 source "arch/arm/mach-vt8500/Kconfig"
969 source "arch/arm/mach-w90x900/Kconfig"
971 source "arch/arm/mach-zynq/Kconfig"
973 # Definitions to make life easier
979 select GENERIC_CLOCKEVENTS
985 select GENERIC_IRQ_CHIP
988 config PLAT_ORION_LEGACY
995 config PLAT_VERSATILE
998 config ARM_TIMER_SP804
1001 select CLKSRC_OF if OF
1003 source "arch/arm/firmware/Kconfig"
1005 source arch/arm/mm/Kconfig
1008 bool "Enable iWMMXt support"
1009 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1010 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1012 Enable support for iWMMXt context switching at run time if
1013 running on a CPU that supports it.
1015 config MULTI_IRQ_HANDLER
1018 Allow each machine to specify it's own IRQ handler at run time.
1021 source "arch/arm/Kconfig-nommu"
1024 config PJ4B_ERRATA_4742
1025 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1026 depends on CPU_PJ4B && MACH_ARMADA_370
1029 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1030 Event (WFE) IDLE states, a specific timing sensitivity exists between
1031 the retiring WFI/WFE instructions and the newly issued subsequent
1032 instructions. This sensitivity can result in a CPU hang scenario.
1034 The software must insert either a Data Synchronization Barrier (DSB)
1035 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1038 config ARM_ERRATA_326103
1039 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1042 Executing a SWP instruction to read-only memory does not set bit 11
1043 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1044 treat the access as a read, preventing a COW from occurring and
1045 causing the faulting task to livelock.
1047 config ARM_ERRATA_411920
1048 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1049 depends on CPU_V6 || CPU_V6K
1051 Invalidation of the Instruction Cache operation can
1052 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1053 It does not affect the MPCore. This option enables the ARM Ltd.
1054 recommended workaround.
1056 config ARM_ERRATA_430973
1057 bool "ARM errata: Stale prediction on replaced interworking branch"
1060 This option enables the workaround for the 430973 Cortex-A8
1061 r1p* erratum. If a code sequence containing an ARM/Thumb
1062 interworking branch is replaced with another code sequence at the
1063 same virtual address, whether due to self-modifying code or virtual
1064 to physical address re-mapping, Cortex-A8 does not recover from the
1065 stale interworking branch prediction. This results in Cortex-A8
1066 executing the new code sequence in the incorrect ARM or Thumb state.
1067 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1068 and also flushes the branch target cache at every context switch.
1069 Note that setting specific bits in the ACTLR register may not be
1070 available in non-secure mode.
1072 config ARM_ERRATA_458693
1073 bool "ARM errata: Processor deadlock when a false hazard is created"
1075 depends on !ARCH_MULTIPLATFORM
1077 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1078 erratum. For very specific sequences of memory operations, it is
1079 possible for a hazard condition intended for a cache line to instead
1080 be incorrectly associated with a different cache line. This false
1081 hazard might then cause a processor deadlock. The workaround enables
1082 the L1 caching of the NEON accesses and disables the PLD instruction
1083 in the ACTLR register. Note that setting specific bits in the ACTLR
1084 register may not be available in non-secure mode.
1086 config ARM_ERRATA_460075
1087 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1089 depends on !ARCH_MULTIPLATFORM
1091 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1092 erratum. Any asynchronous access to the L2 cache may encounter a
1093 situation in which recent store transactions to the L2 cache are lost
1094 and overwritten with stale memory contents from external memory. The
1095 workaround disables the write-allocate mode for the L2 cache via the
1096 ACTLR register. Note that setting specific bits in the ACTLR register
1097 may not be available in non-secure mode.
1099 config ARM_ERRATA_742230
1100 bool "ARM errata: DMB operation may be faulty"
1101 depends on CPU_V7 && SMP
1102 depends on !ARCH_MULTIPLATFORM
1104 This option enables the workaround for the 742230 Cortex-A9
1105 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1106 between two write operations may not ensure the correct visibility
1107 ordering of the two writes. This workaround sets a specific bit in
1108 the diagnostic register of the Cortex-A9 which causes the DMB
1109 instruction to behave as a DSB, ensuring the correct behaviour of
1112 config ARM_ERRATA_742231
1113 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1114 depends on CPU_V7 && SMP
1115 depends on !ARCH_MULTIPLATFORM
1117 This option enables the workaround for the 742231 Cortex-A9
1118 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1119 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1120 accessing some data located in the same cache line, may get corrupted
1121 data due to bad handling of the address hazard when the line gets
1122 replaced from one of the CPUs at the same time as another CPU is
1123 accessing it. This workaround sets specific bits in the diagnostic
1124 register of the Cortex-A9 which reduces the linefill issuing
1125 capabilities of the processor.
1127 config ARM_ERRATA_643719
1128 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1129 depends on CPU_V7 && SMP
1132 This option enables the workaround for the 643719 Cortex-A9 (prior to
1133 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1134 register returns zero when it should return one. The workaround
1135 corrects this value, ensuring cache maintenance operations which use
1136 it behave as intended and avoiding data corruption.
1138 config ARM_ERRATA_720789
1139 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1142 This option enables the workaround for the 720789 Cortex-A9 (prior to
1143 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1144 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1145 As a consequence of this erratum, some TLB entries which should be
1146 invalidated are not, resulting in an incoherency in the system page
1147 tables. The workaround changes the TLB flushing routines to invalidate
1148 entries regardless of the ASID.
1150 config ARM_ERRATA_743622
1151 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1153 depends on !ARCH_MULTIPLATFORM
1155 This option enables the workaround for the 743622 Cortex-A9
1156 (r2p*) erratum. Under very rare conditions, a faulty
1157 optimisation in the Cortex-A9 Store Buffer may lead to data
1158 corruption. This workaround sets a specific bit in the diagnostic
1159 register of the Cortex-A9 which disables the Store Buffer
1160 optimisation, preventing the defect from occurring. This has no
1161 visible impact on the overall performance or power consumption of the
1164 config ARM_ERRATA_751472
1165 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1167 depends on !ARCH_MULTIPLATFORM
1169 This option enables the workaround for the 751472 Cortex-A9 (prior
1170 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1171 completion of a following broadcasted operation if the second
1172 operation is received by a CPU before the ICIALLUIS has completed,
1173 potentially leading to corrupted entries in the cache or TLB.
1175 config ARM_ERRATA_754322
1176 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1179 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1180 r3p*) erratum. A speculative memory access may cause a page table walk
1181 which starts prior to an ASID switch but completes afterwards. This
1182 can populate the micro-TLB with a stale entry which may be hit with
1183 the new ASID. This workaround places two dsb instructions in the mm
1184 switching code so that no page table walks can cross the ASID switch.
1186 config ARM_ERRATA_754327
1187 bool "ARM errata: no automatic Store Buffer drain"
1188 depends on CPU_V7 && SMP
1190 This option enables the workaround for the 754327 Cortex-A9 (prior to
1191 r2p0) erratum. The Store Buffer does not have any automatic draining
1192 mechanism and therefore a livelock may occur if an external agent
1193 continuously polls a memory location waiting to observe an update.
1194 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1195 written polling loops from denying visibility of updates to memory.
1197 config ARM_ERRATA_364296
1198 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1201 This options enables the workaround for the 364296 ARM1136
1202 r0p2 erratum (possible cache data corruption with
1203 hit-under-miss enabled). It sets the undocumented bit 31 in
1204 the auxiliary control register and the FI bit in the control
1205 register, thus disabling hit-under-miss without putting the
1206 processor into full low interrupt latency mode. ARM11MPCore
1209 config ARM_ERRATA_764369
1210 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1211 depends on CPU_V7 && SMP
1213 This option enables the workaround for erratum 764369
1214 affecting Cortex-A9 MPCore with two or more processors (all
1215 current revisions). Under certain timing circumstances, a data
1216 cache line maintenance operation by MVA targeting an Inner
1217 Shareable memory region may fail to proceed up to either the
1218 Point of Coherency or to the Point of Unification of the
1219 system. This workaround adds a DSB instruction before the
1220 relevant cache maintenance functions and sets a specific bit
1221 in the diagnostic control register of the SCU.
1223 config ARM_ERRATA_775420
1224 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1227 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1228 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1229 operation aborts with MMU exception, it might cause the processor
1230 to deadlock. This workaround puts DSB before executing ISB if
1231 an abort may occur on cache maintenance.
1233 config ARM_ERRATA_798181
1234 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1235 depends on CPU_V7 && SMP
1237 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1238 adequately shooting down all use of the old entries. This
1239 option enables the Linux kernel workaround for this erratum
1240 which sends an IPI to the CPUs that are running the same ASID
1241 as the one being invalidated.
1243 config ARM_ERRATA_773022
1244 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1247 This option enables the workaround for the 773022 Cortex-A15
1248 (up to r0p4) erratum. In certain rare sequences of code, the
1249 loop buffer may deliver incorrect instructions. This
1250 workaround disables the loop buffer to avoid the erratum.
1254 source "arch/arm/common/Kconfig"
1261 Find out whether you have ISA slots on your motherboard. ISA is the
1262 name of a bus system, i.e. the way the CPU talks to the other stuff
1263 inside your box. Other bus systems are PCI, EISA, MicroChannel
1264 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1265 newer boards don't support it. If you have ISA, say Y, otherwise N.
1267 # Select ISA DMA controller support
1272 # Select ISA DMA interface
1277 bool "PCI support" if MIGHT_HAVE_PCI
1279 Find out whether you have a PCI motherboard. PCI is the name of a
1280 bus system, i.e. the way the CPU talks to the other stuff inside
1281 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1282 VESA. If you have PCI, say Y, otherwise N.
1288 config PCI_DOMAINS_GENERIC
1289 def_bool PCI_DOMAINS
1291 config PCI_NANOENGINE
1292 bool "BSE nanoEngine PCI support"
1293 depends on SA1100_NANOENGINE
1295 Enable PCI on the BSE nanoEngine board.
1300 config PCI_HOST_ITE8152
1302 depends on PCI && MACH_ARMCORE
1306 source "drivers/pci/Kconfig"
1307 source "drivers/pci/pcie/Kconfig"
1309 source "drivers/pcmcia/Kconfig"
1313 menu "Kernel Features"
1318 This option should be selected by machines which have an SMP-
1321 The only effect of this option is to make the SMP-related
1322 options available to the user for configuration.
1325 bool "Symmetric Multi-Processing"
1326 depends on CPU_V6K || CPU_V7
1327 depends on GENERIC_CLOCKEVENTS
1329 depends on MMU || ARM_MPU
1331 This enables support for systems with more than one CPU. If you have
1332 a system with only one CPU, say N. If you have a system with more
1333 than one CPU, say Y.
1335 If you say N here, the kernel will run on uni- and multiprocessor
1336 machines, but will use only one CPU of a multiprocessor machine. If
1337 you say Y here, the kernel will run on many, but not all,
1338 uniprocessor machines. On a uniprocessor machine, the kernel
1339 will run faster if you say N here.
1341 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1342 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1343 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1345 If you don't know what to do here, say N.
1348 bool "Allow booting SMP kernel on uniprocessor systems"
1349 depends on SMP && !XIP_KERNEL && MMU
1352 SMP kernels contain instructions which fail on non-SMP processors.
1353 Enabling this option allows the kernel to modify itself to make
1354 these instructions safe. Disabling it allows about 1K of space
1357 If you don't know what to do here, say Y.
1359 config ARM_CPU_TOPOLOGY
1360 bool "Support cpu topology definition"
1361 depends on SMP && CPU_V7
1364 Support ARM cpu topology definition. The MPIDR register defines
1365 affinity between processors which is then used to describe the cpu
1366 topology of an ARM System.
1369 bool "Multi-core scheduler support"
1370 depends on ARM_CPU_TOPOLOGY
1372 Multi-core scheduler support improves the CPU scheduler's decision
1373 making when dealing with multi-core CPU chips at a cost of slightly
1374 increased overhead in some places. If unsure say N here.
1377 bool "SMT scheduler support"
1378 depends on ARM_CPU_TOPOLOGY
1380 Improves the CPU scheduler's decision making when dealing with
1381 MultiThreading at a cost of slightly increased overhead in some
1382 places. If unsure say N here.
1387 This option enables support for the ARM system coherency unit
1389 config HAVE_ARM_ARCH_TIMER
1390 bool "Architected timer support"
1392 select ARM_ARCH_TIMER
1393 select GENERIC_CLOCKEVENTS
1395 This option enables support for the ARM architected timer
1400 select CLKSRC_OF if OF
1402 This options enables support for the ARM timer and watchdog unit
1405 bool "Multi-Cluster Power Management"
1406 depends on CPU_V7 && SMP
1408 This option provides the common power management infrastructure
1409 for (multi-)cluster based systems, such as big.LITTLE based
1412 config MCPM_QUAD_CLUSTER
1416 To avoid wasting resources unnecessarily, MCPM only supports up
1417 to 2 clusters by default.
1418 Platforms with 3 or 4 clusters that use MCPM must select this
1419 option to allow the additional clusters to be managed.
1422 bool "big.LITTLE support (Experimental)"
1423 depends on CPU_V7 && SMP
1426 This option enables support selections for the big.LITTLE
1427 system architecture.
1430 bool "big.LITTLE switcher support"
1431 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1432 select ARM_CPU_SUSPEND
1435 The big.LITTLE "switcher" provides the core functionality to
1436 transparently handle transition between a cluster of A15's
1437 and a cluster of A7's in a big.LITTLE system.
1439 config BL_SWITCHER_DUMMY_IF
1440 tristate "Simple big.LITTLE switcher user interface"
1441 depends on BL_SWITCHER && DEBUG_KERNEL
1443 This is a simple and dummy char dev interface to control
1444 the big.LITTLE switcher core code. It is meant for
1445 debugging purposes only.
1448 prompt "Memory split"
1452 Select the desired split between kernel and user memory.
1454 If you are not absolutely sure what you are doing, leave this
1458 bool "3G/1G user/kernel split"
1460 bool "2G/2G user/kernel split"
1462 bool "1G/3G user/kernel split"
1467 default PHYS_OFFSET if !MMU
1468 default 0x40000000 if VMSPLIT_1G
1469 default 0x80000000 if VMSPLIT_2G
1473 int "Maximum number of CPUs (2-32)"
1479 bool "Support for hot-pluggable CPUs"
1482 Say Y here to experiment with turning CPUs off and on. CPUs
1483 can be controlled through /sys/devices/system/cpu.
1486 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1489 Say Y here if you want Linux to communicate with system firmware
1490 implementing the PSCI specification for CPU-centric power
1491 management operations described in ARM document number ARM DEN
1492 0022A ("Power State Coordination Interface System Software on
1495 # The GPIO number here must be sorted by descending number. In case of
1496 # a multiplatform kernel, we just want the highest value required by the
1497 # selected platforms.
1500 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA || ARCH_ZYNQ
1501 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1502 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1503 default 416 if ARCH_SUNXI
1504 default 392 if ARCH_U8500
1505 default 352 if ARCH_VT8500
1506 default 288 if ARCH_ROCKCHIP
1507 default 264 if MACH_H4700
1510 Maximum number of GPIOs in the system.
1512 If unsure, leave the default value.
1514 source kernel/Kconfig.preempt
1518 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1519 ARCH_S5PV210 || ARCH_EXYNOS4
1520 default AT91_TIMER_HZ if ARCH_AT91
1521 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1525 depends on HZ_FIXED = 0
1526 prompt "Timer frequency"
1550 default HZ_FIXED if HZ_FIXED != 0
1551 default 100 if HZ_100
1552 default 200 if HZ_200
1553 default 250 if HZ_250
1554 default 300 if HZ_300
1555 default 500 if HZ_500
1559 def_bool HIGH_RES_TIMERS
1561 config THUMB2_KERNEL
1562 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1563 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1564 default y if CPU_THUMBONLY
1566 select ARM_ASM_UNIFIED
1569 By enabling this option, the kernel will be compiled in
1570 Thumb-2 mode. A compiler/assembler that understand the unified
1571 ARM-Thumb syntax is needed.
1575 config THUMB2_AVOID_R_ARM_THM_JUMP11
1576 bool "Work around buggy Thumb-2 short branch relocations in gas"
1577 depends on THUMB2_KERNEL && MODULES
1580 Various binutils versions can resolve Thumb-2 branches to
1581 locally-defined, preemptible global symbols as short-range "b.n"
1582 branch instructions.
1584 This is a problem, because there's no guarantee the final
1585 destination of the symbol, or any candidate locations for a
1586 trampoline, are within range of the branch. For this reason, the
1587 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1588 relocation in modules at all, and it makes little sense to add
1591 The symptom is that the kernel fails with an "unsupported
1592 relocation" error when loading some modules.
1594 Until fixed tools are available, passing
1595 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1596 code which hits this problem, at the cost of a bit of extra runtime
1597 stack usage in some cases.
1599 The problem is described in more detail at:
1600 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1602 Only Thumb-2 kernels are affected.
1604 Unless you are sure your tools don't have this problem, say Y.
1606 config ARM_ASM_UNIFIED
1610 bool "Use the ARM EABI to compile the kernel"
1612 This option allows for the kernel to be compiled using the latest
1613 ARM ABI (aka EABI). This is only useful if you are using a user
1614 space environment that is also compiled with EABI.
1616 Since there are major incompatibilities between the legacy ABI and
1617 EABI, especially with regard to structure member alignment, this
1618 option also changes the kernel syscall calling convention to
1619 disambiguate both ABIs and allow for backward compatibility support
1620 (selected with CONFIG_OABI_COMPAT).
1622 To use this you need GCC version 4.0.0 or later.
1625 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1626 depends on AEABI && !THUMB2_KERNEL
1628 This option preserves the old syscall interface along with the
1629 new (ARM EABI) one. It also provides a compatibility layer to
1630 intercept syscalls that have structure arguments which layout
1631 in memory differs between the legacy ABI and the new ARM EABI
1632 (only for non "thumb" binaries). This option adds a tiny
1633 overhead to all syscalls and produces a slightly larger kernel.
1635 The seccomp filter system will not be available when this is
1636 selected, since there is no way yet to sensibly distinguish
1637 between calling conventions during filtering.
1639 If you know you'll be using only pure EABI user space then you
1640 can say N here. If this option is not selected and you attempt
1641 to execute a legacy ABI binary then the result will be
1642 UNPREDICTABLE (in fact it can be predicted that it won't work
1643 at all). If in doubt say N.
1645 config ARCH_HAS_HOLES_MEMORYMODEL
1648 config ARCH_SPARSEMEM_ENABLE
1651 config ARCH_SPARSEMEM_DEFAULT
1652 def_bool ARCH_SPARSEMEM_ENABLE
1654 config ARCH_SELECT_MEMORY_MODEL
1655 def_bool ARCH_SPARSEMEM_ENABLE
1657 config HAVE_ARCH_PFN_VALID
1658 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1660 config HAVE_GENERIC_RCU_GUP
1665 bool "High Memory Support"
1668 The address space of ARM processors is only 4 Gigabytes large
1669 and it has to accommodate user address space, kernel address
1670 space as well as some memory mapped IO. That means that, if you
1671 have a large amount of physical memory and/or IO, not all of the
1672 memory can be "permanently mapped" by the kernel. The physical
1673 memory that is not permanently mapped is called "high memory".
1675 Depending on the selected kernel/user memory split, minimum
1676 vmalloc space and actual amount of RAM, you may not need this
1677 option which should result in a slightly faster kernel.
1682 bool "Allocate 2nd-level pagetables from highmem"
1685 config HW_PERF_EVENTS
1686 bool "Enable hardware performance counter support for perf events"
1687 depends on PERF_EVENTS
1690 Enable hardware performance counter support for perf events. If
1691 disabled, perf events will use software events only.
1693 config SYS_SUPPORTS_HUGETLBFS
1697 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1701 config ARCH_WANT_GENERAL_HUGETLB
1706 config FORCE_MAX_ZONEORDER
1707 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1708 range 11 64 if ARCH_SHMOBILE_LEGACY
1709 default "12" if SOC_AM33XX
1710 default "9" if SA1111 || ARCH_EFM32
1713 The kernel memory allocator divides physically contiguous memory
1714 blocks into "zones", where each zone is a power of two number of
1715 pages. This option selects the largest power of two that the kernel
1716 keeps in the memory allocator. If you need to allocate very large
1717 blocks of physically contiguous memory, then you may need to
1718 increase this value.
1720 This config option is actually maximum order plus one. For example,
1721 a value of 11 means that the largest free memory block is 2^10 pages.
1723 config ALIGNMENT_TRAP
1725 depends on CPU_CP15_MMU
1726 default y if !ARCH_EBSA110
1727 select HAVE_PROC_CPU if PROC_FS
1729 ARM processors cannot fetch/store information which is not
1730 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1731 address divisible by 4. On 32-bit ARM processors, these non-aligned
1732 fetch/store instructions will be emulated in software if you say
1733 here, which has a severe performance impact. This is necessary for
1734 correct operation of some network protocols. With an IP-only
1735 configuration it is safe to say N, otherwise say Y.
1737 config UACCESS_WITH_MEMCPY
1738 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1740 default y if CPU_FEROCEON
1742 Implement faster copy_to_user and clear_user methods for CPU
1743 cores where a 8-word STM instruction give significantly higher
1744 memory write throughput than a sequence of individual 32bit stores.
1746 A possible side effect is a slight increase in scheduling latency
1747 between threads sharing the same address space if they invoke
1748 such copy operations with large buffers.
1750 However, if the CPU data cache is using a write-allocate mode,
1751 this option is unlikely to provide any performance gain.
1755 prompt "Enable seccomp to safely compute untrusted bytecode"
1757 This kernel feature is useful for number crunching applications
1758 that may need to compute untrusted bytecode during their
1759 execution. By using pipes or other transports made available to
1760 the process as file descriptors supporting the read/write
1761 syscalls, it's possible to isolate those applications in
1762 their own address space using seccomp. Once seccomp is
1763 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1764 and the task is only allowed to execute a few safe syscalls
1765 defined by each seccomp mode.
1778 bool "Xen guest support on ARM"
1779 depends on ARM && AEABI && OF
1780 depends on CPU_V7 && !CPU_V6
1781 depends on !GENERIC_ATOMIC64
1783 select ARCH_DMA_ADDR_T_64BIT
1787 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1794 bool "Flattened Device Tree support"
1797 select OF_EARLY_FLATTREE
1798 select OF_RESERVED_MEM
1800 Include support for flattened device tree machine descriptions.
1803 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1806 This is the traditional way of passing data to the kernel at boot
1807 time. If you are solely relying on the flattened device tree (or
1808 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1809 to remove ATAGS support from your kernel binary. If unsure,
1812 config DEPRECATED_PARAM_STRUCT
1813 bool "Provide old way to pass kernel parameters"
1816 This was deprecated in 2001 and announced to live on for 5 years.
1817 Some old boot loaders still use this way.
1819 # Compressed boot loader in ROM. Yes, we really want to ask about
1820 # TEXT and BSS so we preserve their values in the config files.
1821 config ZBOOT_ROM_TEXT
1822 hex "Compressed ROM boot loader base address"
1825 The physical address at which the ROM-able zImage is to be
1826 placed in the target. Platforms which normally make use of
1827 ROM-able zImage formats normally set this to a suitable
1828 value in their defconfig file.
1830 If ZBOOT_ROM is not enabled, this has no effect.
1832 config ZBOOT_ROM_BSS
1833 hex "Compressed ROM boot loader BSS address"
1836 The base address of an area of read/write memory in the target
1837 for the ROM-able zImage which must be available while the
1838 decompressor is running. It must be large enough to hold the
1839 entire decompressed kernel plus an additional 128 KiB.
1840 Platforms which normally make use of ROM-able zImage formats
1841 normally set this to a suitable value in their defconfig file.
1843 If ZBOOT_ROM is not enabled, this has no effect.
1846 bool "Compressed boot loader in ROM/flash"
1847 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1848 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1850 Say Y here if you intend to execute your compressed kernel image
1851 (zImage) directly from ROM or flash. If unsure, say N.
1854 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1855 depends on ZBOOT_ROM && ARCH_SH7372
1856 default ZBOOT_ROM_NONE
1858 Include experimental SD/MMC loading code in the ROM-able zImage.
1859 With this enabled it is possible to write the ROM-able zImage
1860 kernel image to an MMC or SD card and boot the kernel straight
1861 from the reset vector. At reset the processor Mask ROM will load
1862 the first part of the ROM-able zImage which in turn loads the
1863 rest the kernel image to RAM.
1865 config ZBOOT_ROM_NONE
1866 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1868 Do not load image from SD or MMC
1870 config ZBOOT_ROM_MMCIF
1871 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1873 Load image from MMCIF hardware block.
1875 config ZBOOT_ROM_SH_MOBILE_SDHI
1876 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1878 Load image from SDHI hardware block
1882 config ARM_APPENDED_DTB
1883 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1886 With this option, the boot code will look for a device tree binary
1887 (DTB) appended to zImage
1888 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1890 This is meant as a backward compatibility convenience for those
1891 systems with a bootloader that can't be upgraded to accommodate
1892 the documented boot protocol using a device tree.
1894 Beware that there is very little in terms of protection against
1895 this option being confused by leftover garbage in memory that might
1896 look like a DTB header after a reboot if no actual DTB is appended
1897 to zImage. Do not leave this option active in a production kernel
1898 if you don't intend to always append a DTB. Proper passing of the
1899 location into r2 of a bootloader provided DTB is always preferable
1902 config ARM_ATAG_DTB_COMPAT
1903 bool "Supplement the appended DTB with traditional ATAG information"
1904 depends on ARM_APPENDED_DTB
1906 Some old bootloaders can't be updated to a DTB capable one, yet
1907 they provide ATAGs with memory configuration, the ramdisk address,
1908 the kernel cmdline string, etc. Such information is dynamically
1909 provided by the bootloader and can't always be stored in a static
1910 DTB. To allow a device tree enabled kernel to be used with such
1911 bootloaders, this option allows zImage to extract the information
1912 from the ATAG list and store it at run time into the appended DTB.
1915 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1916 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1918 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1919 bool "Use bootloader kernel arguments if available"
1921 Uses the command-line options passed by the boot loader instead of
1922 the device tree bootargs property. If the boot loader doesn't provide
1923 any, the device tree bootargs property will be used.
1925 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1926 bool "Extend with bootloader kernel arguments"
1928 The command-line arguments provided by the boot loader will be
1929 appended to the the device tree bootargs property.
1934 string "Default kernel command string"
1937 On some architectures (EBSA110 and CATS), there is currently no way
1938 for the boot loader to pass arguments to the kernel. For these
1939 architectures, you should supply some command-line options at build
1940 time by entering them here. As a minimum, you should specify the
1941 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1944 prompt "Kernel command line type" if CMDLINE != ""
1945 default CMDLINE_FROM_BOOTLOADER
1948 config CMDLINE_FROM_BOOTLOADER
1949 bool "Use bootloader kernel arguments if available"
1951 Uses the command-line options passed by the boot loader. If
1952 the boot loader doesn't provide any, the default kernel command
1953 string provided in CMDLINE will be used.
1955 config CMDLINE_EXTEND
1956 bool "Extend bootloader kernel arguments"
1958 The command-line arguments provided by the boot loader will be
1959 appended to the default kernel command string.
1961 config CMDLINE_FORCE
1962 bool "Always use the default kernel command string"
1964 Always use the default kernel command string, even if the boot
1965 loader passes other arguments to the kernel.
1966 This is useful if you cannot or don't want to change the
1967 command-line options your boot loader passes to the kernel.
1971 bool "Kernel Execute-In-Place from ROM"
1972 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1974 Execute-In-Place allows the kernel to run from non-volatile storage
1975 directly addressable by the CPU, such as NOR flash. This saves RAM
1976 space since the text section of the kernel is not loaded from flash
1977 to RAM. Read-write sections, such as the data section and stack,
1978 are still copied to RAM. The XIP kernel is not compressed since
1979 it has to run directly from flash, so it will take more space to
1980 store it. The flash address used to link the kernel object files,
1981 and for storing it, is configuration dependent. Therefore, if you
1982 say Y here, you must know the proper physical address where to
1983 store the kernel image depending on your own flash memory usage.
1985 Also note that the make target becomes "make xipImage" rather than
1986 "make zImage" or "make Image". The final kernel binary to put in
1987 ROM memory will be arch/arm/boot/xipImage.
1991 config XIP_PHYS_ADDR
1992 hex "XIP Kernel Physical Location"
1993 depends on XIP_KERNEL
1994 default "0x00080000"
1996 This is the physical address in your flash memory the kernel will
1997 be linked for and stored to. This address is dependent on your
2001 bool "Kexec system call (EXPERIMENTAL)"
2002 depends on (!SMP || PM_SLEEP_SMP)
2004 kexec is a system call that implements the ability to shutdown your
2005 current kernel, and to start another kernel. It is like a reboot
2006 but it is independent of the system firmware. And like a reboot
2007 you can start any kernel with it, not just Linux.
2009 It is an ongoing process to be certain the hardware in a machine
2010 is properly shutdown, so do not be surprised if this code does not
2011 initially work for you.
2014 bool "Export atags in procfs"
2015 depends on ATAGS && KEXEC
2018 Should the atags used to boot the kernel be exported in an "atags"
2019 file in procfs. Useful with kexec.
2022 bool "Build kdump crash kernel (EXPERIMENTAL)"
2024 Generate crash dump after being started by kexec. This should
2025 be normally only set in special crash dump kernels which are
2026 loaded in the main kernel with kexec-tools into a specially
2027 reserved region and then later executed after a crash by
2028 kdump/kexec. The crash dump kernel must be compiled to a
2029 memory address not used by the main kernel
2031 For more details see Documentation/kdump/kdump.txt
2033 config AUTO_ZRELADDR
2034 bool "Auto calculation of the decompressed kernel image address"
2036 ZRELADDR is the physical address where the decompressed kernel
2037 image will be placed. If AUTO_ZRELADDR is selected, the address
2038 will be determined at run-time by masking the current IP with
2039 0xf8000000. This assumes the zImage being placed in the first 128MB
2040 from start of memory.
2044 menu "CPU Power Management"
2046 source "drivers/cpufreq/Kconfig"
2048 source "drivers/cpuidle/Kconfig"
2052 menu "Floating point emulation"
2054 comment "At least one emulation must be selected"
2057 bool "NWFPE math emulation"
2058 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2060 Say Y to include the NWFPE floating point emulator in the kernel.
2061 This is necessary to run most binaries. Linux does not currently
2062 support floating point hardware so you need to say Y here even if
2063 your machine has an FPA or floating point co-processor podule.
2065 You may say N here if you are going to load the Acorn FPEmulator
2066 early in the bootup.
2069 bool "Support extended precision"
2070 depends on FPE_NWFPE
2072 Say Y to include 80-bit support in the kernel floating-point
2073 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2074 Note that gcc does not generate 80-bit operations by default,
2075 so in most cases this option only enlarges the size of the
2076 floating point emulator without any good reason.
2078 You almost surely want to say N here.
2081 bool "FastFPE math emulation (EXPERIMENTAL)"
2082 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2084 Say Y here to include the FAST floating point emulator in the kernel.
2085 This is an experimental much faster emulator which now also has full
2086 precision for the mantissa. It does not support any exceptions.
2087 It is very simple, and approximately 3-6 times faster than NWFPE.
2089 It should be sufficient for most programs. It may be not suitable
2090 for scientific calculations, but you have to check this for yourself.
2091 If you do not feel you need a faster FP emulation you should better
2095 bool "VFP-format floating point maths"
2096 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2098 Say Y to include VFP support code in the kernel. This is needed
2099 if your hardware includes a VFP unit.
2101 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2102 release notes and additional status information.
2104 Say N if your target does not have VFP hardware.
2112 bool "Advanced SIMD (NEON) Extension support"
2113 depends on VFPv3 && CPU_V7
2115 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2118 config KERNEL_MODE_NEON
2119 bool "Support for NEON in kernel mode"
2120 depends on NEON && AEABI
2122 Say Y to include support for NEON in kernel mode.
2126 menu "Userspace binary formats"
2128 source "fs/Kconfig.binfmt"
2131 tristate "RISC OS personality"
2134 Say Y here to include the kernel code necessary if you want to run
2135 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2136 experimental; if this sounds frightening, say N and sleep in peace.
2137 You can also say M here to compile this support as a module (which
2138 will be called arthur).
2142 menu "Power management options"
2144 source "kernel/power/Kconfig"
2146 config ARCH_SUSPEND_POSSIBLE
2147 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2148 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2151 config ARM_CPU_SUSPEND
2154 config ARCH_HIBERNATION_POSSIBLE
2157 default y if ARCH_SUSPEND_POSSIBLE
2161 source "net/Kconfig"
2163 source "drivers/Kconfig"
2167 source "arch/arm/Kconfig.debug"
2169 source "security/Kconfig"
2171 source "crypto/Kconfig"
2173 source "lib/Kconfig"
2175 source "arch/arm/kvm/Kconfig"