4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
8 select ARCH_WANT_IPC_PARSE_VERSION
9 select BUILDTIME_EXTABLE_SORT if MMU
10 select CPU_PM if (SUSPEND || CPU_IDLE)
11 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
12 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
13 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
14 select GENERIC_IRQ_PROBE
15 select GENERIC_IRQ_SHOW
16 select GENERIC_PCI_IOMAP
17 select GENERIC_SMP_IDLE_THREAD
18 select GENERIC_STRNCPY_FROM_USER
19 select GENERIC_STRNLEN_USER
20 select HARDIRQS_SW_RESEND
22 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
24 select HAVE_ARCH_SECCOMP_FILTER
25 select HAVE_ARCH_TRACEHOOK
27 select HAVE_C_RECORDMCOUNT
28 select HAVE_DEBUG_KMEMLEAK
29 select HAVE_DMA_API_DEBUG
31 select HAVE_DMA_CONTIGUOUS if MMU
32 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
33 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
34 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
35 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
36 select HAVE_GENERIC_DMA_COHERENT
37 select HAVE_GENERIC_HARDIRQS
38 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
39 select HAVE_IDE if PCI || ISA || PCMCIA
40 select HAVE_KERNEL_GZIP
41 select HAVE_KERNEL_LZMA
42 select HAVE_KERNEL_LZO
44 select HAVE_KPROBES if !XIP_KERNEL
45 select HAVE_KRETPROBES if (HAVE_KPROBES)
47 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
48 select HAVE_PERF_EVENTS
49 select HAVE_REGS_AND_STACK_ACCESS_API
50 select HAVE_SYSCALL_TRACEPOINTS
53 select PERF_USE_VMALLOC
55 select SYS_SUPPORTS_APM_EMULATION
56 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
57 select MODULES_USE_ELF_REL
58 select CLONE_BACKWARDS
59 select OLD_SIGSUSPEND3
62 The ARM series is a line of low-power-consumption RISC chip designs
63 licensed by ARM Ltd and targeted at embedded applications and
64 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
65 manufactured, but legacy ARM-based PC hardware remains popular in
66 Europe. There is an ARM Linux project with a web page at
67 <http://www.arm.linux.org.uk/>.
69 config ARM_HAS_SG_CHAIN
72 config NEED_SG_DMA_LENGTH
75 config ARM_DMA_USE_IOMMU
77 select ARM_HAS_SG_CHAIN
78 select NEED_SG_DMA_LENGTH
82 config ARM_DMA_IOMMU_ALIGNMENT
83 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
87 DMA mapping framework by default aligns all buffers to the smallest
88 PAGE_SIZE order which is greater than or equal to the requested buffer
89 size. This works well for buffers up to a few hundreds kilobytes, but
90 for larger buffers it just a waste of address space. Drivers which has
91 relatively small addressing window (like 64Mib) might run out of
92 virtual space with just a few allocations.
94 With this parameter you can specify the maximum PAGE_SIZE order for
95 DMA IOMMU buffers. Larger buffers will be aligned only to this
96 specified order. The order is expressed as a power of two multiplied
104 config MIGHT_HAVE_PCI
107 config SYS_SUPPORTS_APM_EMULATION
115 select GENERIC_ALLOCATOR
126 The Extended Industry Standard Architecture (EISA) bus was
127 developed as an open alternative to the IBM MicroChannel bus.
129 The EISA bus provided some of the features of the IBM MicroChannel
130 bus while maintaining backward compatibility with cards made for
131 the older ISA bus. The EISA bus saw limited use between 1988 and
132 1995 when it was made obsolete by the PCI bus.
134 Say Y here if you are building a kernel for an EISA-based machine.
141 config STACKTRACE_SUPPORT
145 config HAVE_LATENCYTOP_SUPPORT
150 config LOCKDEP_SUPPORT
154 config TRACE_IRQFLAGS_SUPPORT
158 config RWSEM_GENERIC_SPINLOCK
162 config RWSEM_XCHGADD_ALGORITHM
165 config ARCH_HAS_ILOG2_U32
168 config ARCH_HAS_ILOG2_U64
171 config ARCH_HAS_CPUFREQ
174 Internal node to signify that the ARCH has CPUFREQ support
175 and that the relevant menu configurations are displayed for
178 config GENERIC_HWEIGHT
182 config GENERIC_CALIBRATE_DELAY
186 config ARCH_MAY_HAVE_PC_FDC
192 config NEED_DMA_MAP_STATE
195 config ARCH_HAS_DMA_SET_COHERENT_MASK
198 config GENERIC_ISA_DMA
204 config NEED_RET_TO_USER
212 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
213 default DRAM_BASE if REMAP_VECTORS_TO_RAM
216 The base address of exception vectors.
218 config ARM_PATCH_PHYS_VIRT
219 bool "Patch physical to virtual translations at runtime" if EMBEDDED
221 depends on !XIP_KERNEL && MMU
222 depends on !ARCH_REALVIEW || !SPARSEMEM
224 Patch phys-to-virt and virt-to-phys translation functions at
225 boot and module load time according to the position of the
226 kernel in system memory.
228 This can only be used with non-XIP MMU kernels where the base
229 of physical memory is at a 16MB boundary.
231 Only disable this option if you know that you do not require
232 this feature (eg, building a kernel for a single machine) and
233 you need to shrink the kernel to the minimal size.
235 config NEED_MACH_GPIO_H
238 Select this when mach/gpio.h is required to provide special
239 definitions for this platform. The need for mach/gpio.h should
240 be avoided when possible.
242 config NEED_MACH_IO_H
245 Select this when mach/io.h is required to provide special
246 definitions for this platform. The need for mach/io.h should
247 be avoided when possible.
249 config NEED_MACH_MEMORY_H
252 Select this when mach/memory.h is required to provide special
253 definitions for this platform. The need for mach/memory.h should
254 be avoided when possible.
257 hex "Physical address of main memory" if MMU
258 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
259 default DRAM_BASE if !MMU
261 Please provide the physical address corresponding to the
262 location of main memory in your system.
268 source "init/Kconfig"
270 source "kernel/Kconfig.freezer"
275 bool "MMU-based Paged Memory Management Support"
278 Select if you want MMU-based virtualised addressing space
279 support by paged memory management. If unsure, say 'Y'.
282 # The "ARM system type" choice list is ordered alphabetically by option
283 # text. Please add new entries in the option alphabetic order.
286 prompt "ARM system type"
287 default ARCH_VERSATILE if !MMU
288 default ARCH_MULTIPLATFORM if MMU
290 config ARCH_MULTIPLATFORM
291 bool "Allow multiple platforms to be selected"
293 select ARM_PATCH_PHYS_VIRT
296 select MULTI_IRQ_HANDLER
300 config ARCH_INTEGRATOR
301 bool "ARM Ltd. Integrator family"
302 select ARCH_HAS_CPUFREQ
305 select COMMON_CLK_VERSATILE
306 select GENERIC_CLOCKEVENTS
309 select MULTI_IRQ_HANDLER
310 select NEED_MACH_MEMORY_H
311 select PLAT_VERSATILE
313 select VERSATILE_FPGA_IRQ
315 Support for ARM's Integrator platform.
318 bool "ARM Ltd. RealView family"
319 select ARCH_WANT_OPTIONAL_GPIOLIB
321 select ARM_TIMER_SP804
323 select COMMON_CLK_VERSATILE
324 select GENERIC_CLOCKEVENTS
325 select GPIO_PL061 if GPIOLIB
327 select NEED_MACH_MEMORY_H
328 select PLAT_VERSATILE
329 select PLAT_VERSATILE_CLCD
331 This enables support for ARM Ltd RealView boards.
333 config ARCH_VERSATILE
334 bool "ARM Ltd. Versatile family"
335 select ARCH_WANT_OPTIONAL_GPIOLIB
337 select ARM_TIMER_SP804
340 select GENERIC_CLOCKEVENTS
341 select HAVE_MACH_CLKDEV
343 select PLAT_VERSATILE
344 select PLAT_VERSATILE_CLCD
345 select PLAT_VERSATILE_CLOCK
346 select VERSATILE_FPGA_IRQ
348 This enables support for ARM Ltd Versatile board.
352 select ARCH_REQUIRE_GPIOLIB
356 select NEED_MACH_GPIO_H
357 select NEED_MACH_IO_H if PCCARD
359 select PINCTRL_AT91 if USE_OF
361 This enables support for systems based on Atmel
362 AT91RM9200 and AT91SAM9* processors.
365 bool "Broadcom BCM2835 family"
366 select ARCH_REQUIRE_GPIOLIB
368 select ARM_ERRATA_411920
369 select ARM_TIMER_SP804
374 select GENERIC_CLOCKEVENTS
375 select MULTI_IRQ_HANDLER
377 select PINCTRL_BCM2835
381 This enables support for the Broadcom BCM2835 SoC. This SoC is
382 use in the Raspberry Pi, and Roku 2 devices.
385 bool "Cavium Networks CNS3XXX family"
388 select GENERIC_CLOCKEVENTS
389 select MIGHT_HAVE_CACHE_L2X0
390 select MIGHT_HAVE_PCI
391 select PCI_DOMAINS if PCI
393 Support for Cavium Networks CNS3XXX platform.
396 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
397 select ARCH_REQUIRE_GPIOLIB
402 select GENERIC_CLOCKEVENTS
403 select MULTI_IRQ_HANDLER
404 select NEED_MACH_MEMORY_H
407 Support for Cirrus Logic 711x/721x/731x based boards.
410 bool "Cortina Systems Gemini"
411 select ARCH_REQUIRE_GPIOLIB
412 select ARCH_USES_GETTIMEOFFSET
415 Support for the Cortina Systems Gemini family SoCs
419 select ARCH_REQUIRE_GPIOLIB
422 select GENERIC_CLOCKEVENTS
423 select GENERIC_IRQ_CHIP
424 select MIGHT_HAVE_CACHE_L2X0
430 Support for CSR SiRFprimaII/Marco/Polo platforms
434 select ARCH_USES_GETTIMEOFFSET
437 select NEED_MACH_IO_H
438 select NEED_MACH_MEMORY_H
441 This is an evaluation board for the StrongARM processor available
442 from Digital. It has limited hardware on-board, including an
443 Ethernet interface, two PCMCIA sockets, two serial ports and a
448 select ARCH_HAS_HOLES_MEMORYMODEL
449 select ARCH_REQUIRE_GPIOLIB
450 select ARCH_USES_GETTIMEOFFSET
455 select NEED_MACH_MEMORY_H
457 This enables support for the Cirrus EP93xx series of CPUs.
459 config ARCH_FOOTBRIDGE
463 select GENERIC_CLOCKEVENTS
465 select NEED_MACH_IO_H if !MMU
466 select NEED_MACH_MEMORY_H
468 Support for systems based on the DC21285 companion chip
469 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
472 bool "Freescale MXS-based"
473 select ARCH_REQUIRE_GPIOLIB
478 select GENERIC_CLOCKEVENTS
479 select HAVE_CLK_PREPARE
480 select MULTI_IRQ_HANDLER
486 Support for Freescale MXS-based family of processors
489 bool "Hilscher NetX based"
493 select GENERIC_CLOCKEVENTS
495 This enables support for systems based on the Hilscher NetX Soc
498 bool "Hynix HMS720x-based"
499 select ARCH_USES_GETTIMEOFFSET
503 This enables support for systems based on the Hynix HMS720x
508 select ARCH_SUPPORTS_MSI
510 select NEED_MACH_MEMORY_H
511 select NEED_RET_TO_USER
516 Support for Intel's IOP13XX (XScale) family of processors.
521 select ARCH_REQUIRE_GPIOLIB
523 select NEED_MACH_GPIO_H
524 select NEED_RET_TO_USER
528 Support for Intel's 80219 and IOP32X (XScale) family of
534 select ARCH_REQUIRE_GPIOLIB
536 select NEED_MACH_GPIO_H
537 select NEED_RET_TO_USER
541 Support for Intel's IOP33X (XScale) family of processors.
546 select ARCH_HAS_DMA_SET_COHERENT_MASK
547 select ARCH_REQUIRE_GPIOLIB
550 select DMABOUNCE if PCI
551 select GENERIC_CLOCKEVENTS
552 select MIGHT_HAVE_PCI
553 select NEED_MACH_IO_H
555 Support for Intel's IXP4XX (XScale) family of processors.
559 select ARCH_REQUIRE_GPIOLIB
561 select GENERIC_CLOCKEVENTS
562 select MIGHT_HAVE_PCI
565 select PLAT_ORION_LEGACY
566 select USB_ARCH_HAS_EHCI
568 Support for the Marvell Dove SoC 88AP510
571 bool "Marvell Kirkwood"
572 select ARCH_REQUIRE_GPIOLIB
574 select GENERIC_CLOCKEVENTS
578 select PINCTRL_KIRKWOOD
579 select PLAT_ORION_LEGACY
581 Support for the following Marvell Kirkwood series SoCs:
582 88F6180, 88F6192 and 88F6281.
585 bool "Marvell MV78xx0"
586 select ARCH_REQUIRE_GPIOLIB
588 select GENERIC_CLOCKEVENTS
590 select PLAT_ORION_LEGACY
592 Support for the following Marvell MV78xx0 series SoCs:
598 select ARCH_REQUIRE_GPIOLIB
600 select GENERIC_CLOCKEVENTS
602 select PLAT_ORION_LEGACY
604 Support for the following Marvell Orion 5x series SoCs:
605 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
606 Orion-2 (5281), Orion-1-90 (6183).
609 bool "Marvell PXA168/910/MMP2"
611 select ARCH_REQUIRE_GPIOLIB
613 select GENERIC_ALLOCATOR
614 select GENERIC_CLOCKEVENTS
617 select NEED_MACH_GPIO_H
622 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
625 bool "Micrel/Kendin KS8695"
626 select ARCH_REQUIRE_GPIOLIB
629 select GENERIC_CLOCKEVENTS
630 select NEED_MACH_MEMORY_H
632 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
633 System-on-Chip devices.
636 bool "Nuvoton W90X900 CPU"
637 select ARCH_REQUIRE_GPIOLIB
641 select GENERIC_CLOCKEVENTS
643 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
644 At present, the w90x900 has been renamed nuc900, regarding
645 the ARM series product line, you can login the following
646 link address to know more.
648 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
649 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
653 select ARCH_REQUIRE_GPIOLIB
658 select GENERIC_CLOCKEVENTS
661 select USB_ARCH_HAS_OHCI
664 Support for the NXP LPC32XX family of processors
668 select ARCH_HAS_CPUFREQ
669 select ARCH_REQUIRE_GPIOLIB
674 select GENERIC_CLOCKEVENTS
677 select MIGHT_HAVE_CACHE_L2X0
681 This enables support for NVIDIA Tegra based systems (Tegra APX,
682 Tegra 6xx and Tegra 2 series).
685 bool "PXA2xx/PXA3xx-based"
687 select ARCH_HAS_CPUFREQ
689 select ARCH_REQUIRE_GPIOLIB
690 select ARM_CPU_SUSPEND if PM
694 select GENERIC_CLOCKEVENTS
697 select MULTI_IRQ_HANDLER
698 select NEED_MACH_GPIO_H
702 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
706 select ARCH_REQUIRE_GPIOLIB
708 select GENERIC_CLOCKEVENTS
711 Support for Qualcomm MSM/QSD based systems. This runs on the
712 apps processor of the MSM/QSD and depends on a shared memory
713 interface to the modem processor which runs the baseband
714 stack and controls some vital subsystems
715 (clock and power control, etc).
718 bool "Renesas SH-Mobile / R-Mobile"
720 select GENERIC_CLOCKEVENTS
722 select HAVE_MACH_CLKDEV
724 select MIGHT_HAVE_CACHE_L2X0
725 select MULTI_IRQ_HANDLER
726 select NEED_MACH_MEMORY_H
729 select PM_GENERIC_DOMAINS if PM
732 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
737 select ARCH_MAY_HAVE_PC_FDC
738 select ARCH_SPARSEMEM_ENABLE
739 select ARCH_USES_GETTIMEOFFSET
742 select HAVE_PATA_PLATFORM
744 select NEED_MACH_IO_H
745 select NEED_MACH_MEMORY_H
749 On the Acorn Risc-PC, Linux can support the internal IDE disk and
750 CD-ROM interface, serial and parallel port, and the floppy drive.
754 select ARCH_HAS_CPUFREQ
756 select ARCH_REQUIRE_GPIOLIB
757 select ARCH_SPARSEMEM_ENABLE
762 select GENERIC_CLOCKEVENTS
765 select NEED_MACH_GPIO_H
766 select NEED_MACH_MEMORY_H
769 Support for StrongARM 11x0 based boards.
772 bool "Samsung S3C24XX SoCs"
773 select ARCH_HAS_CPUFREQ
774 select ARCH_USES_GETTIMEOFFSET
777 select HAVE_S3C2410_I2C if I2C
778 select HAVE_S3C2410_WATCHDOG if WATCHDOG
779 select HAVE_S3C_RTC if RTC_CLASS
780 select NEED_MACH_GPIO_H
781 select NEED_MACH_IO_H
783 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
784 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
785 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
786 Samsung SMDK2410 development board (and derivatives).
789 bool "Samsung S3C64XX"
790 select ARCH_HAS_CPUFREQ
791 select ARCH_REQUIRE_GPIOLIB
792 select ARCH_USES_GETTIMEOFFSET
797 select HAVE_S3C2410_I2C if I2C
798 select HAVE_S3C2410_WATCHDOG if WATCHDOG
800 select NEED_MACH_GPIO_H
804 select S3C_GPIO_TRACK
805 select SAMSUNG_CLKSRC
806 select SAMSUNG_GPIOLIB_4BIT
807 select SAMSUNG_IRQ_VIC_TIMER
808 select USB_ARCH_HAS_OHCI
810 Samsung S3C64XX series based systems
813 bool "Samsung S5P6440 S5P6450"
817 select GENERIC_CLOCKEVENTS
819 select HAVE_S3C2410_I2C if I2C
820 select HAVE_S3C2410_WATCHDOG if WATCHDOG
821 select HAVE_S3C_RTC if RTC_CLASS
822 select NEED_MACH_GPIO_H
824 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
828 bool "Samsung S5PC100"
829 select ARCH_USES_GETTIMEOFFSET
833 select HAVE_S3C2410_I2C if I2C
834 select HAVE_S3C2410_WATCHDOG if WATCHDOG
835 select HAVE_S3C_RTC if RTC_CLASS
836 select NEED_MACH_GPIO_H
838 Samsung S5PC100 series based systems
841 bool "Samsung S5PV210/S5PC110"
842 select ARCH_HAS_CPUFREQ
843 select ARCH_HAS_HOLES_MEMORYMODEL
844 select ARCH_SPARSEMEM_ENABLE
848 select GENERIC_CLOCKEVENTS
850 select HAVE_S3C2410_I2C if I2C
851 select HAVE_S3C2410_WATCHDOG if WATCHDOG
852 select HAVE_S3C_RTC if RTC_CLASS
853 select NEED_MACH_GPIO_H
854 select NEED_MACH_MEMORY_H
856 Samsung S5PV210/S5PC110 series based systems
859 bool "Samsung EXYNOS"
860 select ARCH_HAS_CPUFREQ
861 select ARCH_HAS_HOLES_MEMORYMODEL
862 select ARCH_SPARSEMEM_ENABLE
865 select GENERIC_CLOCKEVENTS
867 select HAVE_S3C2410_I2C if I2C
868 select HAVE_S3C2410_WATCHDOG if WATCHDOG
869 select HAVE_S3C_RTC if RTC_CLASS
870 select NEED_MACH_GPIO_H
871 select NEED_MACH_MEMORY_H
873 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
877 select ARCH_USES_GETTIMEOFFSET
881 select NEED_MACH_MEMORY_H
886 Support for the StrongARM based Digital DNARD machine, also known
887 as "Shark" (<http://www.shark-linux.de/shark.html>).
890 bool "ST-Ericsson U300 Series"
892 select ARCH_REQUIRE_GPIOLIB
894 select ARM_PATCH_PHYS_VIRT
900 select GENERIC_CLOCKEVENTS
904 Support for ST-Ericsson U300 series mobile platforms.
907 bool "ST-Ericsson U8500 Series"
909 select ARCH_HAS_CPUFREQ
910 select ARCH_REQUIRE_GPIOLIB
914 select GENERIC_CLOCKEVENTS
916 select MIGHT_HAVE_CACHE_L2X0
919 Support for ST-Ericsson's Ux500 architecture
922 bool "STMicroelectronics Nomadik"
923 select ARCH_REQUIRE_GPIOLIB
926 select CLKSRC_NOMADIK_MTU
929 select GENERIC_CLOCKEVENTS
930 select MIGHT_HAVE_CACHE_L2X0
933 select PINCTRL_STN8815
936 Support for the Nomadik platform by ST-Ericsson
940 select ARCH_HAS_CPUFREQ
941 select ARCH_REQUIRE_GPIOLIB
946 select GENERIC_CLOCKEVENTS
949 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
953 select ARCH_HAS_HOLES_MEMORYMODEL
954 select ARCH_REQUIRE_GPIOLIB
956 select GENERIC_ALLOCATOR
957 select GENERIC_CLOCKEVENTS
958 select GENERIC_IRQ_CHIP
960 select NEED_MACH_GPIO_H
964 Support for TI's DaVinci platform.
969 select ARCH_HAS_CPUFREQ
970 select ARCH_HAS_HOLES_MEMORYMODEL
972 select ARCH_REQUIRE_GPIOLIB
975 select GENERIC_CLOCKEVENTS
976 select GENERIC_IRQ_CHIP
980 select NEED_MACH_IO_H if PCCARD
981 select NEED_MACH_MEMORY_H
983 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
987 menu "Multiple platform selection"
988 depends on ARCH_MULTIPLATFORM
990 comment "CPU Core family selection"
993 bool "ARMv4 based platforms (FA526, StrongARM)"
994 depends on !ARCH_MULTI_V6_V7
995 select ARCH_MULTI_V4_V5
997 config ARCH_MULTI_V4T
998 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
999 depends on !ARCH_MULTI_V6_V7
1000 select ARCH_MULTI_V4_V5
1002 config ARCH_MULTI_V5
1003 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
1004 depends on !ARCH_MULTI_V6_V7
1005 select ARCH_MULTI_V4_V5
1007 config ARCH_MULTI_V4_V5
1010 config ARCH_MULTI_V6
1011 bool "ARMv6 based platforms (ARM11)"
1012 select ARCH_MULTI_V6_V7
1015 config ARCH_MULTI_V7
1016 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
1018 select ARCH_MULTI_V6_V7
1019 select ARCH_VEXPRESS
1022 config ARCH_MULTI_V6_V7
1025 config ARCH_MULTI_CPU_AUTO
1026 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
1027 select ARCH_MULTI_V5
1032 # This is sorted alphabetically by mach-* pathname. However, plat-*
1033 # Kconfigs may be included either alphabetically (according to the
1034 # plat- suffix) or along side the corresponding mach-* source.
1036 source "arch/arm/mach-mvebu/Kconfig"
1038 source "arch/arm/mach-at91/Kconfig"
1040 source "arch/arm/mach-bcm/Kconfig"
1042 source "arch/arm/mach-clps711x/Kconfig"
1044 source "arch/arm/mach-cns3xxx/Kconfig"
1046 source "arch/arm/mach-davinci/Kconfig"
1048 source "arch/arm/mach-dove/Kconfig"
1050 source "arch/arm/mach-ep93xx/Kconfig"
1052 source "arch/arm/mach-footbridge/Kconfig"
1054 source "arch/arm/mach-gemini/Kconfig"
1056 source "arch/arm/mach-h720x/Kconfig"
1058 source "arch/arm/mach-highbank/Kconfig"
1060 source "arch/arm/mach-integrator/Kconfig"
1062 source "arch/arm/mach-iop32x/Kconfig"
1064 source "arch/arm/mach-iop33x/Kconfig"
1066 source "arch/arm/mach-iop13xx/Kconfig"
1068 source "arch/arm/mach-ixp4xx/Kconfig"
1070 source "arch/arm/mach-kirkwood/Kconfig"
1072 source "arch/arm/mach-ks8695/Kconfig"
1074 source "arch/arm/mach-msm/Kconfig"
1076 source "arch/arm/mach-mv78xx0/Kconfig"
1078 source "arch/arm/mach-imx/Kconfig"
1080 source "arch/arm/mach-mxs/Kconfig"
1082 source "arch/arm/mach-netx/Kconfig"
1084 source "arch/arm/mach-nomadik/Kconfig"
1086 source "arch/arm/plat-omap/Kconfig"
1088 source "arch/arm/mach-omap1/Kconfig"
1090 source "arch/arm/mach-omap2/Kconfig"
1092 source "arch/arm/mach-orion5x/Kconfig"
1094 source "arch/arm/mach-picoxcell/Kconfig"
1096 source "arch/arm/mach-pxa/Kconfig"
1097 source "arch/arm/plat-pxa/Kconfig"
1099 source "arch/arm/mach-mmp/Kconfig"
1101 source "arch/arm/mach-realview/Kconfig"
1103 source "arch/arm/mach-sa1100/Kconfig"
1105 source "arch/arm/plat-samsung/Kconfig"
1107 source "arch/arm/mach-socfpga/Kconfig"
1109 source "arch/arm/plat-spear/Kconfig"
1111 source "arch/arm/mach-s3c24xx/Kconfig"
1114 source "arch/arm/mach-s3c64xx/Kconfig"
1117 source "arch/arm/mach-s5p64x0/Kconfig"
1119 source "arch/arm/mach-s5pc100/Kconfig"
1121 source "arch/arm/mach-s5pv210/Kconfig"
1123 source "arch/arm/mach-exynos/Kconfig"
1125 source "arch/arm/mach-shmobile/Kconfig"
1127 source "arch/arm/mach-sunxi/Kconfig"
1129 source "arch/arm/mach-prima2/Kconfig"
1131 source "arch/arm/mach-tegra/Kconfig"
1133 source "arch/arm/mach-u300/Kconfig"
1135 source "arch/arm/mach-ux500/Kconfig"
1137 source "arch/arm/mach-versatile/Kconfig"
1139 source "arch/arm/mach-vexpress/Kconfig"
1140 source "arch/arm/plat-versatile/Kconfig"
1142 source "arch/arm/mach-virt/Kconfig"
1144 source "arch/arm/mach-vt8500/Kconfig"
1146 source "arch/arm/mach-w90x900/Kconfig"
1148 source "arch/arm/mach-zynq/Kconfig"
1150 # Definitions to make life easier
1156 select GENERIC_CLOCKEVENTS
1162 select GENERIC_IRQ_CHIP
1165 config PLAT_ORION_LEGACY
1172 config PLAT_VERSATILE
1175 config ARM_TIMER_SP804
1178 select HAVE_SCHED_CLOCK
1180 source arch/arm/mm/Kconfig
1184 default 16 if ARCH_EP93XX
1188 bool "Enable iWMMXt support"
1189 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1190 default y if PXA27x || PXA3xx || ARCH_MMP
1192 Enable support for iWMMXt context switching at run time if
1193 running on a CPU that supports it.
1197 depends on CPU_XSCALE
1200 config MULTI_IRQ_HANDLER
1203 Allow each machine to specify it's own IRQ handler at run time.
1206 source "arch/arm/Kconfig-nommu"
1209 config ARM_ERRATA_326103
1210 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1213 Executing a SWP instruction to read-only memory does not set bit 11
1214 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1215 treat the access as a read, preventing a COW from occurring and
1216 causing the faulting task to livelock.
1218 config ARM_ERRATA_411920
1219 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1220 depends on CPU_V6 || CPU_V6K
1222 Invalidation of the Instruction Cache operation can
1223 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1224 It does not affect the MPCore. This option enables the ARM Ltd.
1225 recommended workaround.
1227 config ARM_ERRATA_430973
1228 bool "ARM errata: Stale prediction on replaced interworking branch"
1231 This option enables the workaround for the 430973 Cortex-A8
1232 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1233 interworking branch is replaced with another code sequence at the
1234 same virtual address, whether due to self-modifying code or virtual
1235 to physical address re-mapping, Cortex-A8 does not recover from the
1236 stale interworking branch prediction. This results in Cortex-A8
1237 executing the new code sequence in the incorrect ARM or Thumb state.
1238 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1239 and also flushes the branch target cache at every context switch.
1240 Note that setting specific bits in the ACTLR register may not be
1241 available in non-secure mode.
1243 config ARM_ERRATA_458693
1244 bool "ARM errata: Processor deadlock when a false hazard is created"
1246 depends on !ARCH_MULTIPLATFORM
1248 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1249 erratum. For very specific sequences of memory operations, it is
1250 possible for a hazard condition intended for a cache line to instead
1251 be incorrectly associated with a different cache line. This false
1252 hazard might then cause a processor deadlock. The workaround enables
1253 the L1 caching of the NEON accesses and disables the PLD instruction
1254 in the ACTLR register. Note that setting specific bits in the ACTLR
1255 register may not be available in non-secure mode.
1257 config ARM_ERRATA_460075
1258 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1260 depends on !ARCH_MULTIPLATFORM
1262 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1263 erratum. Any asynchronous access to the L2 cache may encounter a
1264 situation in which recent store transactions to the L2 cache are lost
1265 and overwritten with stale memory contents from external memory. The
1266 workaround disables the write-allocate mode for the L2 cache via the
1267 ACTLR register. Note that setting specific bits in the ACTLR register
1268 may not be available in non-secure mode.
1270 config ARM_ERRATA_742230
1271 bool "ARM errata: DMB operation may be faulty"
1272 depends on CPU_V7 && SMP
1273 depends on !ARCH_MULTIPLATFORM
1275 This option enables the workaround for the 742230 Cortex-A9
1276 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1277 between two write operations may not ensure the correct visibility
1278 ordering of the two writes. This workaround sets a specific bit in
1279 the diagnostic register of the Cortex-A9 which causes the DMB
1280 instruction to behave as a DSB, ensuring the correct behaviour of
1283 config ARM_ERRATA_742231
1284 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1285 depends on CPU_V7 && SMP
1286 depends on !ARCH_MULTIPLATFORM
1288 This option enables the workaround for the 742231 Cortex-A9
1289 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1290 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1291 accessing some data located in the same cache line, may get corrupted
1292 data due to bad handling of the address hazard when the line gets
1293 replaced from one of the CPUs at the same time as another CPU is
1294 accessing it. This workaround sets specific bits in the diagnostic
1295 register of the Cortex-A9 which reduces the linefill issuing
1296 capabilities of the processor.
1298 config PL310_ERRATA_588369
1299 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1300 depends on CACHE_L2X0
1302 The PL310 L2 cache controller implements three types of Clean &
1303 Invalidate maintenance operations: by Physical Address
1304 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1305 They are architecturally defined to behave as the execution of a
1306 clean operation followed immediately by an invalidate operation,
1307 both performing to the same memory location. This functionality
1308 is not correctly implemented in PL310 as clean lines are not
1309 invalidated as a result of these operations.
1311 config ARM_ERRATA_720789
1312 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1315 This option enables the workaround for the 720789 Cortex-A9 (prior to
1316 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1317 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1318 As a consequence of this erratum, some TLB entries which should be
1319 invalidated are not, resulting in an incoherency in the system page
1320 tables. The workaround changes the TLB flushing routines to invalidate
1321 entries regardless of the ASID.
1323 config PL310_ERRATA_727915
1324 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1325 depends on CACHE_L2X0
1327 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1328 operation (offset 0x7FC). This operation runs in background so that
1329 PL310 can handle normal accesses while it is in progress. Under very
1330 rare circumstances, due to this erratum, write data can be lost when
1331 PL310 treats a cacheable write transaction during a Clean &
1332 Invalidate by Way operation.
1334 config ARM_ERRATA_743622
1335 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1337 depends on !ARCH_MULTIPLATFORM
1339 This option enables the workaround for the 743622 Cortex-A9
1340 (r2p*) erratum. Under very rare conditions, a faulty
1341 optimisation in the Cortex-A9 Store Buffer may lead to data
1342 corruption. This workaround sets a specific bit in the diagnostic
1343 register of the Cortex-A9 which disables the Store Buffer
1344 optimisation, preventing the defect from occurring. This has no
1345 visible impact on the overall performance or power consumption of the
1348 config ARM_ERRATA_751472
1349 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1351 depends on !ARCH_MULTIPLATFORM
1353 This option enables the workaround for the 751472 Cortex-A9 (prior
1354 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1355 completion of a following broadcasted operation if the second
1356 operation is received by a CPU before the ICIALLUIS has completed,
1357 potentially leading to corrupted entries in the cache or TLB.
1359 config PL310_ERRATA_753970
1360 bool "PL310 errata: cache sync operation may be faulty"
1361 depends on CACHE_PL310
1363 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1365 Under some condition the effect of cache sync operation on
1366 the store buffer still remains when the operation completes.
1367 This means that the store buffer is always asked to drain and
1368 this prevents it from merging any further writes. The workaround
1369 is to replace the normal offset of cache sync operation (0x730)
1370 by another offset targeting an unmapped PL310 register 0x740.
1371 This has the same effect as the cache sync operation: store buffer
1372 drain and waiting for all buffers empty.
1374 config ARM_ERRATA_754322
1375 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1378 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1379 r3p*) erratum. A speculative memory access may cause a page table walk
1380 which starts prior to an ASID switch but completes afterwards. This
1381 can populate the micro-TLB with a stale entry which may be hit with
1382 the new ASID. This workaround places two dsb instructions in the mm
1383 switching code so that no page table walks can cross the ASID switch.
1385 config ARM_ERRATA_754327
1386 bool "ARM errata: no automatic Store Buffer drain"
1387 depends on CPU_V7 && SMP
1389 This option enables the workaround for the 754327 Cortex-A9 (prior to
1390 r2p0) erratum. The Store Buffer does not have any automatic draining
1391 mechanism and therefore a livelock may occur if an external agent
1392 continuously polls a memory location waiting to observe an update.
1393 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1394 written polling loops from denying visibility of updates to memory.
1396 config ARM_ERRATA_364296
1397 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1398 depends on CPU_V6 && !SMP
1400 This options enables the workaround for the 364296 ARM1136
1401 r0p2 erratum (possible cache data corruption with
1402 hit-under-miss enabled). It sets the undocumented bit 31 in
1403 the auxiliary control register and the FI bit in the control
1404 register, thus disabling hit-under-miss without putting the
1405 processor into full low interrupt latency mode. ARM11MPCore
1408 config ARM_ERRATA_764369
1409 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1410 depends on CPU_V7 && SMP
1412 This option enables the workaround for erratum 764369
1413 affecting Cortex-A9 MPCore with two or more processors (all
1414 current revisions). Under certain timing circumstances, a data
1415 cache line maintenance operation by MVA targeting an Inner
1416 Shareable memory region may fail to proceed up to either the
1417 Point of Coherency or to the Point of Unification of the
1418 system. This workaround adds a DSB instruction before the
1419 relevant cache maintenance functions and sets a specific bit
1420 in the diagnostic control register of the SCU.
1422 config PL310_ERRATA_769419
1423 bool "PL310 errata: no automatic Store Buffer drain"
1424 depends on CACHE_L2X0
1426 On revisions of the PL310 prior to r3p2, the Store Buffer does
1427 not automatically drain. This can cause normal, non-cacheable
1428 writes to be retained when the memory system is idle, leading
1429 to suboptimal I/O performance for drivers using coherent DMA.
1430 This option adds a write barrier to the cpu_idle loop so that,
1431 on systems with an outer cache, the store buffer is drained
1434 config ARM_ERRATA_775420
1435 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1438 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1439 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1440 operation aborts with MMU exception, it might cause the processor
1441 to deadlock. This workaround puts DSB before executing ISB if
1442 an abort may occur on cache maintenance.
1446 source "arch/arm/common/Kconfig"
1456 Find out whether you have ISA slots on your motherboard. ISA is the
1457 name of a bus system, i.e. the way the CPU talks to the other stuff
1458 inside your box. Other bus systems are PCI, EISA, MicroChannel
1459 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1460 newer boards don't support it. If you have ISA, say Y, otherwise N.
1462 # Select ISA DMA controller support
1467 # Select ISA DMA interface
1472 bool "PCI support" if MIGHT_HAVE_PCI
1474 Find out whether you have a PCI motherboard. PCI is the name of a
1475 bus system, i.e. the way the CPU talks to the other stuff inside
1476 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1477 VESA. If you have PCI, say Y, otherwise N.
1483 config PCI_NANOENGINE
1484 bool "BSE nanoEngine PCI support"
1485 depends on SA1100_NANOENGINE
1487 Enable PCI on the BSE nanoEngine board.
1492 # Select the host bridge type
1493 config PCI_HOST_VIA82C505
1495 depends on PCI && ARCH_SHARK
1498 config PCI_HOST_ITE8152
1500 depends on PCI && MACH_ARMCORE
1504 source "drivers/pci/Kconfig"
1506 source "drivers/pcmcia/Kconfig"
1510 menu "Kernel Features"
1515 This option should be selected by machines which have an SMP-
1518 The only effect of this option is to make the SMP-related
1519 options available to the user for configuration.
1522 bool "Symmetric Multi-Processing"
1523 depends on CPU_V6K || CPU_V7
1524 depends on GENERIC_CLOCKEVENTS
1527 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1528 select USE_GENERIC_SMP_HELPERS
1530 This enables support for systems with more than one CPU. If you have
1531 a system with only one CPU, like most personal computers, say N. If
1532 you have a system with more than one CPU, say Y.
1534 If you say N here, the kernel will run on single and multiprocessor
1535 machines, but will use only one CPU of a multiprocessor machine. If
1536 you say Y here, the kernel will run on many, but not all, single
1537 processor machines. On a single processor machine, the kernel will
1538 run faster if you say N here.
1540 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1541 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1542 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1544 If you don't know what to do here, say N.
1547 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1548 depends on SMP && !XIP_KERNEL
1551 SMP kernels contain instructions which fail on non-SMP processors.
1552 Enabling this option allows the kernel to modify itself to make
1553 these instructions safe. Disabling it allows about 1K of space
1556 If you don't know what to do here, say Y.
1558 config ARM_CPU_TOPOLOGY
1559 bool "Support cpu topology definition"
1560 depends on SMP && CPU_V7
1563 Support ARM cpu topology definition. The MPIDR register defines
1564 affinity between processors which is then used to describe the cpu
1565 topology of an ARM System.
1568 bool "Multi-core scheduler support"
1569 depends on ARM_CPU_TOPOLOGY
1571 Multi-core scheduler support improves the CPU scheduler's decision
1572 making when dealing with multi-core CPU chips at a cost of slightly
1573 increased overhead in some places. If unsure say N here.
1576 bool "SMT scheduler support"
1577 depends on ARM_CPU_TOPOLOGY
1579 Improves the CPU scheduler's decision making when dealing with
1580 MultiThreading at a cost of slightly increased overhead in some
1581 places. If unsure say N here.
1586 This option enables support for the ARM system coherency unit
1588 config HAVE_ARM_ARCH_TIMER
1589 bool "Architected timer support"
1591 select ARM_ARCH_TIMER
1593 This option enables support for the ARM architected timer
1598 select CLKSRC_OF if OF
1600 This options enables support for the ARM timer and watchdog unit
1603 prompt "Memory split"
1606 Select the desired split between kernel and user memory.
1608 If you are not absolutely sure what you are doing, leave this
1612 bool "3G/1G user/kernel split"
1614 bool "2G/2G user/kernel split"
1616 bool "1G/3G user/kernel split"
1621 default 0x40000000 if VMSPLIT_1G
1622 default 0x80000000 if VMSPLIT_2G
1626 int "Maximum number of CPUs (2-32)"
1632 bool "Support for hot-pluggable CPUs"
1633 depends on SMP && HOTPLUG
1635 Say Y here to experiment with turning CPUs off and on. CPUs
1636 can be controlled through /sys/devices/system/cpu.
1639 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1642 Say Y here if you want Linux to communicate with system firmware
1643 implementing the PSCI specification for CPU-centric power
1644 management operations described in ARM document number ARM DEN
1645 0022A ("Power State Coordination Interface System Software on
1649 bool "Use local timer interrupts"
1652 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1654 Enable support for local timers on SMP platforms, rather then the
1655 legacy IPI broadcast method. Local timers allows the system
1656 accounting to be spread across the timer interval, preventing a
1657 "thundering herd" at every timer tick.
1659 # The GPIO number here must be sorted by descending number. In case of
1660 # a multiplatform kernel, we just want the highest value required by the
1661 # selected platforms.
1664 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1665 default 512 if SOC_OMAP5
1666 default 355 if ARCH_U8500
1667 default 288 if ARCH_VT8500 || ARCH_SUNXI
1668 default 264 if MACH_H4700
1671 Maximum number of GPIOs in the system.
1673 If unsure, leave the default value.
1675 source kernel/Kconfig.preempt
1679 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1680 ARCH_S5PV210 || ARCH_EXYNOS4
1681 default AT91_TIMER_HZ if ARCH_AT91
1682 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1686 def_bool HIGH_RES_TIMERS
1688 config THUMB2_KERNEL
1689 bool "Compile the kernel in Thumb-2 mode"
1690 depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1692 select ARM_ASM_UNIFIED
1695 By enabling this option, the kernel will be compiled in
1696 Thumb-2 mode. A compiler/assembler that understand the unified
1697 ARM-Thumb syntax is needed.
1701 config THUMB2_AVOID_R_ARM_THM_JUMP11
1702 bool "Work around buggy Thumb-2 short branch relocations in gas"
1703 depends on THUMB2_KERNEL && MODULES
1706 Various binutils versions can resolve Thumb-2 branches to
1707 locally-defined, preemptible global symbols as short-range "b.n"
1708 branch instructions.
1710 This is a problem, because there's no guarantee the final
1711 destination of the symbol, or any candidate locations for a
1712 trampoline, are within range of the branch. For this reason, the
1713 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1714 relocation in modules at all, and it makes little sense to add
1717 The symptom is that the kernel fails with an "unsupported
1718 relocation" error when loading some modules.
1720 Until fixed tools are available, passing
1721 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1722 code which hits this problem, at the cost of a bit of extra runtime
1723 stack usage in some cases.
1725 The problem is described in more detail at:
1726 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1728 Only Thumb-2 kernels are affected.
1730 Unless you are sure your tools don't have this problem, say Y.
1732 config ARM_ASM_UNIFIED
1736 bool "Use the ARM EABI to compile the kernel"
1738 This option allows for the kernel to be compiled using the latest
1739 ARM ABI (aka EABI). This is only useful if you are using a user
1740 space environment that is also compiled with EABI.
1742 Since there are major incompatibilities between the legacy ABI and
1743 EABI, especially with regard to structure member alignment, this
1744 option also changes the kernel syscall calling convention to
1745 disambiguate both ABIs and allow for backward compatibility support
1746 (selected with CONFIG_OABI_COMPAT).
1748 To use this you need GCC version 4.0.0 or later.
1751 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1752 depends on AEABI && !THUMB2_KERNEL
1755 This option preserves the old syscall interface along with the
1756 new (ARM EABI) one. It also provides a compatibility layer to
1757 intercept syscalls that have structure arguments which layout
1758 in memory differs between the legacy ABI and the new ARM EABI
1759 (only for non "thumb" binaries). This option adds a tiny
1760 overhead to all syscalls and produces a slightly larger kernel.
1761 If you know you'll be using only pure EABI user space then you
1762 can say N here. If this option is not selected and you attempt
1763 to execute a legacy ABI binary then the result will be
1764 UNPREDICTABLE (in fact it can be predicted that it won't work
1765 at all). If in doubt say Y.
1767 config ARCH_HAS_HOLES_MEMORYMODEL
1770 config ARCH_SPARSEMEM_ENABLE
1773 config ARCH_SPARSEMEM_DEFAULT
1774 def_bool ARCH_SPARSEMEM_ENABLE
1776 config ARCH_SELECT_MEMORY_MODEL
1777 def_bool ARCH_SPARSEMEM_ENABLE
1779 config HAVE_ARCH_PFN_VALID
1780 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1783 bool "High Memory Support"
1786 The address space of ARM processors is only 4 Gigabytes large
1787 and it has to accommodate user address space, kernel address
1788 space as well as some memory mapped IO. That means that, if you
1789 have a large amount of physical memory and/or IO, not all of the
1790 memory can be "permanently mapped" by the kernel. The physical
1791 memory that is not permanently mapped is called "high memory".
1793 Depending on the selected kernel/user memory split, minimum
1794 vmalloc space and actual amount of RAM, you may not need this
1795 option which should result in a slightly faster kernel.
1800 bool "Allocate 2nd-level pagetables from highmem"
1803 config HW_PERF_EVENTS
1804 bool "Enable hardware performance counter support for perf events"
1805 depends on PERF_EVENTS
1808 Enable hardware performance counter support for perf events. If
1809 disabled, perf events will use software events only.
1813 config FORCE_MAX_ZONEORDER
1814 int "Maximum zone order" if ARCH_SHMOBILE
1815 range 11 64 if ARCH_SHMOBILE
1816 default "12" if SOC_AM33XX
1817 default "9" if SA1111
1820 The kernel memory allocator divides physically contiguous memory
1821 blocks into "zones", where each zone is a power of two number of
1822 pages. This option selects the largest power of two that the kernel
1823 keeps in the memory allocator. If you need to allocate very large
1824 blocks of physically contiguous memory, then you may need to
1825 increase this value.
1827 This config option is actually maximum order plus one. For example,
1828 a value of 11 means that the largest free memory block is 2^10 pages.
1830 config ALIGNMENT_TRAP
1832 depends on CPU_CP15_MMU
1833 default y if !ARCH_EBSA110
1834 select HAVE_PROC_CPU if PROC_FS
1836 ARM processors cannot fetch/store information which is not
1837 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1838 address divisible by 4. On 32-bit ARM processors, these non-aligned
1839 fetch/store instructions will be emulated in software if you say
1840 here, which has a severe performance impact. This is necessary for
1841 correct operation of some network protocols. With an IP-only
1842 configuration it is safe to say N, otherwise say Y.
1844 config UACCESS_WITH_MEMCPY
1845 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1847 default y if CPU_FEROCEON
1849 Implement faster copy_to_user and clear_user methods for CPU
1850 cores where a 8-word STM instruction give significantly higher
1851 memory write throughput than a sequence of individual 32bit stores.
1853 A possible side effect is a slight increase in scheduling latency
1854 between threads sharing the same address space if they invoke
1855 such copy operations with large buffers.
1857 However, if the CPU data cache is using a write-allocate mode,
1858 this option is unlikely to provide any performance gain.
1862 prompt "Enable seccomp to safely compute untrusted bytecode"
1864 This kernel feature is useful for number crunching applications
1865 that may need to compute untrusted bytecode during their
1866 execution. By using pipes or other transports made available to
1867 the process as file descriptors supporting the read/write
1868 syscalls, it's possible to isolate those applications in
1869 their own address space using seccomp. Once seccomp is
1870 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1871 and the task is only allowed to execute a few safe syscalls
1872 defined by each seccomp mode.
1874 config CC_STACKPROTECTOR
1875 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1877 This option turns on the -fstack-protector GCC feature. This
1878 feature puts, at the beginning of functions, a canary value on
1879 the stack just before the return address, and validates
1880 the value just before actually returning. Stack based buffer
1881 overflows (that need to overwrite this return address) now also
1882 overwrite the canary, which gets detected and the attack is then
1883 neutralized via a kernel panic.
1884 This feature requires gcc version 4.2 or above.
1891 bool "Xen guest support on ARM (EXPERIMENTAL)"
1892 depends on ARM && AEABI && OF
1893 depends on CPU_V7 && !CPU_V6
1894 depends on !GENERIC_ATOMIC64
1896 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1903 bool "Flattened Device Tree support"
1906 select OF_EARLY_FLATTREE
1908 Include support for flattened device tree machine descriptions.
1911 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1914 This is the traditional way of passing data to the kernel at boot
1915 time. If you are solely relying on the flattened device tree (or
1916 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1917 to remove ATAGS support from your kernel binary. If unsure,
1920 config DEPRECATED_PARAM_STRUCT
1921 bool "Provide old way to pass kernel parameters"
1924 This was deprecated in 2001 and announced to live on for 5 years.
1925 Some old boot loaders still use this way.
1927 # Compressed boot loader in ROM. Yes, we really want to ask about
1928 # TEXT and BSS so we preserve their values in the config files.
1929 config ZBOOT_ROM_TEXT
1930 hex "Compressed ROM boot loader base address"
1933 The physical address at which the ROM-able zImage is to be
1934 placed in the target. Platforms which normally make use of
1935 ROM-able zImage formats normally set this to a suitable
1936 value in their defconfig file.
1938 If ZBOOT_ROM is not enabled, this has no effect.
1940 config ZBOOT_ROM_BSS
1941 hex "Compressed ROM boot loader BSS address"
1944 The base address of an area of read/write memory in the target
1945 for the ROM-able zImage which must be available while the
1946 decompressor is running. It must be large enough to hold the
1947 entire decompressed kernel plus an additional 128 KiB.
1948 Platforms which normally make use of ROM-able zImage formats
1949 normally set this to a suitable value in their defconfig file.
1951 If ZBOOT_ROM is not enabled, this has no effect.
1954 bool "Compressed boot loader in ROM/flash"
1955 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1957 Say Y here if you intend to execute your compressed kernel image
1958 (zImage) directly from ROM or flash. If unsure, say N.
1961 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1962 depends on ZBOOT_ROM && ARCH_SH7372
1963 default ZBOOT_ROM_NONE
1965 Include experimental SD/MMC loading code in the ROM-able zImage.
1966 With this enabled it is possible to write the ROM-able zImage
1967 kernel image to an MMC or SD card and boot the kernel straight
1968 from the reset vector. At reset the processor Mask ROM will load
1969 the first part of the ROM-able zImage which in turn loads the
1970 rest the kernel image to RAM.
1972 config ZBOOT_ROM_NONE
1973 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1975 Do not load image from SD or MMC
1977 config ZBOOT_ROM_MMCIF
1978 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1980 Load image from MMCIF hardware block.
1982 config ZBOOT_ROM_SH_MOBILE_SDHI
1983 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1985 Load image from SDHI hardware block
1989 config ARM_APPENDED_DTB
1990 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1991 depends on OF && !ZBOOT_ROM
1993 With this option, the boot code will look for a device tree binary
1994 (DTB) appended to zImage
1995 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1997 This is meant as a backward compatibility convenience for those
1998 systems with a bootloader that can't be upgraded to accommodate
1999 the documented boot protocol using a device tree.
2001 Beware that there is very little in terms of protection against
2002 this option being confused by leftover garbage in memory that might
2003 look like a DTB header after a reboot if no actual DTB is appended
2004 to zImage. Do not leave this option active in a production kernel
2005 if you don't intend to always append a DTB. Proper passing of the
2006 location into r2 of a bootloader provided DTB is always preferable
2009 config ARM_ATAG_DTB_COMPAT
2010 bool "Supplement the appended DTB with traditional ATAG information"
2011 depends on ARM_APPENDED_DTB
2013 Some old bootloaders can't be updated to a DTB capable one, yet
2014 they provide ATAGs with memory configuration, the ramdisk address,
2015 the kernel cmdline string, etc. Such information is dynamically
2016 provided by the bootloader and can't always be stored in a static
2017 DTB. To allow a device tree enabled kernel to be used with such
2018 bootloaders, this option allows zImage to extract the information
2019 from the ATAG list and store it at run time into the appended DTB.
2022 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2023 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2025 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2026 bool "Use bootloader kernel arguments if available"
2028 Uses the command-line options passed by the boot loader instead of
2029 the device tree bootargs property. If the boot loader doesn't provide
2030 any, the device tree bootargs property will be used.
2032 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2033 bool "Extend with bootloader kernel arguments"
2035 The command-line arguments provided by the boot loader will be
2036 appended to the the device tree bootargs property.
2041 string "Default kernel command string"
2044 On some architectures (EBSA110 and CATS), there is currently no way
2045 for the boot loader to pass arguments to the kernel. For these
2046 architectures, you should supply some command-line options at build
2047 time by entering them here. As a minimum, you should specify the
2048 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2051 prompt "Kernel command line type" if CMDLINE != ""
2052 default CMDLINE_FROM_BOOTLOADER
2055 config CMDLINE_FROM_BOOTLOADER
2056 bool "Use bootloader kernel arguments if available"
2058 Uses the command-line options passed by the boot loader. If
2059 the boot loader doesn't provide any, the default kernel command
2060 string provided in CMDLINE will be used.
2062 config CMDLINE_EXTEND
2063 bool "Extend bootloader kernel arguments"
2065 The command-line arguments provided by the boot loader will be
2066 appended to the default kernel command string.
2068 config CMDLINE_FORCE
2069 bool "Always use the default kernel command string"
2071 Always use the default kernel command string, even if the boot
2072 loader passes other arguments to the kernel.
2073 This is useful if you cannot or don't want to change the
2074 command-line options your boot loader passes to the kernel.
2078 bool "Kernel Execute-In-Place from ROM"
2079 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2081 Execute-In-Place allows the kernel to run from non-volatile storage
2082 directly addressable by the CPU, such as NOR flash. This saves RAM
2083 space since the text section of the kernel is not loaded from flash
2084 to RAM. Read-write sections, such as the data section and stack,
2085 are still copied to RAM. The XIP kernel is not compressed since
2086 it has to run directly from flash, so it will take more space to
2087 store it. The flash address used to link the kernel object files,
2088 and for storing it, is configuration dependent. Therefore, if you
2089 say Y here, you must know the proper physical address where to
2090 store the kernel image depending on your own flash memory usage.
2092 Also note that the make target becomes "make xipImage" rather than
2093 "make zImage" or "make Image". The final kernel binary to put in
2094 ROM memory will be arch/arm/boot/xipImage.
2098 config XIP_PHYS_ADDR
2099 hex "XIP Kernel Physical Location"
2100 depends on XIP_KERNEL
2101 default "0x00080000"
2103 This is the physical address in your flash memory the kernel will
2104 be linked for and stored to. This address is dependent on your
2108 bool "Kexec system call (EXPERIMENTAL)"
2109 depends on (!SMP || HOTPLUG_CPU)
2111 kexec is a system call that implements the ability to shutdown your
2112 current kernel, and to start another kernel. It is like a reboot
2113 but it is independent of the system firmware. And like a reboot
2114 you can start any kernel with it, not just Linux.
2116 It is an ongoing process to be certain the hardware in a machine
2117 is properly shutdown, so do not be surprised if this code does not
2118 initially work for you. It may help to enable device hotplugging
2122 bool "Export atags in procfs"
2123 depends on ATAGS && KEXEC
2126 Should the atags used to boot the kernel be exported in an "atags"
2127 file in procfs. Useful with kexec.
2130 bool "Build kdump crash kernel (EXPERIMENTAL)"
2132 Generate crash dump after being started by kexec. This should
2133 be normally only set in special crash dump kernels which are
2134 loaded in the main kernel with kexec-tools into a specially
2135 reserved region and then later executed after a crash by
2136 kdump/kexec. The crash dump kernel must be compiled to a
2137 memory address not used by the main kernel
2139 For more details see Documentation/kdump/kdump.txt
2141 config AUTO_ZRELADDR
2142 bool "Auto calculation of the decompressed kernel image address"
2143 depends on !ZBOOT_ROM && !ARCH_U300
2145 ZRELADDR is the physical address where the decompressed kernel
2146 image will be placed. If AUTO_ZRELADDR is selected, the address
2147 will be determined at run-time by masking the current IP with
2148 0xf8000000. This assumes the zImage being placed in the first 128MB
2149 from start of memory.
2153 menu "CPU Power Management"
2157 source "drivers/cpufreq/Kconfig"
2160 tristate "CPUfreq driver for i.MX CPUs"
2161 depends on ARCH_MXC && CPU_FREQ
2162 select CPU_FREQ_TABLE
2164 This enables the CPUfreq driver for i.MX CPUs.
2166 config CPU_FREQ_SA1100
2169 config CPU_FREQ_SA1110
2172 config CPU_FREQ_INTEGRATOR
2173 tristate "CPUfreq driver for ARM Integrator CPUs"
2174 depends on ARCH_INTEGRATOR && CPU_FREQ
2177 This enables the CPUfreq driver for ARM Integrator CPUs.
2179 For details, take a look at <file:Documentation/cpu-freq>.
2185 depends on CPU_FREQ && ARCH_PXA && PXA25x
2187 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2188 select CPU_FREQ_TABLE
2193 Internal configuration node for common cpufreq on Samsung SoC
2195 config CPU_FREQ_S3C24XX
2196 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2197 depends on ARCH_S3C24XX && CPU_FREQ
2200 This enables the CPUfreq driver for the Samsung S3C24XX family
2203 For details, take a look at <file:Documentation/cpu-freq>.
2207 config CPU_FREQ_S3C24XX_PLL
2208 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2209 depends on CPU_FREQ_S3C24XX
2211 Compile in support for changing the PLL frequency from the
2212 S3C24XX series CPUfreq driver. The PLL takes time to settle
2213 after a frequency change, so by default it is not enabled.
2215 This also means that the PLL tables for the selected CPU(s) will
2216 be built which may increase the size of the kernel image.
2218 config CPU_FREQ_S3C24XX_DEBUG
2219 bool "Debug CPUfreq Samsung driver core"
2220 depends on CPU_FREQ_S3C24XX
2222 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2224 config CPU_FREQ_S3C24XX_IODEBUG
2225 bool "Debug CPUfreq Samsung driver IO timing"
2226 depends on CPU_FREQ_S3C24XX
2228 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2230 config CPU_FREQ_S3C24XX_DEBUGFS
2231 bool "Export debugfs for CPUFreq"
2232 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2234 Export status information via debugfs.
2238 source "drivers/cpuidle/Kconfig"
2242 menu "Floating point emulation"
2244 comment "At least one emulation must be selected"
2247 bool "NWFPE math emulation"
2248 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2250 Say Y to include the NWFPE floating point emulator in the kernel.
2251 This is necessary to run most binaries. Linux does not currently
2252 support floating point hardware so you need to say Y here even if
2253 your machine has an FPA or floating point co-processor podule.
2255 You may say N here if you are going to load the Acorn FPEmulator
2256 early in the bootup.
2259 bool "Support extended precision"
2260 depends on FPE_NWFPE
2262 Say Y to include 80-bit support in the kernel floating-point
2263 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2264 Note that gcc does not generate 80-bit operations by default,
2265 so in most cases this option only enlarges the size of the
2266 floating point emulator without any good reason.
2268 You almost surely want to say N here.
2271 bool "FastFPE math emulation (EXPERIMENTAL)"
2272 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2274 Say Y here to include the FAST floating point emulator in the kernel.
2275 This is an experimental much faster emulator which now also has full
2276 precision for the mantissa. It does not support any exceptions.
2277 It is very simple, and approximately 3-6 times faster than NWFPE.
2279 It should be sufficient for most programs. It may be not suitable
2280 for scientific calculations, but you have to check this for yourself.
2281 If you do not feel you need a faster FP emulation you should better
2285 bool "VFP-format floating point maths"
2286 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2288 Say Y to include VFP support code in the kernel. This is needed
2289 if your hardware includes a VFP unit.
2291 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2292 release notes and additional status information.
2294 Say N if your target does not have VFP hardware.
2302 bool "Advanced SIMD (NEON) Extension support"
2303 depends on VFPv3 && CPU_V7
2305 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2310 menu "Userspace binary formats"
2312 source "fs/Kconfig.binfmt"
2315 tristate "RISC OS personality"
2318 Say Y here to include the kernel code necessary if you want to run
2319 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2320 experimental; if this sounds frightening, say N and sleep in peace.
2321 You can also say M here to compile this support as a module (which
2322 will be called arthur).
2326 menu "Power management options"
2328 source "kernel/power/Kconfig"
2330 config ARCH_SUSPEND_POSSIBLE
2331 depends on !ARCH_S5PC100
2332 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2333 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2336 config ARM_CPU_SUSPEND
2341 source "net/Kconfig"
2343 source "drivers/Kconfig"
2347 source "arch/arm/Kconfig.debug"
2349 source "security/Kconfig"
2351 source "crypto/Kconfig"
2353 source "lib/Kconfig"
2355 source "arch/arm/kvm/Kconfig"