4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
8 select ARCH_WANT_IPC_PARSE_VERSION
9 select BUILDTIME_EXTABLE_SORT if MMU
10 select CPU_PM if (SUSPEND || CPU_IDLE)
11 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
12 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
13 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
14 select GENERIC_IRQ_PROBE
15 select GENERIC_IRQ_SHOW
16 select GENERIC_PCI_IOMAP
17 select GENERIC_SMP_IDLE_THREAD
18 select GENERIC_IDLE_POLL_SETUP
19 select GENERIC_STRNCPY_FROM_USER
20 select GENERIC_STRNLEN_USER
21 select HARDIRQS_SW_RESEND
23 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
25 select HAVE_ARCH_SECCOMP_FILTER
26 select HAVE_ARCH_TRACEHOOK
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_DEBUG_KMEMLEAK
30 select HAVE_DMA_API_DEBUG
32 select HAVE_DMA_CONTIGUOUS if MMU
33 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
34 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
35 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
36 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
37 select HAVE_GENERIC_DMA_COHERENT
38 select HAVE_GENERIC_HARDIRQS
39 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
40 select HAVE_IDE if PCI || ISA || PCMCIA
41 select HAVE_KERNEL_GZIP
42 select HAVE_KERNEL_LZMA
43 select HAVE_KERNEL_LZO
45 select HAVE_KPROBES if !XIP_KERNEL
46 select HAVE_KRETPROBES if (HAVE_KPROBES)
48 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
49 select HAVE_PERF_EVENTS
50 select HAVE_REGS_AND_STACK_ACCESS_API
51 select HAVE_SYSCALL_TRACEPOINTS
54 select PERF_USE_VMALLOC
56 select SYS_SUPPORTS_APM_EMULATION
57 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
58 select MODULES_USE_ELF_REL
59 select CLONE_BACKWARDS
60 select OLD_SIGSUSPEND3
63 The ARM series is a line of low-power-consumption RISC chip designs
64 licensed by ARM Ltd and targeted at embedded applications and
65 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
66 manufactured, but legacy ARM-based PC hardware remains popular in
67 Europe. There is an ARM Linux project with a web page at
68 <http://www.arm.linux.org.uk/>.
70 config ARM_HAS_SG_CHAIN
73 config NEED_SG_DMA_LENGTH
76 config ARM_DMA_USE_IOMMU
78 select ARM_HAS_SG_CHAIN
79 select NEED_SG_DMA_LENGTH
83 config ARM_DMA_IOMMU_ALIGNMENT
84 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
88 DMA mapping framework by default aligns all buffers to the smallest
89 PAGE_SIZE order which is greater than or equal to the requested buffer
90 size. This works well for buffers up to a few hundreds kilobytes, but
91 for larger buffers it just a waste of address space. Drivers which has
92 relatively small addressing window (like 64Mib) might run out of
93 virtual space with just a few allocations.
95 With this parameter you can specify the maximum PAGE_SIZE order for
96 DMA IOMMU buffers. Larger buffers will be aligned only to this
97 specified order. The order is expressed as a power of two multiplied
105 config MIGHT_HAVE_PCI
108 config SYS_SUPPORTS_APM_EMULATION
116 select GENERIC_ALLOCATOR
127 The Extended Industry Standard Architecture (EISA) bus was
128 developed as an open alternative to the IBM MicroChannel bus.
130 The EISA bus provided some of the features of the IBM MicroChannel
131 bus while maintaining backward compatibility with cards made for
132 the older ISA bus. The EISA bus saw limited use between 1988 and
133 1995 when it was made obsolete by the PCI bus.
135 Say Y here if you are building a kernel for an EISA-based machine.
142 config STACKTRACE_SUPPORT
146 config HAVE_LATENCYTOP_SUPPORT
151 config LOCKDEP_SUPPORT
155 config TRACE_IRQFLAGS_SUPPORT
159 config RWSEM_GENERIC_SPINLOCK
163 config RWSEM_XCHGADD_ALGORITHM
166 config ARCH_HAS_ILOG2_U32
169 config ARCH_HAS_ILOG2_U64
172 config ARCH_HAS_CPUFREQ
175 Internal node to signify that the ARCH has CPUFREQ support
176 and that the relevant menu configurations are displayed for
179 config GENERIC_HWEIGHT
183 config GENERIC_CALIBRATE_DELAY
187 config ARCH_MAY_HAVE_PC_FDC
193 config NEED_DMA_MAP_STATE
196 config ARCH_HAS_DMA_SET_COHERENT_MASK
199 config GENERIC_ISA_DMA
205 config NEED_RET_TO_USER
213 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
214 default DRAM_BASE if REMAP_VECTORS_TO_RAM
217 The base address of exception vectors.
219 config ARM_PATCH_PHYS_VIRT
220 bool "Patch physical to virtual translations at runtime" if EMBEDDED
222 depends on !XIP_KERNEL && MMU
223 depends on !ARCH_REALVIEW || !SPARSEMEM
225 Patch phys-to-virt and virt-to-phys translation functions at
226 boot and module load time according to the position of the
227 kernel in system memory.
229 This can only be used with non-XIP MMU kernels where the base
230 of physical memory is at a 16MB boundary.
232 Only disable this option if you know that you do not require
233 this feature (eg, building a kernel for a single machine) and
234 you need to shrink the kernel to the minimal size.
236 config NEED_MACH_GPIO_H
239 Select this when mach/gpio.h is required to provide special
240 definitions for this platform. The need for mach/gpio.h should
241 be avoided when possible.
243 config NEED_MACH_IO_H
246 Select this when mach/io.h is required to provide special
247 definitions for this platform. The need for mach/io.h should
248 be avoided when possible.
250 config NEED_MACH_MEMORY_H
253 Select this when mach/memory.h is required to provide special
254 definitions for this platform. The need for mach/memory.h should
255 be avoided when possible.
258 hex "Physical address of main memory" if MMU
259 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
260 default DRAM_BASE if !MMU
262 Please provide the physical address corresponding to the
263 location of main memory in your system.
269 source "init/Kconfig"
271 source "kernel/Kconfig.freezer"
276 bool "MMU-based Paged Memory Management Support"
279 Select if you want MMU-based virtualised addressing space
280 support by paged memory management. If unsure, say 'Y'.
283 # The "ARM system type" choice list is ordered alphabetically by option
284 # text. Please add new entries in the option alphabetic order.
287 prompt "ARM system type"
288 default ARCH_VERSATILE if !MMU
289 default ARCH_MULTIPLATFORM if MMU
291 config ARCH_MULTIPLATFORM
292 bool "Allow multiple platforms to be selected"
294 select ARM_PATCH_PHYS_VIRT
297 select MULTI_IRQ_HANDLER
301 config ARCH_INTEGRATOR
302 bool "ARM Ltd. Integrator family"
303 select ARCH_HAS_CPUFREQ
306 select COMMON_CLK_VERSATILE
307 select GENERIC_CLOCKEVENTS
310 select MULTI_IRQ_HANDLER
311 select NEED_MACH_MEMORY_H
312 select PLAT_VERSATILE
314 select VERSATILE_FPGA_IRQ
316 Support for ARM's Integrator platform.
319 bool "ARM Ltd. RealView family"
320 select ARCH_WANT_OPTIONAL_GPIOLIB
322 select ARM_TIMER_SP804
324 select COMMON_CLK_VERSATILE
325 select GENERIC_CLOCKEVENTS
326 select GPIO_PL061 if GPIOLIB
328 select NEED_MACH_MEMORY_H
329 select PLAT_VERSATILE
330 select PLAT_VERSATILE_CLCD
332 This enables support for ARM Ltd RealView boards.
334 config ARCH_VERSATILE
335 bool "ARM Ltd. Versatile family"
336 select ARCH_WANT_OPTIONAL_GPIOLIB
338 select ARM_TIMER_SP804
341 select GENERIC_CLOCKEVENTS
342 select HAVE_MACH_CLKDEV
344 select PLAT_VERSATILE
345 select PLAT_VERSATILE_CLCD
346 select PLAT_VERSATILE_CLOCK
347 select VERSATILE_FPGA_IRQ
349 This enables support for ARM Ltd Versatile board.
353 select ARCH_REQUIRE_GPIOLIB
357 select NEED_MACH_GPIO_H
358 select NEED_MACH_IO_H if PCCARD
360 select PINCTRL_AT91 if USE_OF
362 This enables support for systems based on Atmel
363 AT91RM9200 and AT91SAM9* processors.
366 bool "Broadcom BCM2835 family"
367 select ARCH_REQUIRE_GPIOLIB
369 select ARM_ERRATA_411920
370 select ARM_TIMER_SP804
375 select GENERIC_CLOCKEVENTS
376 select MULTI_IRQ_HANDLER
378 select PINCTRL_BCM2835
382 This enables support for the Broadcom BCM2835 SoC. This SoC is
383 use in the Raspberry Pi, and Roku 2 devices.
386 bool "Cavium Networks CNS3XXX family"
389 select GENERIC_CLOCKEVENTS
390 select MIGHT_HAVE_CACHE_L2X0
391 select MIGHT_HAVE_PCI
392 select PCI_DOMAINS if PCI
394 Support for Cavium Networks CNS3XXX platform.
397 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
398 select ARCH_REQUIRE_GPIOLIB
403 select GENERIC_CLOCKEVENTS
404 select MULTI_IRQ_HANDLER
405 select NEED_MACH_MEMORY_H
408 Support for Cirrus Logic 711x/721x/731x based boards.
411 bool "Cortina Systems Gemini"
412 select ARCH_REQUIRE_GPIOLIB
413 select ARCH_USES_GETTIMEOFFSET
414 select NEED_MACH_GPIO_H
417 Support for the Cortina Systems Gemini family SoCs
421 select ARCH_REQUIRE_GPIOLIB
424 select GENERIC_CLOCKEVENTS
425 select GENERIC_IRQ_CHIP
426 select MIGHT_HAVE_CACHE_L2X0
432 Support for CSR SiRFprimaII/Marco/Polo platforms
436 select ARCH_USES_GETTIMEOFFSET
439 select NEED_MACH_IO_H
440 select NEED_MACH_MEMORY_H
443 This is an evaluation board for the StrongARM processor available
444 from Digital. It has limited hardware on-board, including an
445 Ethernet interface, two PCMCIA sockets, two serial ports and a
450 select ARCH_HAS_HOLES_MEMORYMODEL
451 select ARCH_REQUIRE_GPIOLIB
452 select ARCH_USES_GETTIMEOFFSET
457 select NEED_MACH_MEMORY_H
459 This enables support for the Cirrus EP93xx series of CPUs.
461 config ARCH_FOOTBRIDGE
465 select GENERIC_CLOCKEVENTS
467 select NEED_MACH_IO_H if !MMU
468 select NEED_MACH_MEMORY_H
470 Support for systems based on the DC21285 companion chip
471 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
474 bool "Freescale MXS-based"
475 select ARCH_REQUIRE_GPIOLIB
480 select GENERIC_CLOCKEVENTS
481 select HAVE_CLK_PREPARE
482 select MULTI_IRQ_HANDLER
488 Support for Freescale MXS-based family of processors
491 bool "Hilscher NetX based"
495 select GENERIC_CLOCKEVENTS
497 This enables support for systems based on the Hilscher NetX Soc
502 select ARCH_SUPPORTS_MSI
504 select NEED_MACH_MEMORY_H
505 select NEED_RET_TO_USER
510 Support for Intel's IOP13XX (XScale) family of processors.
515 select ARCH_REQUIRE_GPIOLIB
517 select NEED_MACH_GPIO_H
518 select NEED_RET_TO_USER
522 Support for Intel's 80219 and IOP32X (XScale) family of
528 select ARCH_REQUIRE_GPIOLIB
530 select NEED_MACH_GPIO_H
531 select NEED_RET_TO_USER
535 Support for Intel's IOP33X (XScale) family of processors.
540 select ARCH_HAS_DMA_SET_COHERENT_MASK
541 select ARCH_REQUIRE_GPIOLIB
544 select DMABOUNCE if PCI
545 select GENERIC_CLOCKEVENTS
546 select MIGHT_HAVE_PCI
547 select NEED_MACH_IO_H
548 select USB_EHCI_BIG_ENDIAN_MMIO
549 select USB_EHCI_BIG_ENDIAN_DESC
551 Support for Intel's IXP4XX (XScale) family of processors.
555 select ARCH_REQUIRE_GPIOLIB
557 select GENERIC_CLOCKEVENTS
558 select MIGHT_HAVE_PCI
561 select PLAT_ORION_LEGACY
562 select USB_ARCH_HAS_EHCI
564 Support for the Marvell Dove SoC 88AP510
567 bool "Marvell Kirkwood"
568 select ARCH_REQUIRE_GPIOLIB
570 select GENERIC_CLOCKEVENTS
574 select PINCTRL_KIRKWOOD
575 select PLAT_ORION_LEGACY
577 Support for the following Marvell Kirkwood series SoCs:
578 88F6180, 88F6192 and 88F6281.
581 bool "Marvell MV78xx0"
582 select ARCH_REQUIRE_GPIOLIB
584 select GENERIC_CLOCKEVENTS
586 select PLAT_ORION_LEGACY
588 Support for the following Marvell MV78xx0 series SoCs:
594 select ARCH_REQUIRE_GPIOLIB
596 select GENERIC_CLOCKEVENTS
598 select PLAT_ORION_LEGACY
600 Support for the following Marvell Orion 5x series SoCs:
601 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
602 Orion-2 (5281), Orion-1-90 (6183).
605 bool "Marvell PXA168/910/MMP2"
607 select ARCH_REQUIRE_GPIOLIB
609 select GENERIC_ALLOCATOR
610 select GENERIC_CLOCKEVENTS
613 select NEED_MACH_GPIO_H
618 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
621 bool "Micrel/Kendin KS8695"
622 select ARCH_REQUIRE_GPIOLIB
625 select GENERIC_CLOCKEVENTS
626 select NEED_MACH_MEMORY_H
628 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
629 System-on-Chip devices.
632 bool "Nuvoton W90X900 CPU"
633 select ARCH_REQUIRE_GPIOLIB
637 select GENERIC_CLOCKEVENTS
639 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
640 At present, the w90x900 has been renamed nuc900, regarding
641 the ARM series product line, you can login the following
642 link address to know more.
644 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
645 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
649 select ARCH_REQUIRE_GPIOLIB
654 select GENERIC_CLOCKEVENTS
657 select USB_ARCH_HAS_OHCI
660 Support for the NXP LPC32XX family of processors
664 select ARCH_HAS_CPUFREQ
665 select ARCH_REQUIRE_GPIOLIB
670 select GENERIC_CLOCKEVENTS
673 select MIGHT_HAVE_CACHE_L2X0
678 This enables support for NVIDIA Tegra based systems (Tegra APX,
679 Tegra 6xx and Tegra 2 series).
682 bool "PXA2xx/PXA3xx-based"
684 select ARCH_HAS_CPUFREQ
686 select ARCH_REQUIRE_GPIOLIB
687 select ARM_CPU_SUSPEND if PM
691 select GENERIC_CLOCKEVENTS
694 select MULTI_IRQ_HANDLER
695 select NEED_MACH_GPIO_H
699 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
703 select ARCH_REQUIRE_GPIOLIB
705 select GENERIC_CLOCKEVENTS
708 Support for Qualcomm MSM/QSD based systems. This runs on the
709 apps processor of the MSM/QSD and depends on a shared memory
710 interface to the modem processor which runs the baseband
711 stack and controls some vital subsystems
712 (clock and power control, etc).
715 bool "Renesas SH-Mobile / R-Mobile"
717 select GENERIC_CLOCKEVENTS
719 select HAVE_MACH_CLKDEV
721 select MIGHT_HAVE_CACHE_L2X0
722 select MULTI_IRQ_HANDLER
723 select NEED_MACH_MEMORY_H
726 select PM_GENERIC_DOMAINS if PM
729 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
734 select ARCH_MAY_HAVE_PC_FDC
735 select ARCH_SPARSEMEM_ENABLE
736 select ARCH_USES_GETTIMEOFFSET
739 select HAVE_PATA_PLATFORM
741 select NEED_MACH_IO_H
742 select NEED_MACH_MEMORY_H
746 On the Acorn Risc-PC, Linux can support the internal IDE disk and
747 CD-ROM interface, serial and parallel port, and the floppy drive.
751 select ARCH_HAS_CPUFREQ
753 select ARCH_REQUIRE_GPIOLIB
754 select ARCH_SPARSEMEM_ENABLE
759 select GENERIC_CLOCKEVENTS
762 select NEED_MACH_GPIO_H
763 select NEED_MACH_MEMORY_H
766 Support for StrongARM 11x0 based boards.
769 bool "Samsung S3C24XX SoCs"
770 select ARCH_HAS_CPUFREQ
771 select ARCH_USES_GETTIMEOFFSET
774 select HAVE_S3C2410_I2C if I2C
775 select HAVE_S3C2410_WATCHDOG if WATCHDOG
776 select HAVE_S3C_RTC if RTC_CLASS
777 select NEED_MACH_GPIO_H
778 select NEED_MACH_IO_H
780 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
781 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
782 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
783 Samsung SMDK2410 development board (and derivatives).
786 bool "Samsung S3C64XX"
787 select ARCH_HAS_CPUFREQ
788 select ARCH_REQUIRE_GPIOLIB
789 select ARCH_USES_GETTIMEOFFSET
794 select HAVE_S3C2410_I2C if I2C
795 select HAVE_S3C2410_WATCHDOG if WATCHDOG
797 select NEED_MACH_GPIO_H
801 select S3C_GPIO_TRACK
802 select SAMSUNG_CLKSRC
803 select SAMSUNG_GPIOLIB_4BIT
804 select SAMSUNG_IRQ_VIC_TIMER
805 select USB_ARCH_HAS_OHCI
807 Samsung S3C64XX series based systems
810 bool "Samsung S5P6440 S5P6450"
814 select GENERIC_CLOCKEVENTS
816 select HAVE_S3C2410_I2C if I2C
817 select HAVE_S3C2410_WATCHDOG if WATCHDOG
818 select HAVE_S3C_RTC if RTC_CLASS
819 select NEED_MACH_GPIO_H
821 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
825 bool "Samsung S5PC100"
826 select ARCH_USES_GETTIMEOFFSET
830 select HAVE_S3C2410_I2C if I2C
831 select HAVE_S3C2410_WATCHDOG if WATCHDOG
832 select HAVE_S3C_RTC if RTC_CLASS
833 select NEED_MACH_GPIO_H
835 Samsung S5PC100 series based systems
838 bool "Samsung S5PV210/S5PC110"
839 select ARCH_HAS_CPUFREQ
840 select ARCH_HAS_HOLES_MEMORYMODEL
841 select ARCH_SPARSEMEM_ENABLE
845 select GENERIC_CLOCKEVENTS
847 select HAVE_S3C2410_I2C if I2C
848 select HAVE_S3C2410_WATCHDOG if WATCHDOG
849 select HAVE_S3C_RTC if RTC_CLASS
850 select NEED_MACH_GPIO_H
851 select NEED_MACH_MEMORY_H
853 Samsung S5PV210/S5PC110 series based systems
856 bool "Samsung EXYNOS"
857 select ARCH_HAS_CPUFREQ
858 select ARCH_HAS_HOLES_MEMORYMODEL
859 select ARCH_SPARSEMEM_ENABLE
862 select GENERIC_CLOCKEVENTS
864 select HAVE_S3C2410_I2C if I2C
865 select HAVE_S3C2410_WATCHDOG if WATCHDOG
866 select HAVE_S3C_RTC if RTC_CLASS
867 select NEED_MACH_GPIO_H
868 select NEED_MACH_MEMORY_H
870 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
874 select ARCH_USES_GETTIMEOFFSET
878 select NEED_MACH_MEMORY_H
883 Support for the StrongARM based Digital DNARD machine, also known
884 as "Shark" (<http://www.shark-linux.de/shark.html>).
887 bool "ST-Ericsson U300 Series"
889 select ARCH_REQUIRE_GPIOLIB
891 select ARM_PATCH_PHYS_VIRT
897 select GENERIC_CLOCKEVENTS
901 Support for ST-Ericsson U300 series mobile platforms.
904 bool "ST-Ericsson U8500 Series"
906 select ARCH_HAS_CPUFREQ
907 select ARCH_REQUIRE_GPIOLIB
911 select GENERIC_CLOCKEVENTS
913 select MIGHT_HAVE_CACHE_L2X0
916 Support for ST-Ericsson's Ux500 architecture
919 bool "STMicroelectronics Nomadik"
920 select ARCH_REQUIRE_GPIOLIB
923 select CLKSRC_NOMADIK_MTU
926 select GENERIC_CLOCKEVENTS
927 select MIGHT_HAVE_CACHE_L2X0
930 select PINCTRL_STN8815
933 Support for the Nomadik platform by ST-Ericsson
937 select ARCH_HAS_CPUFREQ
938 select ARCH_REQUIRE_GPIOLIB
943 select GENERIC_CLOCKEVENTS
946 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
950 select ARCH_HAS_HOLES_MEMORYMODEL
951 select ARCH_REQUIRE_GPIOLIB
953 select GENERIC_ALLOCATOR
954 select GENERIC_CLOCKEVENTS
955 select GENERIC_IRQ_CHIP
957 select NEED_MACH_GPIO_H
961 Support for TI's DaVinci platform.
966 select ARCH_HAS_CPUFREQ
967 select ARCH_HAS_HOLES_MEMORYMODEL
969 select ARCH_REQUIRE_GPIOLIB
972 select GENERIC_CLOCKEVENTS
973 select GENERIC_IRQ_CHIP
977 select NEED_MACH_IO_H if PCCARD
978 select NEED_MACH_MEMORY_H
980 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
984 menu "Multiple platform selection"
985 depends on ARCH_MULTIPLATFORM
987 comment "CPU Core family selection"
990 bool "ARMv4 based platforms (FA526, StrongARM)"
991 depends on !ARCH_MULTI_V6_V7
992 select ARCH_MULTI_V4_V5
994 config ARCH_MULTI_V4T
995 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
996 depends on !ARCH_MULTI_V6_V7
997 select ARCH_MULTI_V4_V5
1000 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
1001 depends on !ARCH_MULTI_V6_V7
1002 select ARCH_MULTI_V4_V5
1004 config ARCH_MULTI_V4_V5
1007 config ARCH_MULTI_V6
1008 bool "ARMv6 based platforms (ARM11)"
1009 select ARCH_MULTI_V6_V7
1012 config ARCH_MULTI_V7
1013 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
1015 select ARCH_MULTI_V6_V7
1016 select ARCH_VEXPRESS
1019 config ARCH_MULTI_V6_V7
1022 config ARCH_MULTI_CPU_AUTO
1023 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
1024 select ARCH_MULTI_V5
1029 # This is sorted alphabetically by mach-* pathname. However, plat-*
1030 # Kconfigs may be included either alphabetically (according to the
1031 # plat- suffix) or along side the corresponding mach-* source.
1033 source "arch/arm/mach-mvebu/Kconfig"
1035 source "arch/arm/mach-at91/Kconfig"
1037 source "arch/arm/mach-bcm/Kconfig"
1039 source "arch/arm/mach-clps711x/Kconfig"
1041 source "arch/arm/mach-cns3xxx/Kconfig"
1043 source "arch/arm/mach-davinci/Kconfig"
1045 source "arch/arm/mach-dove/Kconfig"
1047 source "arch/arm/mach-ep93xx/Kconfig"
1049 source "arch/arm/mach-footbridge/Kconfig"
1051 source "arch/arm/mach-gemini/Kconfig"
1053 source "arch/arm/mach-highbank/Kconfig"
1055 source "arch/arm/mach-integrator/Kconfig"
1057 source "arch/arm/mach-iop32x/Kconfig"
1059 source "arch/arm/mach-iop33x/Kconfig"
1061 source "arch/arm/mach-iop13xx/Kconfig"
1063 source "arch/arm/mach-ixp4xx/Kconfig"
1065 source "arch/arm/mach-kirkwood/Kconfig"
1067 source "arch/arm/mach-ks8695/Kconfig"
1069 source "arch/arm/mach-msm/Kconfig"
1071 source "arch/arm/mach-mv78xx0/Kconfig"
1073 source "arch/arm/mach-imx/Kconfig"
1075 source "arch/arm/mach-mxs/Kconfig"
1077 source "arch/arm/mach-netx/Kconfig"
1079 source "arch/arm/mach-nomadik/Kconfig"
1081 source "arch/arm/plat-omap/Kconfig"
1083 source "arch/arm/mach-omap1/Kconfig"
1085 source "arch/arm/mach-omap2/Kconfig"
1087 source "arch/arm/mach-orion5x/Kconfig"
1089 source "arch/arm/mach-picoxcell/Kconfig"
1091 source "arch/arm/mach-pxa/Kconfig"
1092 source "arch/arm/plat-pxa/Kconfig"
1094 source "arch/arm/mach-mmp/Kconfig"
1096 source "arch/arm/mach-realview/Kconfig"
1098 source "arch/arm/mach-sa1100/Kconfig"
1100 source "arch/arm/plat-samsung/Kconfig"
1102 source "arch/arm/mach-socfpga/Kconfig"
1104 source "arch/arm/plat-spear/Kconfig"
1106 source "arch/arm/mach-s3c24xx/Kconfig"
1109 source "arch/arm/mach-s3c64xx/Kconfig"
1112 source "arch/arm/mach-s5p64x0/Kconfig"
1114 source "arch/arm/mach-s5pc100/Kconfig"
1116 source "arch/arm/mach-s5pv210/Kconfig"
1118 source "arch/arm/mach-exynos/Kconfig"
1120 source "arch/arm/mach-shmobile/Kconfig"
1122 source "arch/arm/mach-sunxi/Kconfig"
1124 source "arch/arm/mach-prima2/Kconfig"
1126 source "arch/arm/mach-tegra/Kconfig"
1128 source "arch/arm/mach-u300/Kconfig"
1130 source "arch/arm/mach-ux500/Kconfig"
1132 source "arch/arm/mach-versatile/Kconfig"
1134 source "arch/arm/mach-vexpress/Kconfig"
1135 source "arch/arm/plat-versatile/Kconfig"
1137 source "arch/arm/mach-virt/Kconfig"
1139 source "arch/arm/mach-vt8500/Kconfig"
1141 source "arch/arm/mach-w90x900/Kconfig"
1143 source "arch/arm/mach-zynq/Kconfig"
1145 # Definitions to make life easier
1151 select GENERIC_CLOCKEVENTS
1157 select GENERIC_IRQ_CHIP
1160 config PLAT_ORION_LEGACY
1167 config PLAT_VERSATILE
1170 config ARM_TIMER_SP804
1174 source arch/arm/mm/Kconfig
1178 default 16 if ARCH_EP93XX
1182 bool "Enable iWMMXt support" if !CPU_PJ4
1183 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1184 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1186 Enable support for iWMMXt context switching at run time if
1187 running on a CPU that supports it.
1191 depends on CPU_XSCALE
1194 config MULTI_IRQ_HANDLER
1197 Allow each machine to specify it's own IRQ handler at run time.
1200 source "arch/arm/Kconfig-nommu"
1203 config ARM_ERRATA_326103
1204 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1207 Executing a SWP instruction to read-only memory does not set bit 11
1208 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1209 treat the access as a read, preventing a COW from occurring and
1210 causing the faulting task to livelock.
1212 config ARM_ERRATA_411920
1213 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1214 depends on CPU_V6 || CPU_V6K
1216 Invalidation of the Instruction Cache operation can
1217 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1218 It does not affect the MPCore. This option enables the ARM Ltd.
1219 recommended workaround.
1221 config ARM_ERRATA_430973
1222 bool "ARM errata: Stale prediction on replaced interworking branch"
1225 This option enables the workaround for the 430973 Cortex-A8
1226 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1227 interworking branch is replaced with another code sequence at the
1228 same virtual address, whether due to self-modifying code or virtual
1229 to physical address re-mapping, Cortex-A8 does not recover from the
1230 stale interworking branch prediction. This results in Cortex-A8
1231 executing the new code sequence in the incorrect ARM or Thumb state.
1232 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1233 and also flushes the branch target cache at every context switch.
1234 Note that setting specific bits in the ACTLR register may not be
1235 available in non-secure mode.
1237 config ARM_ERRATA_458693
1238 bool "ARM errata: Processor deadlock when a false hazard is created"
1240 depends on !ARCH_MULTIPLATFORM
1242 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1243 erratum. For very specific sequences of memory operations, it is
1244 possible for a hazard condition intended for a cache line to instead
1245 be incorrectly associated with a different cache line. This false
1246 hazard might then cause a processor deadlock. The workaround enables
1247 the L1 caching of the NEON accesses and disables the PLD instruction
1248 in the ACTLR register. Note that setting specific bits in the ACTLR
1249 register may not be available in non-secure mode.
1251 config ARM_ERRATA_460075
1252 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1254 depends on !ARCH_MULTIPLATFORM
1256 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1257 erratum. Any asynchronous access to the L2 cache may encounter a
1258 situation in which recent store transactions to the L2 cache are lost
1259 and overwritten with stale memory contents from external memory. The
1260 workaround disables the write-allocate mode for the L2 cache via the
1261 ACTLR register. Note that setting specific bits in the ACTLR register
1262 may not be available in non-secure mode.
1264 config ARM_ERRATA_742230
1265 bool "ARM errata: DMB operation may be faulty"
1266 depends on CPU_V7 && SMP
1267 depends on !ARCH_MULTIPLATFORM
1269 This option enables the workaround for the 742230 Cortex-A9
1270 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1271 between two write operations may not ensure the correct visibility
1272 ordering of the two writes. This workaround sets a specific bit in
1273 the diagnostic register of the Cortex-A9 which causes the DMB
1274 instruction to behave as a DSB, ensuring the correct behaviour of
1277 config ARM_ERRATA_742231
1278 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1279 depends on CPU_V7 && SMP
1280 depends on !ARCH_MULTIPLATFORM
1282 This option enables the workaround for the 742231 Cortex-A9
1283 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1284 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1285 accessing some data located in the same cache line, may get corrupted
1286 data due to bad handling of the address hazard when the line gets
1287 replaced from one of the CPUs at the same time as another CPU is
1288 accessing it. This workaround sets specific bits in the diagnostic
1289 register of the Cortex-A9 which reduces the linefill issuing
1290 capabilities of the processor.
1292 config PL310_ERRATA_588369
1293 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1294 depends on CACHE_L2X0
1296 The PL310 L2 cache controller implements three types of Clean &
1297 Invalidate maintenance operations: by Physical Address
1298 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1299 They are architecturally defined to behave as the execution of a
1300 clean operation followed immediately by an invalidate operation,
1301 both performing to the same memory location. This functionality
1302 is not correctly implemented in PL310 as clean lines are not
1303 invalidated as a result of these operations.
1305 config ARM_ERRATA_720789
1306 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1309 This option enables the workaround for the 720789 Cortex-A9 (prior to
1310 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1311 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1312 As a consequence of this erratum, some TLB entries which should be
1313 invalidated are not, resulting in an incoherency in the system page
1314 tables. The workaround changes the TLB flushing routines to invalidate
1315 entries regardless of the ASID.
1317 config PL310_ERRATA_727915
1318 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1319 depends on CACHE_L2X0
1321 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1322 operation (offset 0x7FC). This operation runs in background so that
1323 PL310 can handle normal accesses while it is in progress. Under very
1324 rare circumstances, due to this erratum, write data can be lost when
1325 PL310 treats a cacheable write transaction during a Clean &
1326 Invalidate by Way operation.
1328 config ARM_ERRATA_743622
1329 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1331 depends on !ARCH_MULTIPLATFORM
1333 This option enables the workaround for the 743622 Cortex-A9
1334 (r2p*) erratum. Under very rare conditions, a faulty
1335 optimisation in the Cortex-A9 Store Buffer may lead to data
1336 corruption. This workaround sets a specific bit in the diagnostic
1337 register of the Cortex-A9 which disables the Store Buffer
1338 optimisation, preventing the defect from occurring. This has no
1339 visible impact on the overall performance or power consumption of the
1342 config ARM_ERRATA_751472
1343 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1345 depends on !ARCH_MULTIPLATFORM
1347 This option enables the workaround for the 751472 Cortex-A9 (prior
1348 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1349 completion of a following broadcasted operation if the second
1350 operation is received by a CPU before the ICIALLUIS has completed,
1351 potentially leading to corrupted entries in the cache or TLB.
1353 config PL310_ERRATA_753970
1354 bool "PL310 errata: cache sync operation may be faulty"
1355 depends on CACHE_PL310
1357 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1359 Under some condition the effect of cache sync operation on
1360 the store buffer still remains when the operation completes.
1361 This means that the store buffer is always asked to drain and
1362 this prevents it from merging any further writes. The workaround
1363 is to replace the normal offset of cache sync operation (0x730)
1364 by another offset targeting an unmapped PL310 register 0x740.
1365 This has the same effect as the cache sync operation: store buffer
1366 drain and waiting for all buffers empty.
1368 config ARM_ERRATA_754322
1369 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1372 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1373 r3p*) erratum. A speculative memory access may cause a page table walk
1374 which starts prior to an ASID switch but completes afterwards. This
1375 can populate the micro-TLB with a stale entry which may be hit with
1376 the new ASID. This workaround places two dsb instructions in the mm
1377 switching code so that no page table walks can cross the ASID switch.
1379 config ARM_ERRATA_754327
1380 bool "ARM errata: no automatic Store Buffer drain"
1381 depends on CPU_V7 && SMP
1383 This option enables the workaround for the 754327 Cortex-A9 (prior to
1384 r2p0) erratum. The Store Buffer does not have any automatic draining
1385 mechanism and therefore a livelock may occur if an external agent
1386 continuously polls a memory location waiting to observe an update.
1387 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1388 written polling loops from denying visibility of updates to memory.
1390 config ARM_ERRATA_364296
1391 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1392 depends on CPU_V6 && !SMP
1394 This options enables the workaround for the 364296 ARM1136
1395 r0p2 erratum (possible cache data corruption with
1396 hit-under-miss enabled). It sets the undocumented bit 31 in
1397 the auxiliary control register and the FI bit in the control
1398 register, thus disabling hit-under-miss without putting the
1399 processor into full low interrupt latency mode. ARM11MPCore
1402 config ARM_ERRATA_764369
1403 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1404 depends on CPU_V7 && SMP
1406 This option enables the workaround for erratum 764369
1407 affecting Cortex-A9 MPCore with two or more processors (all
1408 current revisions). Under certain timing circumstances, a data
1409 cache line maintenance operation by MVA targeting an Inner
1410 Shareable memory region may fail to proceed up to either the
1411 Point of Coherency or to the Point of Unification of the
1412 system. This workaround adds a DSB instruction before the
1413 relevant cache maintenance functions and sets a specific bit
1414 in the diagnostic control register of the SCU.
1416 config PL310_ERRATA_769419
1417 bool "PL310 errata: no automatic Store Buffer drain"
1418 depends on CACHE_L2X0
1420 On revisions of the PL310 prior to r3p2, the Store Buffer does
1421 not automatically drain. This can cause normal, non-cacheable
1422 writes to be retained when the memory system is idle, leading
1423 to suboptimal I/O performance for drivers using coherent DMA.
1424 This option adds a write barrier to the cpu_idle loop so that,
1425 on systems with an outer cache, the store buffer is drained
1428 config ARM_ERRATA_775420
1429 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1432 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1433 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1434 operation aborts with MMU exception, it might cause the processor
1435 to deadlock. This workaround puts DSB before executing ISB if
1436 an abort may occur on cache maintenance.
1438 config ARM_ERRATA_798181
1439 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1440 depends on CPU_V7 && SMP
1442 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1443 adequately shooting down all use of the old entries. This
1444 option enables the Linux kernel workaround for this erratum
1445 which sends an IPI to the CPUs that are running the same ASID
1446 as the one being invalidated.
1450 source "arch/arm/common/Kconfig"
1460 Find out whether you have ISA slots on your motherboard. ISA is the
1461 name of a bus system, i.e. the way the CPU talks to the other stuff
1462 inside your box. Other bus systems are PCI, EISA, MicroChannel
1463 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1464 newer boards don't support it. If you have ISA, say Y, otherwise N.
1466 # Select ISA DMA controller support
1471 # Select ISA DMA interface
1476 bool "PCI support" if MIGHT_HAVE_PCI
1478 Find out whether you have a PCI motherboard. PCI is the name of a
1479 bus system, i.e. the way the CPU talks to the other stuff inside
1480 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1481 VESA. If you have PCI, say Y, otherwise N.
1487 config PCI_NANOENGINE
1488 bool "BSE nanoEngine PCI support"
1489 depends on SA1100_NANOENGINE
1491 Enable PCI on the BSE nanoEngine board.
1496 # Select the host bridge type
1497 config PCI_HOST_VIA82C505
1499 depends on PCI && ARCH_SHARK
1502 config PCI_HOST_ITE8152
1504 depends on PCI && MACH_ARMCORE
1508 source "drivers/pci/Kconfig"
1510 source "drivers/pcmcia/Kconfig"
1514 menu "Kernel Features"
1519 This option should be selected by machines which have an SMP-
1522 The only effect of this option is to make the SMP-related
1523 options available to the user for configuration.
1526 bool "Symmetric Multi-Processing"
1527 depends on CPU_V6K || CPU_V7
1528 depends on GENERIC_CLOCKEVENTS
1531 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1532 select USE_GENERIC_SMP_HELPERS
1534 This enables support for systems with more than one CPU. If you have
1535 a system with only one CPU, like most personal computers, say N. If
1536 you have a system with more than one CPU, say Y.
1538 If you say N here, the kernel will run on single and multiprocessor
1539 machines, but will use only one CPU of a multiprocessor machine. If
1540 you say Y here, the kernel will run on many, but not all, single
1541 processor machines. On a single processor machine, the kernel will
1542 run faster if you say N here.
1544 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1545 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1546 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1548 If you don't know what to do here, say N.
1551 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1552 depends on SMP && !XIP_KERNEL
1555 SMP kernels contain instructions which fail on non-SMP processors.
1556 Enabling this option allows the kernel to modify itself to make
1557 these instructions safe. Disabling it allows about 1K of space
1560 If you don't know what to do here, say Y.
1562 config ARM_CPU_TOPOLOGY
1563 bool "Support cpu topology definition"
1564 depends on SMP && CPU_V7
1567 Support ARM cpu topology definition. The MPIDR register defines
1568 affinity between processors which is then used to describe the cpu
1569 topology of an ARM System.
1572 bool "Multi-core scheduler support"
1573 depends on ARM_CPU_TOPOLOGY
1575 Multi-core scheduler support improves the CPU scheduler's decision
1576 making when dealing with multi-core CPU chips at a cost of slightly
1577 increased overhead in some places. If unsure say N here.
1580 bool "SMT scheduler support"
1581 depends on ARM_CPU_TOPOLOGY
1583 Improves the CPU scheduler's decision making when dealing with
1584 MultiThreading at a cost of slightly increased overhead in some
1585 places. If unsure say N here.
1590 This option enables support for the ARM system coherency unit
1592 config HAVE_ARM_ARCH_TIMER
1593 bool "Architected timer support"
1595 select ARM_ARCH_TIMER
1597 This option enables support for the ARM architected timer
1602 select CLKSRC_OF if OF
1604 This options enables support for the ARM timer and watchdog unit
1607 prompt "Memory split"
1610 Select the desired split between kernel and user memory.
1612 If you are not absolutely sure what you are doing, leave this
1616 bool "3G/1G user/kernel split"
1618 bool "2G/2G user/kernel split"
1620 bool "1G/3G user/kernel split"
1625 default 0x40000000 if VMSPLIT_1G
1626 default 0x80000000 if VMSPLIT_2G
1630 int "Maximum number of CPUs (2-32)"
1636 bool "Support for hot-pluggable CPUs"
1637 depends on SMP && HOTPLUG
1639 Say Y here to experiment with turning CPUs off and on. CPUs
1640 can be controlled through /sys/devices/system/cpu.
1643 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1646 Say Y here if you want Linux to communicate with system firmware
1647 implementing the PSCI specification for CPU-centric power
1648 management operations described in ARM document number ARM DEN
1649 0022A ("Power State Coordination Interface System Software on
1653 bool "Use local timer interrupts"
1656 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1658 Enable support for local timers on SMP platforms, rather then the
1659 legacy IPI broadcast method. Local timers allows the system
1660 accounting to be spread across the timer interval, preventing a
1661 "thundering herd" at every timer tick.
1663 # The GPIO number here must be sorted by descending number. In case of
1664 # a multiplatform kernel, we just want the highest value required by the
1665 # selected platforms.
1668 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1669 default 512 if SOC_OMAP5
1670 default 392 if ARCH_U8500
1671 default 288 if ARCH_VT8500 || ARCH_SUNXI
1672 default 264 if MACH_H4700
1675 Maximum number of GPIOs in the system.
1677 If unsure, leave the default value.
1679 source kernel/Kconfig.preempt
1683 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1684 ARCH_S5PV210 || ARCH_EXYNOS4
1685 default AT91_TIMER_HZ if ARCH_AT91
1686 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1690 def_bool HIGH_RES_TIMERS
1692 config THUMB2_KERNEL
1693 bool "Compile the kernel in Thumb-2 mode"
1694 depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1696 select ARM_ASM_UNIFIED
1699 By enabling this option, the kernel will be compiled in
1700 Thumb-2 mode. A compiler/assembler that understand the unified
1701 ARM-Thumb syntax is needed.
1705 config THUMB2_AVOID_R_ARM_THM_JUMP11
1706 bool "Work around buggy Thumb-2 short branch relocations in gas"
1707 depends on THUMB2_KERNEL && MODULES
1710 Various binutils versions can resolve Thumb-2 branches to
1711 locally-defined, preemptible global symbols as short-range "b.n"
1712 branch instructions.
1714 This is a problem, because there's no guarantee the final
1715 destination of the symbol, or any candidate locations for a
1716 trampoline, are within range of the branch. For this reason, the
1717 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1718 relocation in modules at all, and it makes little sense to add
1721 The symptom is that the kernel fails with an "unsupported
1722 relocation" error when loading some modules.
1724 Until fixed tools are available, passing
1725 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1726 code which hits this problem, at the cost of a bit of extra runtime
1727 stack usage in some cases.
1729 The problem is described in more detail at:
1730 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1732 Only Thumb-2 kernels are affected.
1734 Unless you are sure your tools don't have this problem, say Y.
1736 config ARM_ASM_UNIFIED
1740 bool "Use the ARM EABI to compile the kernel"
1742 This option allows for the kernel to be compiled using the latest
1743 ARM ABI (aka EABI). This is only useful if you are using a user
1744 space environment that is also compiled with EABI.
1746 Since there are major incompatibilities between the legacy ABI and
1747 EABI, especially with regard to structure member alignment, this
1748 option also changes the kernel syscall calling convention to
1749 disambiguate both ABIs and allow for backward compatibility support
1750 (selected with CONFIG_OABI_COMPAT).
1752 To use this you need GCC version 4.0.0 or later.
1755 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1756 depends on AEABI && !THUMB2_KERNEL
1759 This option preserves the old syscall interface along with the
1760 new (ARM EABI) one. It also provides a compatibility layer to
1761 intercept syscalls that have structure arguments which layout
1762 in memory differs between the legacy ABI and the new ARM EABI
1763 (only for non "thumb" binaries). This option adds a tiny
1764 overhead to all syscalls and produces a slightly larger kernel.
1765 If you know you'll be using only pure EABI user space then you
1766 can say N here. If this option is not selected and you attempt
1767 to execute a legacy ABI binary then the result will be
1768 UNPREDICTABLE (in fact it can be predicted that it won't work
1769 at all). If in doubt say Y.
1771 config ARCH_HAS_HOLES_MEMORYMODEL
1774 config ARCH_SPARSEMEM_ENABLE
1777 config ARCH_SPARSEMEM_DEFAULT
1778 def_bool ARCH_SPARSEMEM_ENABLE
1780 config ARCH_SELECT_MEMORY_MODEL
1781 def_bool ARCH_SPARSEMEM_ENABLE
1783 config HAVE_ARCH_PFN_VALID
1784 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1787 bool "High Memory Support"
1790 The address space of ARM processors is only 4 Gigabytes large
1791 and it has to accommodate user address space, kernel address
1792 space as well as some memory mapped IO. That means that, if you
1793 have a large amount of physical memory and/or IO, not all of the
1794 memory can be "permanently mapped" by the kernel. The physical
1795 memory that is not permanently mapped is called "high memory".
1797 Depending on the selected kernel/user memory split, minimum
1798 vmalloc space and actual amount of RAM, you may not need this
1799 option which should result in a slightly faster kernel.
1804 bool "Allocate 2nd-level pagetables from highmem"
1807 config HW_PERF_EVENTS
1808 bool "Enable hardware performance counter support for perf events"
1809 depends on PERF_EVENTS
1812 Enable hardware performance counter support for perf events. If
1813 disabled, perf events will use software events only.
1817 config FORCE_MAX_ZONEORDER
1818 int "Maximum zone order" if ARCH_SHMOBILE
1819 range 11 64 if ARCH_SHMOBILE
1820 default "12" if SOC_AM33XX
1821 default "9" if SA1111
1824 The kernel memory allocator divides physically contiguous memory
1825 blocks into "zones", where each zone is a power of two number of
1826 pages. This option selects the largest power of two that the kernel
1827 keeps in the memory allocator. If you need to allocate very large
1828 blocks of physically contiguous memory, then you may need to
1829 increase this value.
1831 This config option is actually maximum order plus one. For example,
1832 a value of 11 means that the largest free memory block is 2^10 pages.
1834 config ALIGNMENT_TRAP
1836 depends on CPU_CP15_MMU
1837 default y if !ARCH_EBSA110
1838 select HAVE_PROC_CPU if PROC_FS
1840 ARM processors cannot fetch/store information which is not
1841 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1842 address divisible by 4. On 32-bit ARM processors, these non-aligned
1843 fetch/store instructions will be emulated in software if you say
1844 here, which has a severe performance impact. This is necessary for
1845 correct operation of some network protocols. With an IP-only
1846 configuration it is safe to say N, otherwise say Y.
1848 config UACCESS_WITH_MEMCPY
1849 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1851 default y if CPU_FEROCEON
1853 Implement faster copy_to_user and clear_user methods for CPU
1854 cores where a 8-word STM instruction give significantly higher
1855 memory write throughput than a sequence of individual 32bit stores.
1857 A possible side effect is a slight increase in scheduling latency
1858 between threads sharing the same address space if they invoke
1859 such copy operations with large buffers.
1861 However, if the CPU data cache is using a write-allocate mode,
1862 this option is unlikely to provide any performance gain.
1866 prompt "Enable seccomp to safely compute untrusted bytecode"
1868 This kernel feature is useful for number crunching applications
1869 that may need to compute untrusted bytecode during their
1870 execution. By using pipes or other transports made available to
1871 the process as file descriptors supporting the read/write
1872 syscalls, it's possible to isolate those applications in
1873 their own address space using seccomp. Once seccomp is
1874 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1875 and the task is only allowed to execute a few safe syscalls
1876 defined by each seccomp mode.
1878 config CC_STACKPROTECTOR
1879 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1881 This option turns on the -fstack-protector GCC feature. This
1882 feature puts, at the beginning of functions, a canary value on
1883 the stack just before the return address, and validates
1884 the value just before actually returning. Stack based buffer
1885 overflows (that need to overwrite this return address) now also
1886 overwrite the canary, which gets detected and the attack is then
1887 neutralized via a kernel panic.
1888 This feature requires gcc version 4.2 or above.
1895 bool "Xen guest support on ARM (EXPERIMENTAL)"
1896 depends on ARM && AEABI && OF
1897 depends on CPU_V7 && !CPU_V6
1898 depends on !GENERIC_ATOMIC64
1900 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1907 bool "Flattened Device Tree support"
1910 select OF_EARLY_FLATTREE
1912 Include support for flattened device tree machine descriptions.
1915 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1918 This is the traditional way of passing data to the kernel at boot
1919 time. If you are solely relying on the flattened device tree (or
1920 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1921 to remove ATAGS support from your kernel binary. If unsure,
1924 config DEPRECATED_PARAM_STRUCT
1925 bool "Provide old way to pass kernel parameters"
1928 This was deprecated in 2001 and announced to live on for 5 years.
1929 Some old boot loaders still use this way.
1931 # Compressed boot loader in ROM. Yes, we really want to ask about
1932 # TEXT and BSS so we preserve their values in the config files.
1933 config ZBOOT_ROM_TEXT
1934 hex "Compressed ROM boot loader base address"
1937 The physical address at which the ROM-able zImage is to be
1938 placed in the target. Platforms which normally make use of
1939 ROM-able zImage formats normally set this to a suitable
1940 value in their defconfig file.
1942 If ZBOOT_ROM is not enabled, this has no effect.
1944 config ZBOOT_ROM_BSS
1945 hex "Compressed ROM boot loader BSS address"
1948 The base address of an area of read/write memory in the target
1949 for the ROM-able zImage which must be available while the
1950 decompressor is running. It must be large enough to hold the
1951 entire decompressed kernel plus an additional 128 KiB.
1952 Platforms which normally make use of ROM-able zImage formats
1953 normally set this to a suitable value in their defconfig file.
1955 If ZBOOT_ROM is not enabled, this has no effect.
1958 bool "Compressed boot loader in ROM/flash"
1959 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1961 Say Y here if you intend to execute your compressed kernel image
1962 (zImage) directly from ROM or flash. If unsure, say N.
1965 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1966 depends on ZBOOT_ROM && ARCH_SH7372
1967 default ZBOOT_ROM_NONE
1969 Include experimental SD/MMC loading code in the ROM-able zImage.
1970 With this enabled it is possible to write the ROM-able zImage
1971 kernel image to an MMC or SD card and boot the kernel straight
1972 from the reset vector. At reset the processor Mask ROM will load
1973 the first part of the ROM-able zImage which in turn loads the
1974 rest the kernel image to RAM.
1976 config ZBOOT_ROM_NONE
1977 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1979 Do not load image from SD or MMC
1981 config ZBOOT_ROM_MMCIF
1982 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1984 Load image from MMCIF hardware block.
1986 config ZBOOT_ROM_SH_MOBILE_SDHI
1987 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1989 Load image from SDHI hardware block
1993 config ARM_APPENDED_DTB
1994 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1995 depends on OF && !ZBOOT_ROM
1997 With this option, the boot code will look for a device tree binary
1998 (DTB) appended to zImage
1999 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
2001 This is meant as a backward compatibility convenience for those
2002 systems with a bootloader that can't be upgraded to accommodate
2003 the documented boot protocol using a device tree.
2005 Beware that there is very little in terms of protection against
2006 this option being confused by leftover garbage in memory that might
2007 look like a DTB header after a reboot if no actual DTB is appended
2008 to zImage. Do not leave this option active in a production kernel
2009 if you don't intend to always append a DTB. Proper passing of the
2010 location into r2 of a bootloader provided DTB is always preferable
2013 config ARM_ATAG_DTB_COMPAT
2014 bool "Supplement the appended DTB with traditional ATAG information"
2015 depends on ARM_APPENDED_DTB
2017 Some old bootloaders can't be updated to a DTB capable one, yet
2018 they provide ATAGs with memory configuration, the ramdisk address,
2019 the kernel cmdline string, etc. Such information is dynamically
2020 provided by the bootloader and can't always be stored in a static
2021 DTB. To allow a device tree enabled kernel to be used with such
2022 bootloaders, this option allows zImage to extract the information
2023 from the ATAG list and store it at run time into the appended DTB.
2026 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2027 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2029 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2030 bool "Use bootloader kernel arguments if available"
2032 Uses the command-line options passed by the boot loader instead of
2033 the device tree bootargs property. If the boot loader doesn't provide
2034 any, the device tree bootargs property will be used.
2036 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2037 bool "Extend with bootloader kernel arguments"
2039 The command-line arguments provided by the boot loader will be
2040 appended to the the device tree bootargs property.
2045 string "Default kernel command string"
2048 On some architectures (EBSA110 and CATS), there is currently no way
2049 for the boot loader to pass arguments to the kernel. For these
2050 architectures, you should supply some command-line options at build
2051 time by entering them here. As a minimum, you should specify the
2052 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2055 prompt "Kernel command line type" if CMDLINE != ""
2056 default CMDLINE_FROM_BOOTLOADER
2059 config CMDLINE_FROM_BOOTLOADER
2060 bool "Use bootloader kernel arguments if available"
2062 Uses the command-line options passed by the boot loader. If
2063 the boot loader doesn't provide any, the default kernel command
2064 string provided in CMDLINE will be used.
2066 config CMDLINE_EXTEND
2067 bool "Extend bootloader kernel arguments"
2069 The command-line arguments provided by the boot loader will be
2070 appended to the default kernel command string.
2072 config CMDLINE_FORCE
2073 bool "Always use the default kernel command string"
2075 Always use the default kernel command string, even if the boot
2076 loader passes other arguments to the kernel.
2077 This is useful if you cannot or don't want to change the
2078 command-line options your boot loader passes to the kernel.
2082 bool "Kernel Execute-In-Place from ROM"
2083 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2085 Execute-In-Place allows the kernel to run from non-volatile storage
2086 directly addressable by the CPU, such as NOR flash. This saves RAM
2087 space since the text section of the kernel is not loaded from flash
2088 to RAM. Read-write sections, such as the data section and stack,
2089 are still copied to RAM. The XIP kernel is not compressed since
2090 it has to run directly from flash, so it will take more space to
2091 store it. The flash address used to link the kernel object files,
2092 and for storing it, is configuration dependent. Therefore, if you
2093 say Y here, you must know the proper physical address where to
2094 store the kernel image depending on your own flash memory usage.
2096 Also note that the make target becomes "make xipImage" rather than
2097 "make zImage" or "make Image". The final kernel binary to put in
2098 ROM memory will be arch/arm/boot/xipImage.
2102 config XIP_PHYS_ADDR
2103 hex "XIP Kernel Physical Location"
2104 depends on XIP_KERNEL
2105 default "0x00080000"
2107 This is the physical address in your flash memory the kernel will
2108 be linked for and stored to. This address is dependent on your
2112 bool "Kexec system call (EXPERIMENTAL)"
2113 depends on (!SMP || HOTPLUG_CPU)
2115 kexec is a system call that implements the ability to shutdown your
2116 current kernel, and to start another kernel. It is like a reboot
2117 but it is independent of the system firmware. And like a reboot
2118 you can start any kernel with it, not just Linux.
2120 It is an ongoing process to be certain the hardware in a machine
2121 is properly shutdown, so do not be surprised if this code does not
2122 initially work for you. It may help to enable device hotplugging
2126 bool "Export atags in procfs"
2127 depends on ATAGS && KEXEC
2130 Should the atags used to boot the kernel be exported in an "atags"
2131 file in procfs. Useful with kexec.
2134 bool "Build kdump crash kernel (EXPERIMENTAL)"
2136 Generate crash dump after being started by kexec. This should
2137 be normally only set in special crash dump kernels which are
2138 loaded in the main kernel with kexec-tools into a specially
2139 reserved region and then later executed after a crash by
2140 kdump/kexec. The crash dump kernel must be compiled to a
2141 memory address not used by the main kernel
2143 For more details see Documentation/kdump/kdump.txt
2145 config AUTO_ZRELADDR
2146 bool "Auto calculation of the decompressed kernel image address"
2147 depends on !ZBOOT_ROM && !ARCH_U300
2149 ZRELADDR is the physical address where the decompressed kernel
2150 image will be placed. If AUTO_ZRELADDR is selected, the address
2151 will be determined at run-time by masking the current IP with
2152 0xf8000000. This assumes the zImage being placed in the first 128MB
2153 from start of memory.
2157 menu "CPU Power Management"
2160 source "drivers/cpufreq/Kconfig"
2165 Internal configuration node for common cpufreq on Samsung SoC
2167 config CPU_FREQ_S3C24XX
2168 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2169 depends on ARCH_S3C24XX && CPU_FREQ
2172 This enables the CPUfreq driver for the Samsung S3C24XX family
2175 For details, take a look at <file:Documentation/cpu-freq>.
2179 config CPU_FREQ_S3C24XX_PLL
2180 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2181 depends on CPU_FREQ_S3C24XX
2183 Compile in support for changing the PLL frequency from the
2184 S3C24XX series CPUfreq driver. The PLL takes time to settle
2185 after a frequency change, so by default it is not enabled.
2187 This also means that the PLL tables for the selected CPU(s) will
2188 be built which may increase the size of the kernel image.
2190 config CPU_FREQ_S3C24XX_DEBUG
2191 bool "Debug CPUfreq Samsung driver core"
2192 depends on CPU_FREQ_S3C24XX
2194 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2196 config CPU_FREQ_S3C24XX_IODEBUG
2197 bool "Debug CPUfreq Samsung driver IO timing"
2198 depends on CPU_FREQ_S3C24XX
2200 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2202 config CPU_FREQ_S3C24XX_DEBUGFS
2203 bool "Export debugfs for CPUFreq"
2204 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2206 Export status information via debugfs.
2210 source "drivers/cpuidle/Kconfig"
2214 menu "Floating point emulation"
2216 comment "At least one emulation must be selected"
2219 bool "NWFPE math emulation"
2220 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2222 Say Y to include the NWFPE floating point emulator in the kernel.
2223 This is necessary to run most binaries. Linux does not currently
2224 support floating point hardware so you need to say Y here even if
2225 your machine has an FPA or floating point co-processor podule.
2227 You may say N here if you are going to load the Acorn FPEmulator
2228 early in the bootup.
2231 bool "Support extended precision"
2232 depends on FPE_NWFPE
2234 Say Y to include 80-bit support in the kernel floating-point
2235 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2236 Note that gcc does not generate 80-bit operations by default,
2237 so in most cases this option only enlarges the size of the
2238 floating point emulator without any good reason.
2240 You almost surely want to say N here.
2243 bool "FastFPE math emulation (EXPERIMENTAL)"
2244 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2246 Say Y here to include the FAST floating point emulator in the kernel.
2247 This is an experimental much faster emulator which now also has full
2248 precision for the mantissa. It does not support any exceptions.
2249 It is very simple, and approximately 3-6 times faster than NWFPE.
2251 It should be sufficient for most programs. It may be not suitable
2252 for scientific calculations, but you have to check this for yourself.
2253 If you do not feel you need a faster FP emulation you should better
2257 bool "VFP-format floating point maths"
2258 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2260 Say Y to include VFP support code in the kernel. This is needed
2261 if your hardware includes a VFP unit.
2263 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2264 release notes and additional status information.
2266 Say N if your target does not have VFP hardware.
2274 bool "Advanced SIMD (NEON) Extension support"
2275 depends on VFPv3 && CPU_V7
2277 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2282 menu "Userspace binary formats"
2284 source "fs/Kconfig.binfmt"
2287 tristate "RISC OS personality"
2290 Say Y here to include the kernel code necessary if you want to run
2291 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2292 experimental; if this sounds frightening, say N and sleep in peace.
2293 You can also say M here to compile this support as a module (which
2294 will be called arthur).
2298 menu "Power management options"
2300 source "kernel/power/Kconfig"
2302 config ARCH_SUSPEND_POSSIBLE
2303 depends on !ARCH_S5PC100
2304 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2305 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2308 config ARM_CPU_SUSPEND
2313 source "net/Kconfig"
2315 source "drivers/Kconfig"
2319 source "arch/arm/Kconfig.debug"
2321 source "security/Kconfig"
2323 source "crypto/Kconfig"
2325 source "lib/Kconfig"
2327 source "arch/arm/kvm/Kconfig"