4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_WANT_IPC_PARSE_VERSION
9 select BUILDTIME_EXTABLE_SORT if MMU
10 select CLONE_BACKWARDS
11 select CPU_PM if (SUSPEND || CPU_IDLE)
12 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
13 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
14 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
15 select GENERIC_IDLE_POLL_SETUP
16 select GENERIC_IRQ_PROBE
17 select GENERIC_IRQ_SHOW
18 select GENERIC_PCI_IOMAP
19 select GENERIC_SCHED_CLOCK
20 select GENERIC_SMP_IDLE_THREAD
21 select GENERIC_STRNCPY_FROM_USER
22 select GENERIC_STRNLEN_USER
23 select HARDIRQS_SW_RESEND
24 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
26 select HAVE_ARCH_SECCOMP_FILTER
27 select HAVE_ARCH_TRACEHOOK
29 select HAVE_CONTEXT_TRACKING
30 select HAVE_C_RECORDMCOUNT
31 select HAVE_DEBUG_KMEMLEAK
32 select HAVE_DMA_API_DEBUG
34 select HAVE_DMA_CONTIGUOUS if MMU
35 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
36 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
37 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
38 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
39 select HAVE_GENERIC_DMA_COHERENT
40 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
41 select HAVE_IDE if PCI || ISA || PCMCIA
42 select HAVE_IRQ_TIME_ACCOUNTING
43 select HAVE_KERNEL_GZIP
44 select HAVE_KERNEL_LZ4
45 select HAVE_KERNEL_LZMA
46 select HAVE_KERNEL_LZO
48 select HAVE_KPROBES if !XIP_KERNEL
49 select HAVE_KRETPROBES if (HAVE_KPROBES)
51 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
52 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
53 select HAVE_PERF_EVENTS
54 select HAVE_REGS_AND_STACK_ACCESS_API
55 select HAVE_SYSCALL_TRACEPOINTS
57 select HAVE_VIRT_CPU_ACCOUNTING_GEN
58 select IRQ_FORCED_THREADING
60 select MODULES_USE_ELF_REL
62 select OLD_SIGSUSPEND3
63 select PERF_USE_VMALLOC
65 select SYS_SUPPORTS_APM_EMULATION
66 # Above selects are sorted alphabetically; please add new ones
67 # according to that. Thanks.
69 The ARM series is a line of low-power-consumption RISC chip designs
70 licensed by ARM Ltd and targeted at embedded applications and
71 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
72 manufactured, but legacy ARM-based PC hardware remains popular in
73 Europe. There is an ARM Linux project with a web page at
74 <http://www.arm.linux.org.uk/>.
76 config ARM_HAS_SG_CHAIN
79 config NEED_SG_DMA_LENGTH
82 config ARM_DMA_USE_IOMMU
84 select ARM_HAS_SG_CHAIN
85 select NEED_SG_DMA_LENGTH
89 config ARM_DMA_IOMMU_ALIGNMENT
90 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
94 DMA mapping framework by default aligns all buffers to the smallest
95 PAGE_SIZE order which is greater than or equal to the requested buffer
96 size. This works well for buffers up to a few hundreds kilobytes, but
97 for larger buffers it just a waste of address space. Drivers which has
98 relatively small addressing window (like 64Mib) might run out of
99 virtual space with just a few allocations.
101 With this parameter you can specify the maximum PAGE_SIZE order for
102 DMA IOMMU buffers. Larger buffers will be aligned only to this
103 specified order. The order is expressed as a power of two multiplied
111 config MIGHT_HAVE_PCI
114 config SYS_SUPPORTS_APM_EMULATION
119 select GENERIC_ALLOCATOR
130 The Extended Industry Standard Architecture (EISA) bus was
131 developed as an open alternative to the IBM MicroChannel bus.
133 The EISA bus provided some of the features of the IBM MicroChannel
134 bus while maintaining backward compatibility with cards made for
135 the older ISA bus. The EISA bus saw limited use between 1988 and
136 1995 when it was made obsolete by the PCI bus.
138 Say Y here if you are building a kernel for an EISA-based machine.
145 config STACKTRACE_SUPPORT
149 config HAVE_LATENCYTOP_SUPPORT
154 config LOCKDEP_SUPPORT
158 config TRACE_IRQFLAGS_SUPPORT
162 config RWSEM_GENERIC_SPINLOCK
166 config RWSEM_XCHGADD_ALGORITHM
169 config ARCH_HAS_ILOG2_U32
172 config ARCH_HAS_ILOG2_U64
175 config ARCH_HAS_CPUFREQ
178 Internal node to signify that the ARCH has CPUFREQ support
179 and that the relevant menu configurations are displayed for
182 config ARCH_HAS_BANDGAP
185 config GENERIC_HWEIGHT
189 config GENERIC_CALIBRATE_DELAY
193 config ARCH_MAY_HAVE_PC_FDC
199 config NEED_DMA_MAP_STATE
202 config ARCH_HAS_DMA_SET_COHERENT_MASK
205 config GENERIC_ISA_DMA
211 config NEED_RET_TO_USER
219 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
220 default DRAM_BASE if REMAP_VECTORS_TO_RAM
223 The base address of exception vectors. This must be two pages
226 config ARM_PATCH_PHYS_VIRT
227 bool "Patch physical to virtual translations at runtime" if EMBEDDED
229 depends on !XIP_KERNEL && MMU
230 depends on !ARCH_REALVIEW || !SPARSEMEM
232 Patch phys-to-virt and virt-to-phys translation functions at
233 boot and module load time according to the position of the
234 kernel in system memory.
236 This can only be used with non-XIP MMU kernels where the base
237 of physical memory is at a 16MB boundary.
239 Only disable this option if you know that you do not require
240 this feature (eg, building a kernel for a single machine) and
241 you need to shrink the kernel to the minimal size.
243 config NEED_MACH_GPIO_H
246 Select this when mach/gpio.h is required to provide special
247 definitions for this platform. The need for mach/gpio.h should
248 be avoided when possible.
250 config NEED_MACH_IO_H
253 Select this when mach/io.h is required to provide special
254 definitions for this platform. The need for mach/io.h should
255 be avoided when possible.
257 config NEED_MACH_MEMORY_H
260 Select this when mach/memory.h is required to provide special
261 definitions for this platform. The need for mach/memory.h should
262 be avoided when possible.
265 hex "Physical address of main memory" if MMU
266 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
267 default DRAM_BASE if !MMU
269 Please provide the physical address corresponding to the
270 location of main memory in your system.
276 source "init/Kconfig"
278 source "kernel/Kconfig.freezer"
283 bool "MMU-based Paged Memory Management Support"
286 Select if you want MMU-based virtualised addressing space
287 support by paged memory management. If unsure, say 'Y'.
290 # The "ARM system type" choice list is ordered alphabetically by option
291 # text. Please add new entries in the option alphabetic order.
294 prompt "ARM system type"
295 default ARCH_VERSATILE if !MMU
296 default ARCH_MULTIPLATFORM if MMU
298 config ARCH_MULTIPLATFORM
299 bool "Allow multiple platforms to be selected"
301 select ARM_PATCH_PHYS_VIRT
304 select MULTI_IRQ_HANDLER
308 config ARCH_INTEGRATOR
309 bool "ARM Ltd. Integrator family"
310 select ARCH_HAS_CPUFREQ
313 select COMMON_CLK_VERSATILE
314 select GENERIC_CLOCKEVENTS
317 select MULTI_IRQ_HANDLER
318 select NEED_MACH_MEMORY_H
319 select PLAT_VERSATILE
322 select VERSATILE_FPGA_IRQ
324 Support for ARM's Integrator platform.
327 bool "ARM Ltd. RealView family"
328 select ARCH_WANT_OPTIONAL_GPIOLIB
330 select ARM_TIMER_SP804
332 select COMMON_CLK_VERSATILE
333 select GENERIC_CLOCKEVENTS
334 select GPIO_PL061 if GPIOLIB
336 select NEED_MACH_MEMORY_H
337 select PLAT_VERSATILE
338 select PLAT_VERSATILE_CLCD
340 This enables support for ARM Ltd RealView boards.
342 config ARCH_VERSATILE
343 bool "ARM Ltd. Versatile family"
344 select ARCH_WANT_OPTIONAL_GPIOLIB
346 select ARM_TIMER_SP804
349 select GENERIC_CLOCKEVENTS
350 select HAVE_MACH_CLKDEV
352 select PLAT_VERSATILE
353 select PLAT_VERSATILE_CLCD
354 select PLAT_VERSATILE_CLOCK
355 select VERSATILE_FPGA_IRQ
357 This enables support for ARM Ltd Versatile board.
361 select ARCH_REQUIRE_GPIOLIB
364 select NEED_MACH_GPIO_H
365 select NEED_MACH_IO_H if PCCARD
367 select PINCTRL_AT91 if USE_OF
369 This enables support for systems based on Atmel
370 AT91RM9200 and AT91SAM9* processors.
373 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
374 select ARCH_REQUIRE_GPIOLIB
379 select GENERIC_CLOCKEVENTS
381 select MULTI_IRQ_HANDLER
384 Support for Cirrus Logic 711x/721x/731x based boards.
387 bool "Cortina Systems Gemini"
388 select ARCH_REQUIRE_GPIOLIB
391 select GENERIC_CLOCKEVENTS
392 select NEED_MACH_GPIO_H
394 Support for the Cortina Systems Gemini family SoCs
398 select ARCH_USES_GETTIMEOFFSET
401 select NEED_MACH_IO_H
402 select NEED_MACH_MEMORY_H
405 This is an evaluation board for the StrongARM processor available
406 from Digital. It has limited hardware on-board, including an
407 Ethernet interface, two PCMCIA sockets, two serial ports and a
412 select ARCH_HAS_HOLES_MEMORYMODEL
413 select ARCH_REQUIRE_GPIOLIB
414 select ARCH_USES_GETTIMEOFFSET
419 select NEED_MACH_MEMORY_H
421 This enables support for the Cirrus EP93xx series of CPUs.
423 config ARCH_FOOTBRIDGE
427 select GENERIC_CLOCKEVENTS
429 select NEED_MACH_IO_H if !MMU
430 select NEED_MACH_MEMORY_H
432 Support for systems based on the DC21285 companion chip
433 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
436 bool "Hilscher NetX based"
440 select GENERIC_CLOCKEVENTS
442 This enables support for systems based on the Hilscher NetX Soc
448 select NEED_MACH_MEMORY_H
449 select NEED_RET_TO_USER
454 Support for Intel's IOP13XX (XScale) family of processors.
459 select ARCH_REQUIRE_GPIOLIB
461 select NEED_MACH_GPIO_H
462 select NEED_RET_TO_USER
466 Support for Intel's 80219 and IOP32X (XScale) family of
472 select ARCH_REQUIRE_GPIOLIB
474 select NEED_MACH_GPIO_H
475 select NEED_RET_TO_USER
479 Support for Intel's IOP33X (XScale) family of processors.
484 select ARCH_HAS_DMA_SET_COHERENT_MASK
485 select ARCH_REQUIRE_GPIOLIB
488 select DMABOUNCE if PCI
489 select GENERIC_CLOCKEVENTS
490 select MIGHT_HAVE_PCI
491 select NEED_MACH_IO_H
492 select USB_EHCI_BIG_ENDIAN_DESC
493 select USB_EHCI_BIG_ENDIAN_MMIO
495 Support for Intel's IXP4XX (XScale) family of processors.
499 select ARCH_REQUIRE_GPIOLIB
501 select GENERIC_CLOCKEVENTS
502 select MIGHT_HAVE_PCI
506 select PLAT_ORION_LEGACY
507 select USB_ARCH_HAS_EHCI
509 Support for the Marvell Dove SoC 88AP510
512 bool "Marvell Kirkwood"
513 select ARCH_HAS_CPUFREQ
514 select ARCH_REQUIRE_GPIOLIB
516 select GENERIC_CLOCKEVENTS
521 select PINCTRL_KIRKWOOD
522 select PLAT_ORION_LEGACY
524 Support for the following Marvell Kirkwood series SoCs:
525 88F6180, 88F6192 and 88F6281.
528 bool "Marvell MV78xx0"
529 select ARCH_REQUIRE_GPIOLIB
531 select GENERIC_CLOCKEVENTS
534 select PLAT_ORION_LEGACY
536 Support for the following Marvell MV78xx0 series SoCs:
542 select ARCH_REQUIRE_GPIOLIB
544 select GENERIC_CLOCKEVENTS
547 select PLAT_ORION_LEGACY
549 Support for the following Marvell Orion 5x series SoCs:
550 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
551 Orion-2 (5281), Orion-1-90 (6183).
554 bool "Marvell PXA168/910/MMP2"
556 select ARCH_REQUIRE_GPIOLIB
558 select GENERIC_ALLOCATOR
559 select GENERIC_CLOCKEVENTS
562 select MULTI_IRQ_HANDLER
563 select NEED_MACH_GPIO_H
568 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
571 bool "Micrel/Kendin KS8695"
572 select ARCH_REQUIRE_GPIOLIB
575 select GENERIC_CLOCKEVENTS
576 select NEED_MACH_MEMORY_H
578 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
579 System-on-Chip devices.
582 bool "Nuvoton W90X900 CPU"
583 select ARCH_REQUIRE_GPIOLIB
587 select GENERIC_CLOCKEVENTS
589 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
590 At present, the w90x900 has been renamed nuc900, regarding
591 the ARM series product line, you can login the following
592 link address to know more.
594 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
595 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
599 select ARCH_REQUIRE_GPIOLIB
604 select GENERIC_CLOCKEVENTS
607 select USB_ARCH_HAS_OHCI
610 Support for the NXP LPC32XX family of processors
613 bool "PXA2xx/PXA3xx-based"
615 select ARCH_HAS_CPUFREQ
617 select ARCH_REQUIRE_GPIOLIB
618 select ARM_CPU_SUSPEND if PM
622 select GENERIC_CLOCKEVENTS
625 select MULTI_IRQ_HANDLER
626 select NEED_MACH_GPIO_H
630 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
634 select ARCH_REQUIRE_GPIOLIB
635 select CLKSRC_OF if OF
637 select GENERIC_CLOCKEVENTS
639 Support for Qualcomm MSM/QSD based systems. This runs on the
640 apps processor of the MSM/QSD and depends on a shared memory
641 interface to the modem processor which runs the baseband
642 stack and controls some vital subsystems
643 (clock and power control, etc).
646 bool "Renesas SH-Mobile / R-Mobile"
647 select ARM_PATCH_PHYS_VIRT
649 select GENERIC_CLOCKEVENTS
650 select HAVE_ARM_SCU if SMP
651 select HAVE_ARM_TWD if SMP
652 select HAVE_MACH_CLKDEV
654 select MIGHT_HAVE_CACHE_L2X0
655 select MULTI_IRQ_HANDLER
658 select PM_GENERIC_DOMAINS if PM
661 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
666 select ARCH_MAY_HAVE_PC_FDC
667 select ARCH_SPARSEMEM_ENABLE
668 select ARCH_USES_GETTIMEOFFSET
671 select HAVE_PATA_PLATFORM
673 select NEED_MACH_IO_H
674 select NEED_MACH_MEMORY_H
678 On the Acorn Risc-PC, Linux can support the internal IDE disk and
679 CD-ROM interface, serial and parallel port, and the floppy drive.
683 select ARCH_HAS_CPUFREQ
685 select ARCH_REQUIRE_GPIOLIB
686 select ARCH_SPARSEMEM_ENABLE
691 select GENERIC_CLOCKEVENTS
694 select NEED_MACH_GPIO_H
695 select NEED_MACH_MEMORY_H
698 Support for StrongARM 11x0 based boards.
701 bool "Samsung S3C24XX SoCs"
702 select ARCH_HAS_CPUFREQ
703 select ARCH_REQUIRE_GPIOLIB
705 select CLKSRC_SAMSUNG_PWM
706 select GENERIC_CLOCKEVENTS
708 select HAVE_S3C2410_I2C if I2C
709 select HAVE_S3C2410_WATCHDOG if WATCHDOG
710 select HAVE_S3C_RTC if RTC_CLASS
711 select MULTI_IRQ_HANDLER
712 select NEED_MACH_GPIO_H
713 select NEED_MACH_IO_H
716 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
717 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
718 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
719 Samsung SMDK2410 development board (and derivatives).
722 bool "Samsung S3C64XX"
723 select ARCH_HAS_CPUFREQ
724 select ARCH_REQUIRE_GPIOLIB
727 select CLKSRC_SAMSUNG_PWM
730 select GENERIC_CLOCKEVENTS
732 select HAVE_S3C2410_I2C if I2C
733 select HAVE_S3C2410_WATCHDOG if WATCHDOG
735 select NEED_MACH_GPIO_H
738 select PM_GENERIC_DOMAINS
740 select S3C_GPIO_TRACK
742 select SAMSUNG_GPIOLIB_4BIT
743 select SAMSUNG_WAKEMASK
744 select SAMSUNG_WDT_RESET
745 select USB_ARCH_HAS_OHCI
747 Samsung S3C64XX series based systems
750 bool "Samsung S5P6440 S5P6450"
752 select CLKSRC_SAMSUNG_PWM
754 select GENERIC_CLOCKEVENTS
756 select HAVE_S3C2410_I2C if I2C
757 select HAVE_S3C2410_WATCHDOG if WATCHDOG
758 select HAVE_S3C_RTC if RTC_CLASS
759 select NEED_MACH_GPIO_H
761 select SAMSUNG_WDT_RESET
763 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
767 bool "Samsung S5PC100"
768 select ARCH_REQUIRE_GPIOLIB
770 select CLKSRC_SAMSUNG_PWM
772 select GENERIC_CLOCKEVENTS
774 select HAVE_S3C2410_I2C if I2C
775 select HAVE_S3C2410_WATCHDOG if WATCHDOG
776 select HAVE_S3C_RTC if RTC_CLASS
777 select NEED_MACH_GPIO_H
779 select SAMSUNG_WDT_RESET
781 Samsung S5PC100 series based systems
784 bool "Samsung S5PV210/S5PC110"
785 select ARCH_HAS_CPUFREQ
786 select ARCH_HAS_HOLES_MEMORYMODEL
787 select ARCH_SPARSEMEM_ENABLE
789 select CLKSRC_SAMSUNG_PWM
791 select GENERIC_CLOCKEVENTS
793 select HAVE_S3C2410_I2C if I2C
794 select HAVE_S3C2410_WATCHDOG if WATCHDOG
795 select HAVE_S3C_RTC if RTC_CLASS
796 select NEED_MACH_GPIO_H
797 select NEED_MACH_MEMORY_H
800 Samsung S5PV210/S5PC110 series based systems
803 bool "Samsung EXYNOS"
804 select ARCH_HAS_CPUFREQ
805 select ARCH_HAS_HOLES_MEMORYMODEL
806 select ARCH_REQUIRE_GPIOLIB
807 select ARCH_SPARSEMEM_ENABLE
811 select GENERIC_CLOCKEVENTS
812 select HAVE_S3C2410_I2C if I2C
813 select HAVE_S3C2410_WATCHDOG if WATCHDOG
814 select HAVE_S3C_RTC if RTC_CLASS
815 select NEED_MACH_MEMORY_H
819 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
823 select ARCH_HAS_HOLES_MEMORYMODEL
824 select ARCH_REQUIRE_GPIOLIB
826 select GENERIC_ALLOCATOR
827 select GENERIC_CLOCKEVENTS
828 select GENERIC_IRQ_CHIP
834 Support for TI's DaVinci platform.
839 select ARCH_HAS_CPUFREQ
840 select ARCH_HAS_HOLES_MEMORYMODEL
842 select ARCH_REQUIRE_GPIOLIB
845 select GENERIC_CLOCKEVENTS
846 select GENERIC_IRQ_CHIP
849 select NEED_MACH_IO_H if PCCARD
850 select NEED_MACH_MEMORY_H
852 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
856 menu "Multiple platform selection"
857 depends on ARCH_MULTIPLATFORM
859 comment "CPU Core family selection"
861 config ARCH_MULTI_V4T
862 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
863 depends on !ARCH_MULTI_V6_V7
864 select ARCH_MULTI_V4_V5
865 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
866 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
867 CPU_ARM925T || CPU_ARM940T)
870 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
871 depends on !ARCH_MULTI_V6_V7
872 select ARCH_MULTI_V4_V5
873 select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \
874 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
875 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
877 config ARCH_MULTI_V4_V5
881 bool "ARMv6 based platforms (ARM11)"
882 select ARCH_MULTI_V6_V7
886 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
888 select ARCH_MULTI_V6_V7
891 config ARCH_MULTI_V6_V7
894 config ARCH_MULTI_CPU_AUTO
895 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
901 # This is sorted alphabetically by mach-* pathname. However, plat-*
902 # Kconfigs may be included either alphabetically (according to the
903 # plat- suffix) or along side the corresponding mach-* source.
905 source "arch/arm/mach-mvebu/Kconfig"
907 source "arch/arm/mach-at91/Kconfig"
909 source "arch/arm/mach-bcm/Kconfig"
911 source "arch/arm/mach-bcm2835/Kconfig"
913 source "arch/arm/mach-clps711x/Kconfig"
915 source "arch/arm/mach-cns3xxx/Kconfig"
917 source "arch/arm/mach-davinci/Kconfig"
919 source "arch/arm/mach-dove/Kconfig"
921 source "arch/arm/mach-ep93xx/Kconfig"
923 source "arch/arm/mach-footbridge/Kconfig"
925 source "arch/arm/mach-gemini/Kconfig"
927 source "arch/arm/mach-highbank/Kconfig"
929 source "arch/arm/mach-integrator/Kconfig"
931 source "arch/arm/mach-iop32x/Kconfig"
933 source "arch/arm/mach-iop33x/Kconfig"
935 source "arch/arm/mach-iop13xx/Kconfig"
937 source "arch/arm/mach-ixp4xx/Kconfig"
939 source "arch/arm/mach-keystone/Kconfig"
941 source "arch/arm/mach-kirkwood/Kconfig"
943 source "arch/arm/mach-ks8695/Kconfig"
945 source "arch/arm/mach-msm/Kconfig"
947 source "arch/arm/mach-mv78xx0/Kconfig"
949 source "arch/arm/mach-imx/Kconfig"
951 source "arch/arm/mach-mxs/Kconfig"
953 source "arch/arm/mach-netx/Kconfig"
955 source "arch/arm/mach-nomadik/Kconfig"
957 source "arch/arm/mach-nspire/Kconfig"
959 source "arch/arm/plat-omap/Kconfig"
961 source "arch/arm/mach-omap1/Kconfig"
963 source "arch/arm/mach-omap2/Kconfig"
965 source "arch/arm/mach-orion5x/Kconfig"
967 source "arch/arm/mach-picoxcell/Kconfig"
969 source "arch/arm/mach-pxa/Kconfig"
970 source "arch/arm/plat-pxa/Kconfig"
972 source "arch/arm/mach-mmp/Kconfig"
974 source "arch/arm/mach-realview/Kconfig"
976 source "arch/arm/mach-rockchip/Kconfig"
978 source "arch/arm/mach-sa1100/Kconfig"
980 source "arch/arm/plat-samsung/Kconfig"
982 source "arch/arm/mach-socfpga/Kconfig"
984 source "arch/arm/mach-spear/Kconfig"
986 source "arch/arm/mach-sti/Kconfig"
988 source "arch/arm/mach-s3c24xx/Kconfig"
990 source "arch/arm/mach-s3c64xx/Kconfig"
992 source "arch/arm/mach-s5p64x0/Kconfig"
994 source "arch/arm/mach-s5pc100/Kconfig"
996 source "arch/arm/mach-s5pv210/Kconfig"
998 source "arch/arm/mach-exynos/Kconfig"
1000 source "arch/arm/mach-shmobile/Kconfig"
1002 source "arch/arm/mach-sunxi/Kconfig"
1004 source "arch/arm/mach-prima2/Kconfig"
1006 source "arch/arm/mach-tegra/Kconfig"
1008 source "arch/arm/mach-u300/Kconfig"
1010 source "arch/arm/mach-ux500/Kconfig"
1012 source "arch/arm/mach-versatile/Kconfig"
1014 source "arch/arm/mach-vexpress/Kconfig"
1015 source "arch/arm/plat-versatile/Kconfig"
1017 source "arch/arm/mach-virt/Kconfig"
1019 source "arch/arm/mach-vt8500/Kconfig"
1021 source "arch/arm/mach-w90x900/Kconfig"
1023 source "arch/arm/mach-zynq/Kconfig"
1025 # Definitions to make life easier
1031 select GENERIC_CLOCKEVENTS
1037 select GENERIC_IRQ_CHIP
1040 config PLAT_ORION_LEGACY
1047 config PLAT_VERSATILE
1050 config ARM_TIMER_SP804
1053 select CLKSRC_OF if OF
1055 source arch/arm/mm/Kconfig
1059 default 16 if ARCH_EP93XX
1063 bool "Enable iWMMXt support" if !CPU_PJ4
1064 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1065 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1067 Enable support for iWMMXt context switching at run time if
1068 running on a CPU that supports it.
1072 depends on CPU_XSCALE
1075 config MULTI_IRQ_HANDLER
1078 Allow each machine to specify it's own IRQ handler at run time.
1081 source "arch/arm/Kconfig-nommu"
1084 config PJ4B_ERRATA_4742
1085 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1086 depends on CPU_PJ4B && MACH_ARMADA_370
1089 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1090 Event (WFE) IDLE states, a specific timing sensitivity exists between
1091 the retiring WFI/WFE instructions and the newly issued subsequent
1092 instructions. This sensitivity can result in a CPU hang scenario.
1094 The software must insert either a Data Synchronization Barrier (DSB)
1095 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1098 config ARM_ERRATA_326103
1099 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1102 Executing a SWP instruction to read-only memory does not set bit 11
1103 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1104 treat the access as a read, preventing a COW from occurring and
1105 causing the faulting task to livelock.
1107 config ARM_ERRATA_411920
1108 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1109 depends on CPU_V6 || CPU_V6K
1111 Invalidation of the Instruction Cache operation can
1112 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1113 It does not affect the MPCore. This option enables the ARM Ltd.
1114 recommended workaround.
1116 config ARM_ERRATA_430973
1117 bool "ARM errata: Stale prediction on replaced interworking branch"
1120 This option enables the workaround for the 430973 Cortex-A8
1121 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1122 interworking branch is replaced with another code sequence at the
1123 same virtual address, whether due to self-modifying code or virtual
1124 to physical address re-mapping, Cortex-A8 does not recover from the
1125 stale interworking branch prediction. This results in Cortex-A8
1126 executing the new code sequence in the incorrect ARM or Thumb state.
1127 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1128 and also flushes the branch target cache at every context switch.
1129 Note that setting specific bits in the ACTLR register may not be
1130 available in non-secure mode.
1132 config ARM_ERRATA_458693
1133 bool "ARM errata: Processor deadlock when a false hazard is created"
1135 depends on !ARCH_MULTIPLATFORM
1137 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1138 erratum. For very specific sequences of memory operations, it is
1139 possible for a hazard condition intended for a cache line to instead
1140 be incorrectly associated with a different cache line. This false
1141 hazard might then cause a processor deadlock. The workaround enables
1142 the L1 caching of the NEON accesses and disables the PLD instruction
1143 in the ACTLR register. Note that setting specific bits in the ACTLR
1144 register may not be available in non-secure mode.
1146 config ARM_ERRATA_460075
1147 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1149 depends on !ARCH_MULTIPLATFORM
1151 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1152 erratum. Any asynchronous access to the L2 cache may encounter a
1153 situation in which recent store transactions to the L2 cache are lost
1154 and overwritten with stale memory contents from external memory. The
1155 workaround disables the write-allocate mode for the L2 cache via the
1156 ACTLR register. Note that setting specific bits in the ACTLR register
1157 may not be available in non-secure mode.
1159 config ARM_ERRATA_742230
1160 bool "ARM errata: DMB operation may be faulty"
1161 depends on CPU_V7 && SMP
1162 depends on !ARCH_MULTIPLATFORM
1164 This option enables the workaround for the 742230 Cortex-A9
1165 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1166 between two write operations may not ensure the correct visibility
1167 ordering of the two writes. This workaround sets a specific bit in
1168 the diagnostic register of the Cortex-A9 which causes the DMB
1169 instruction to behave as a DSB, ensuring the correct behaviour of
1172 config ARM_ERRATA_742231
1173 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1174 depends on CPU_V7 && SMP
1175 depends on !ARCH_MULTIPLATFORM
1177 This option enables the workaround for the 742231 Cortex-A9
1178 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1179 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1180 accessing some data located in the same cache line, may get corrupted
1181 data due to bad handling of the address hazard when the line gets
1182 replaced from one of the CPUs at the same time as another CPU is
1183 accessing it. This workaround sets specific bits in the diagnostic
1184 register of the Cortex-A9 which reduces the linefill issuing
1185 capabilities of the processor.
1187 config PL310_ERRATA_588369
1188 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1189 depends on CACHE_L2X0
1191 The PL310 L2 cache controller implements three types of Clean &
1192 Invalidate maintenance operations: by Physical Address
1193 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1194 They are architecturally defined to behave as the execution of a
1195 clean operation followed immediately by an invalidate operation,
1196 both performing to the same memory location. This functionality
1197 is not correctly implemented in PL310 as clean lines are not
1198 invalidated as a result of these operations.
1200 config ARM_ERRATA_643719
1201 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1202 depends on CPU_V7 && SMP
1204 This option enables the workaround for the 643719 Cortex-A9 (prior to
1205 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1206 register returns zero when it should return one. The workaround
1207 corrects this value, ensuring cache maintenance operations which use
1208 it behave as intended and avoiding data corruption.
1210 config ARM_ERRATA_720789
1211 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1214 This option enables the workaround for the 720789 Cortex-A9 (prior to
1215 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1216 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1217 As a consequence of this erratum, some TLB entries which should be
1218 invalidated are not, resulting in an incoherency in the system page
1219 tables. The workaround changes the TLB flushing routines to invalidate
1220 entries regardless of the ASID.
1222 config PL310_ERRATA_727915
1223 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1224 depends on CACHE_L2X0
1226 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1227 operation (offset 0x7FC). This operation runs in background so that
1228 PL310 can handle normal accesses while it is in progress. Under very
1229 rare circumstances, due to this erratum, write data can be lost when
1230 PL310 treats a cacheable write transaction during a Clean &
1231 Invalidate by Way operation.
1233 config ARM_ERRATA_743622
1234 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1236 depends on !ARCH_MULTIPLATFORM
1238 This option enables the workaround for the 743622 Cortex-A9
1239 (r2p*) erratum. Under very rare conditions, a faulty
1240 optimisation in the Cortex-A9 Store Buffer may lead to data
1241 corruption. This workaround sets a specific bit in the diagnostic
1242 register of the Cortex-A9 which disables the Store Buffer
1243 optimisation, preventing the defect from occurring. This has no
1244 visible impact on the overall performance or power consumption of the
1247 config ARM_ERRATA_751472
1248 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1250 depends on !ARCH_MULTIPLATFORM
1252 This option enables the workaround for the 751472 Cortex-A9 (prior
1253 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1254 completion of a following broadcasted operation if the second
1255 operation is received by a CPU before the ICIALLUIS has completed,
1256 potentially leading to corrupted entries in the cache or TLB.
1258 config PL310_ERRATA_753970
1259 bool "PL310 errata: cache sync operation may be faulty"
1260 depends on CACHE_PL310
1262 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1264 Under some condition the effect of cache sync operation on
1265 the store buffer still remains when the operation completes.
1266 This means that the store buffer is always asked to drain and
1267 this prevents it from merging any further writes. The workaround
1268 is to replace the normal offset of cache sync operation (0x730)
1269 by another offset targeting an unmapped PL310 register 0x740.
1270 This has the same effect as the cache sync operation: store buffer
1271 drain and waiting for all buffers empty.
1273 config ARM_ERRATA_754322
1274 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1277 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1278 r3p*) erratum. A speculative memory access may cause a page table walk
1279 which starts prior to an ASID switch but completes afterwards. This
1280 can populate the micro-TLB with a stale entry which may be hit with
1281 the new ASID. This workaround places two dsb instructions in the mm
1282 switching code so that no page table walks can cross the ASID switch.
1284 config ARM_ERRATA_754327
1285 bool "ARM errata: no automatic Store Buffer drain"
1286 depends on CPU_V7 && SMP
1288 This option enables the workaround for the 754327 Cortex-A9 (prior to
1289 r2p0) erratum. The Store Buffer does not have any automatic draining
1290 mechanism and therefore a livelock may occur if an external agent
1291 continuously polls a memory location waiting to observe an update.
1292 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1293 written polling loops from denying visibility of updates to memory.
1295 config ARM_ERRATA_364296
1296 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1299 This options enables the workaround for the 364296 ARM1136
1300 r0p2 erratum (possible cache data corruption with
1301 hit-under-miss enabled). It sets the undocumented bit 31 in
1302 the auxiliary control register and the FI bit in the control
1303 register, thus disabling hit-under-miss without putting the
1304 processor into full low interrupt latency mode. ARM11MPCore
1307 config ARM_ERRATA_764369
1308 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1309 depends on CPU_V7 && SMP
1311 This option enables the workaround for erratum 764369
1312 affecting Cortex-A9 MPCore with two or more processors (all
1313 current revisions). Under certain timing circumstances, a data
1314 cache line maintenance operation by MVA targeting an Inner
1315 Shareable memory region may fail to proceed up to either the
1316 Point of Coherency or to the Point of Unification of the
1317 system. This workaround adds a DSB instruction before the
1318 relevant cache maintenance functions and sets a specific bit
1319 in the diagnostic control register of the SCU.
1321 config PL310_ERRATA_769419
1322 bool "PL310 errata: no automatic Store Buffer drain"
1323 depends on CACHE_L2X0
1325 On revisions of the PL310 prior to r3p2, the Store Buffer does
1326 not automatically drain. This can cause normal, non-cacheable
1327 writes to be retained when the memory system is idle, leading
1328 to suboptimal I/O performance for drivers using coherent DMA.
1329 This option adds a write barrier to the cpu_idle loop so that,
1330 on systems with an outer cache, the store buffer is drained
1333 config ARM_ERRATA_775420
1334 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1337 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1338 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1339 operation aborts with MMU exception, it might cause the processor
1340 to deadlock. This workaround puts DSB before executing ISB if
1341 an abort may occur on cache maintenance.
1343 config ARM_ERRATA_798181
1344 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1345 depends on CPU_V7 && SMP
1347 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1348 adequately shooting down all use of the old entries. This
1349 option enables the Linux kernel workaround for this erratum
1350 which sends an IPI to the CPUs that are running the same ASID
1351 as the one being invalidated.
1353 config ARM_ERRATA_773022
1354 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1357 This option enables the workaround for the 773022 Cortex-A15
1358 (up to r0p4) erratum. In certain rare sequences of code, the
1359 loop buffer may deliver incorrect instructions. This
1360 workaround disables the loop buffer to avoid the erratum.
1364 source "arch/arm/common/Kconfig"
1374 Find out whether you have ISA slots on your motherboard. ISA is the
1375 name of a bus system, i.e. the way the CPU talks to the other stuff
1376 inside your box. Other bus systems are PCI, EISA, MicroChannel
1377 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1378 newer boards don't support it. If you have ISA, say Y, otherwise N.
1380 # Select ISA DMA controller support
1385 # Select ISA DMA interface
1390 bool "PCI support" if MIGHT_HAVE_PCI
1392 Find out whether you have a PCI motherboard. PCI is the name of a
1393 bus system, i.e. the way the CPU talks to the other stuff inside
1394 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1395 VESA. If you have PCI, say Y, otherwise N.
1401 config PCI_NANOENGINE
1402 bool "BSE nanoEngine PCI support"
1403 depends on SA1100_NANOENGINE
1405 Enable PCI on the BSE nanoEngine board.
1410 config PCI_HOST_ITE8152
1412 depends on PCI && MACH_ARMCORE
1416 source "drivers/pci/Kconfig"
1417 source "drivers/pci/pcie/Kconfig"
1419 source "drivers/pcmcia/Kconfig"
1423 menu "Kernel Features"
1428 This option should be selected by machines which have an SMP-
1431 The only effect of this option is to make the SMP-related
1432 options available to the user for configuration.
1435 bool "Symmetric Multi-Processing"
1436 depends on CPU_V6K || CPU_V7
1437 depends on GENERIC_CLOCKEVENTS
1439 depends on MMU || ARM_MPU
1440 select USE_GENERIC_SMP_HELPERS
1442 This enables support for systems with more than one CPU. If you have
1443 a system with only one CPU, like most personal computers, say N. If
1444 you have a system with more than one CPU, say Y.
1446 If you say N here, the kernel will run on single and multiprocessor
1447 machines, but will use only one CPU of a multiprocessor machine. If
1448 you say Y here, the kernel will run on many, but not all, single
1449 processor machines. On a single processor machine, the kernel will
1450 run faster if you say N here.
1452 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1453 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1454 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1456 If you don't know what to do here, say N.
1459 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1460 depends on SMP && !XIP_KERNEL && MMU
1463 SMP kernels contain instructions which fail on non-SMP processors.
1464 Enabling this option allows the kernel to modify itself to make
1465 these instructions safe. Disabling it allows about 1K of space
1468 If you don't know what to do here, say Y.
1470 config ARM_CPU_TOPOLOGY
1471 bool "Support cpu topology definition"
1472 depends on SMP && CPU_V7
1475 Support ARM cpu topology definition. The MPIDR register defines
1476 affinity between processors which is then used to describe the cpu
1477 topology of an ARM System.
1480 bool "Multi-core scheduler support"
1481 depends on ARM_CPU_TOPOLOGY
1483 Multi-core scheduler support improves the CPU scheduler's decision
1484 making when dealing with multi-core CPU chips at a cost of slightly
1485 increased overhead in some places. If unsure say N here.
1488 bool "SMT scheduler support"
1489 depends on ARM_CPU_TOPOLOGY
1491 Improves the CPU scheduler's decision making when dealing with
1492 MultiThreading at a cost of slightly increased overhead in some
1493 places. If unsure say N here.
1498 This option enables support for the ARM system coherency unit
1500 config HAVE_ARM_ARCH_TIMER
1501 bool "Architected timer support"
1503 select ARM_ARCH_TIMER
1505 This option enables support for the ARM architected timer
1510 select CLKSRC_OF if OF
1512 This options enables support for the ARM timer and watchdog unit
1515 bool "Multi-Cluster Power Management"
1516 depends on CPU_V7 && SMP
1518 This option provides the common power management infrastructure
1519 for (multi-)cluster based systems, such as big.LITTLE based
1523 prompt "Memory split"
1526 Select the desired split between kernel and user memory.
1528 If you are not absolutely sure what you are doing, leave this
1532 bool "3G/1G user/kernel split"
1534 bool "2G/2G user/kernel split"
1536 bool "1G/3G user/kernel split"
1541 default 0x40000000 if VMSPLIT_1G
1542 default 0x80000000 if VMSPLIT_2G
1546 int "Maximum number of CPUs (2-32)"
1552 bool "Support for hot-pluggable CPUs"
1555 Say Y here to experiment with turning CPUs off and on. CPUs
1556 can be controlled through /sys/devices/system/cpu.
1559 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1562 Say Y here if you want Linux to communicate with system firmware
1563 implementing the PSCI specification for CPU-centric power
1564 management operations described in ARM document number ARM DEN
1565 0022A ("Power State Coordination Interface System Software on
1568 # The GPIO number here must be sorted by descending number. In case of
1569 # a multiplatform kernel, we just want the highest value required by the
1570 # selected platforms.
1573 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1574 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX
1575 default 392 if ARCH_U8500
1576 default 352 if ARCH_VT8500
1577 default 288 if ARCH_SUNXI
1578 default 264 if MACH_H4700
1581 Maximum number of GPIOs in the system.
1583 If unsure, leave the default value.
1585 source kernel/Kconfig.preempt
1589 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1590 ARCH_S5PV210 || ARCH_EXYNOS4
1591 default AT91_TIMER_HZ if ARCH_AT91
1592 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1596 depends on HZ_FIXED = 0
1597 prompt "Timer frequency"
1621 default HZ_FIXED if HZ_FIXED != 0
1622 default 100 if HZ_100
1623 default 200 if HZ_200
1624 default 250 if HZ_250
1625 default 300 if HZ_300
1626 default 500 if HZ_500
1630 def_bool HIGH_RES_TIMERS
1633 def_bool HIGH_RES_TIMERS
1635 config THUMB2_KERNEL
1636 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1637 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1638 default y if CPU_THUMBONLY
1640 select ARM_ASM_UNIFIED
1643 By enabling this option, the kernel will be compiled in
1644 Thumb-2 mode. A compiler/assembler that understand the unified
1645 ARM-Thumb syntax is needed.
1649 config THUMB2_AVOID_R_ARM_THM_JUMP11
1650 bool "Work around buggy Thumb-2 short branch relocations in gas"
1651 depends on THUMB2_KERNEL && MODULES
1654 Various binutils versions can resolve Thumb-2 branches to
1655 locally-defined, preemptible global symbols as short-range "b.n"
1656 branch instructions.
1658 This is a problem, because there's no guarantee the final
1659 destination of the symbol, or any candidate locations for a
1660 trampoline, are within range of the branch. For this reason, the
1661 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1662 relocation in modules at all, and it makes little sense to add
1665 The symptom is that the kernel fails with an "unsupported
1666 relocation" error when loading some modules.
1668 Until fixed tools are available, passing
1669 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1670 code which hits this problem, at the cost of a bit of extra runtime
1671 stack usage in some cases.
1673 The problem is described in more detail at:
1674 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1676 Only Thumb-2 kernels are affected.
1678 Unless you are sure your tools don't have this problem, say Y.
1680 config ARM_ASM_UNIFIED
1684 bool "Use the ARM EABI to compile the kernel"
1686 This option allows for the kernel to be compiled using the latest
1687 ARM ABI (aka EABI). This is only useful if you are using a user
1688 space environment that is also compiled with EABI.
1690 Since there are major incompatibilities between the legacy ABI and
1691 EABI, especially with regard to structure member alignment, this
1692 option also changes the kernel syscall calling convention to
1693 disambiguate both ABIs and allow for backward compatibility support
1694 (selected with CONFIG_OABI_COMPAT).
1696 To use this you need GCC version 4.0.0 or later.
1699 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1700 depends on AEABI && !THUMB2_KERNEL
1703 This option preserves the old syscall interface along with the
1704 new (ARM EABI) one. It also provides a compatibility layer to
1705 intercept syscalls that have structure arguments which layout
1706 in memory differs between the legacy ABI and the new ARM EABI
1707 (only for non "thumb" binaries). This option adds a tiny
1708 overhead to all syscalls and produces a slightly larger kernel.
1709 If you know you'll be using only pure EABI user space then you
1710 can say N here. If this option is not selected and you attempt
1711 to execute a legacy ABI binary then the result will be
1712 UNPREDICTABLE (in fact it can be predicted that it won't work
1713 at all). If in doubt say Y.
1715 config ARCH_HAS_HOLES_MEMORYMODEL
1718 config ARCH_SPARSEMEM_ENABLE
1721 config ARCH_SPARSEMEM_DEFAULT
1722 def_bool ARCH_SPARSEMEM_ENABLE
1724 config ARCH_SELECT_MEMORY_MODEL
1725 def_bool ARCH_SPARSEMEM_ENABLE
1727 config HAVE_ARCH_PFN_VALID
1728 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1731 bool "High Memory Support"
1734 The address space of ARM processors is only 4 Gigabytes large
1735 and it has to accommodate user address space, kernel address
1736 space as well as some memory mapped IO. That means that, if you
1737 have a large amount of physical memory and/or IO, not all of the
1738 memory can be "permanently mapped" by the kernel. The physical
1739 memory that is not permanently mapped is called "high memory".
1741 Depending on the selected kernel/user memory split, minimum
1742 vmalloc space and actual amount of RAM, you may not need this
1743 option which should result in a slightly faster kernel.
1748 bool "Allocate 2nd-level pagetables from highmem"
1751 config HW_PERF_EVENTS
1752 bool "Enable hardware performance counter support for perf events"
1753 depends on PERF_EVENTS
1756 Enable hardware performance counter support for perf events. If
1757 disabled, perf events will use software events only.
1759 config SYS_SUPPORTS_HUGETLBFS
1763 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1767 config ARCH_WANT_GENERAL_HUGETLB
1772 config FORCE_MAX_ZONEORDER
1773 int "Maximum zone order" if ARCH_SHMOBILE
1774 range 11 64 if ARCH_SHMOBILE
1775 default "12" if SOC_AM33XX
1776 default "9" if SA1111
1779 The kernel memory allocator divides physically contiguous memory
1780 blocks into "zones", where each zone is a power of two number of
1781 pages. This option selects the largest power of two that the kernel
1782 keeps in the memory allocator. If you need to allocate very large
1783 blocks of physically contiguous memory, then you may need to
1784 increase this value.
1786 This config option is actually maximum order plus one. For example,
1787 a value of 11 means that the largest free memory block is 2^10 pages.
1789 config ALIGNMENT_TRAP
1791 depends on CPU_CP15_MMU
1792 default y if !ARCH_EBSA110
1793 select HAVE_PROC_CPU if PROC_FS
1795 ARM processors cannot fetch/store information which is not
1796 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1797 address divisible by 4. On 32-bit ARM processors, these non-aligned
1798 fetch/store instructions will be emulated in software if you say
1799 here, which has a severe performance impact. This is necessary for
1800 correct operation of some network protocols. With an IP-only
1801 configuration it is safe to say N, otherwise say Y.
1803 config UACCESS_WITH_MEMCPY
1804 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1806 default y if CPU_FEROCEON
1808 Implement faster copy_to_user and clear_user methods for CPU
1809 cores where a 8-word STM instruction give significantly higher
1810 memory write throughput than a sequence of individual 32bit stores.
1812 A possible side effect is a slight increase in scheduling latency
1813 between threads sharing the same address space if they invoke
1814 such copy operations with large buffers.
1816 However, if the CPU data cache is using a write-allocate mode,
1817 this option is unlikely to provide any performance gain.
1821 prompt "Enable seccomp to safely compute untrusted bytecode"
1823 This kernel feature is useful for number crunching applications
1824 that may need to compute untrusted bytecode during their
1825 execution. By using pipes or other transports made available to
1826 the process as file descriptors supporting the read/write
1827 syscalls, it's possible to isolate those applications in
1828 their own address space using seccomp. Once seccomp is
1829 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1830 and the task is only allowed to execute a few safe syscalls
1831 defined by each seccomp mode.
1833 config CC_STACKPROTECTOR
1834 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1836 This option turns on the -fstack-protector GCC feature. This
1837 feature puts, at the beginning of functions, a canary value on
1838 the stack just before the return address, and validates
1839 the value just before actually returning. Stack based buffer
1840 overflows (that need to overwrite this return address) now also
1841 overwrite the canary, which gets detected and the attack is then
1842 neutralized via a kernel panic.
1843 This feature requires gcc version 4.2 or above.
1850 bool "Xen guest support on ARM (EXPERIMENTAL)"
1851 depends on ARM && AEABI && OF
1852 depends on CPU_V7 && !CPU_V6
1853 depends on !GENERIC_ATOMIC64
1856 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1863 bool "Flattened Device Tree support"
1866 select OF_EARLY_FLATTREE
1868 Include support for flattened device tree machine descriptions.
1871 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1874 This is the traditional way of passing data to the kernel at boot
1875 time. If you are solely relying on the flattened device tree (or
1876 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1877 to remove ATAGS support from your kernel binary. If unsure,
1880 config DEPRECATED_PARAM_STRUCT
1881 bool "Provide old way to pass kernel parameters"
1884 This was deprecated in 2001 and announced to live on for 5 years.
1885 Some old boot loaders still use this way.
1887 # Compressed boot loader in ROM. Yes, we really want to ask about
1888 # TEXT and BSS so we preserve their values in the config files.
1889 config ZBOOT_ROM_TEXT
1890 hex "Compressed ROM boot loader base address"
1893 The physical address at which the ROM-able zImage is to be
1894 placed in the target. Platforms which normally make use of
1895 ROM-able zImage formats normally set this to a suitable
1896 value in their defconfig file.
1898 If ZBOOT_ROM is not enabled, this has no effect.
1900 config ZBOOT_ROM_BSS
1901 hex "Compressed ROM boot loader BSS address"
1904 The base address of an area of read/write memory in the target
1905 for the ROM-able zImage which must be available while the
1906 decompressor is running. It must be large enough to hold the
1907 entire decompressed kernel plus an additional 128 KiB.
1908 Platforms which normally make use of ROM-able zImage formats
1909 normally set this to a suitable value in their defconfig file.
1911 If ZBOOT_ROM is not enabled, this has no effect.
1914 bool "Compressed boot loader in ROM/flash"
1915 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1917 Say Y here if you intend to execute your compressed kernel image
1918 (zImage) directly from ROM or flash. If unsure, say N.
1921 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1922 depends on ZBOOT_ROM && ARCH_SH7372
1923 default ZBOOT_ROM_NONE
1925 Include experimental SD/MMC loading code in the ROM-able zImage.
1926 With this enabled it is possible to write the ROM-able zImage
1927 kernel image to an MMC or SD card and boot the kernel straight
1928 from the reset vector. At reset the processor Mask ROM will load
1929 the first part of the ROM-able zImage which in turn loads the
1930 rest the kernel image to RAM.
1932 config ZBOOT_ROM_NONE
1933 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1935 Do not load image from SD or MMC
1937 config ZBOOT_ROM_MMCIF
1938 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1940 Load image from MMCIF hardware block.
1942 config ZBOOT_ROM_SH_MOBILE_SDHI
1943 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1945 Load image from SDHI hardware block
1949 config ARM_APPENDED_DTB
1950 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1951 depends on OF && !ZBOOT_ROM
1953 With this option, the boot code will look for a device tree binary
1954 (DTB) appended to zImage
1955 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1957 This is meant as a backward compatibility convenience for those
1958 systems with a bootloader that can't be upgraded to accommodate
1959 the documented boot protocol using a device tree.
1961 Beware that there is very little in terms of protection against
1962 this option being confused by leftover garbage in memory that might
1963 look like a DTB header after a reboot if no actual DTB is appended
1964 to zImage. Do not leave this option active in a production kernel
1965 if you don't intend to always append a DTB. Proper passing of the
1966 location into r2 of a bootloader provided DTB is always preferable
1969 config ARM_ATAG_DTB_COMPAT
1970 bool "Supplement the appended DTB with traditional ATAG information"
1971 depends on ARM_APPENDED_DTB
1973 Some old bootloaders can't be updated to a DTB capable one, yet
1974 they provide ATAGs with memory configuration, the ramdisk address,
1975 the kernel cmdline string, etc. Such information is dynamically
1976 provided by the bootloader and can't always be stored in a static
1977 DTB. To allow a device tree enabled kernel to be used with such
1978 bootloaders, this option allows zImage to extract the information
1979 from the ATAG list and store it at run time into the appended DTB.
1982 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1983 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1985 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1986 bool "Use bootloader kernel arguments if available"
1988 Uses the command-line options passed by the boot loader instead of
1989 the device tree bootargs property. If the boot loader doesn't provide
1990 any, the device tree bootargs property will be used.
1992 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1993 bool "Extend with bootloader kernel arguments"
1995 The command-line arguments provided by the boot loader will be
1996 appended to the the device tree bootargs property.
2001 string "Default kernel command string"
2004 On some architectures (EBSA110 and CATS), there is currently no way
2005 for the boot loader to pass arguments to the kernel. For these
2006 architectures, you should supply some command-line options at build
2007 time by entering them here. As a minimum, you should specify the
2008 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2011 prompt "Kernel command line type" if CMDLINE != ""
2012 default CMDLINE_FROM_BOOTLOADER
2015 config CMDLINE_FROM_BOOTLOADER
2016 bool "Use bootloader kernel arguments if available"
2018 Uses the command-line options passed by the boot loader. If
2019 the boot loader doesn't provide any, the default kernel command
2020 string provided in CMDLINE will be used.
2022 config CMDLINE_EXTEND
2023 bool "Extend bootloader kernel arguments"
2025 The command-line arguments provided by the boot loader will be
2026 appended to the default kernel command string.
2028 config CMDLINE_FORCE
2029 bool "Always use the default kernel command string"
2031 Always use the default kernel command string, even if the boot
2032 loader passes other arguments to the kernel.
2033 This is useful if you cannot or don't want to change the
2034 command-line options your boot loader passes to the kernel.
2038 bool "Kernel Execute-In-Place from ROM"
2039 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2041 Execute-In-Place allows the kernel to run from non-volatile storage
2042 directly addressable by the CPU, such as NOR flash. This saves RAM
2043 space since the text section of the kernel is not loaded from flash
2044 to RAM. Read-write sections, such as the data section and stack,
2045 are still copied to RAM. The XIP kernel is not compressed since
2046 it has to run directly from flash, so it will take more space to
2047 store it. The flash address used to link the kernel object files,
2048 and for storing it, is configuration dependent. Therefore, if you
2049 say Y here, you must know the proper physical address where to
2050 store the kernel image depending on your own flash memory usage.
2052 Also note that the make target becomes "make xipImage" rather than
2053 "make zImage" or "make Image". The final kernel binary to put in
2054 ROM memory will be arch/arm/boot/xipImage.
2058 config XIP_PHYS_ADDR
2059 hex "XIP Kernel Physical Location"
2060 depends on XIP_KERNEL
2061 default "0x00080000"
2063 This is the physical address in your flash memory the kernel will
2064 be linked for and stored to. This address is dependent on your
2068 bool "Kexec system call (EXPERIMENTAL)"
2069 depends on (!SMP || PM_SLEEP_SMP)
2071 kexec is a system call that implements the ability to shutdown your
2072 current kernel, and to start another kernel. It is like a reboot
2073 but it is independent of the system firmware. And like a reboot
2074 you can start any kernel with it, not just Linux.
2076 It is an ongoing process to be certain the hardware in a machine
2077 is properly shutdown, so do not be surprised if this code does not
2078 initially work for you.
2081 bool "Export atags in procfs"
2082 depends on ATAGS && KEXEC
2085 Should the atags used to boot the kernel be exported in an "atags"
2086 file in procfs. Useful with kexec.
2089 bool "Build kdump crash kernel (EXPERIMENTAL)"
2091 Generate crash dump after being started by kexec. This should
2092 be normally only set in special crash dump kernels which are
2093 loaded in the main kernel with kexec-tools into a specially
2094 reserved region and then later executed after a crash by
2095 kdump/kexec. The crash dump kernel must be compiled to a
2096 memory address not used by the main kernel
2098 For more details see Documentation/kdump/kdump.txt
2100 config AUTO_ZRELADDR
2101 bool "Auto calculation of the decompressed kernel image address"
2102 depends on !ZBOOT_ROM
2104 ZRELADDR is the physical address where the decompressed kernel
2105 image will be placed. If AUTO_ZRELADDR is selected, the address
2106 will be determined at run-time by masking the current IP with
2107 0xf8000000. This assumes the zImage being placed in the first 128MB
2108 from start of memory.
2112 menu "CPU Power Management"
2115 source "drivers/cpufreq/Kconfig"
2118 source "drivers/cpuidle/Kconfig"
2122 menu "Floating point emulation"
2124 comment "At least one emulation must be selected"
2127 bool "NWFPE math emulation"
2128 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2130 Say Y to include the NWFPE floating point emulator in the kernel.
2131 This is necessary to run most binaries. Linux does not currently
2132 support floating point hardware so you need to say Y here even if
2133 your machine has an FPA or floating point co-processor podule.
2135 You may say N here if you are going to load the Acorn FPEmulator
2136 early in the bootup.
2139 bool "Support extended precision"
2140 depends on FPE_NWFPE
2142 Say Y to include 80-bit support in the kernel floating-point
2143 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2144 Note that gcc does not generate 80-bit operations by default,
2145 so in most cases this option only enlarges the size of the
2146 floating point emulator without any good reason.
2148 You almost surely want to say N here.
2151 bool "FastFPE math emulation (EXPERIMENTAL)"
2152 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2154 Say Y here to include the FAST floating point emulator in the kernel.
2155 This is an experimental much faster emulator which now also has full
2156 precision for the mantissa. It does not support any exceptions.
2157 It is very simple, and approximately 3-6 times faster than NWFPE.
2159 It should be sufficient for most programs. It may be not suitable
2160 for scientific calculations, but you have to check this for yourself.
2161 If you do not feel you need a faster FP emulation you should better
2165 bool "VFP-format floating point maths"
2166 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2168 Say Y to include VFP support code in the kernel. This is needed
2169 if your hardware includes a VFP unit.
2171 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2172 release notes and additional status information.
2174 Say N if your target does not have VFP hardware.
2182 bool "Advanced SIMD (NEON) Extension support"
2183 depends on VFPv3 && CPU_V7
2185 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2188 config KERNEL_MODE_NEON
2189 bool "Support for NEON in kernel mode"
2190 depends on NEON && AEABI
2192 Say Y to include support for NEON in kernel mode.
2196 menu "Userspace binary formats"
2198 source "fs/Kconfig.binfmt"
2201 tristate "RISC OS personality"
2204 Say Y here to include the kernel code necessary if you want to run
2205 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2206 experimental; if this sounds frightening, say N and sleep in peace.
2207 You can also say M here to compile this support as a module (which
2208 will be called arthur).
2212 menu "Power management options"
2214 source "kernel/power/Kconfig"
2216 config ARCH_SUSPEND_POSSIBLE
2217 depends on !ARCH_S5PC100
2218 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2219 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2222 config ARM_CPU_SUSPEND
2227 source "net/Kconfig"
2229 source "drivers/Kconfig"
2233 source "arch/arm/Kconfig.debug"
2235 source "security/Kconfig"
2237 source "crypto/Kconfig"
2239 source "lib/Kconfig"
2241 source "arch/arm/kvm/Kconfig"