4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
5 select ARCH_HAS_ELF_RANDOMIZE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_MIGHT_HAVE_PC_PARPORT
10 select ARCH_SUPPORTS_ATOMIC_RMW
11 select ARCH_USE_BUILTIN_BSWAP
12 select ARCH_USE_CMPXCHG_LOCKREF
13 select ARCH_WANT_IPC_PARSE_VERSION
14 select BUILDTIME_EXTABLE_SORT if MMU
15 select CLONE_BACKWARDS
16 select CPU_PM if (SUSPEND || CPU_IDLE)
17 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
19 select EDAC_ATOMIC_SCRUB
20 select GENERIC_ALLOCATOR
21 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
22 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
23 select GENERIC_IDLE_POLL_SETUP
24 select GENERIC_IRQ_PROBE
25 select GENERIC_IRQ_SHOW
26 select GENERIC_IRQ_SHOW_LEVEL
27 select GENERIC_PCI_IOMAP
28 select GENERIC_SCHED_CLOCK
29 select GENERIC_SMP_IDLE_THREAD
30 select GENERIC_STRNCPY_FROM_USER
31 select GENERIC_STRNLEN_USER
32 select HANDLE_DOMAIN_IRQ
33 select HARDIRQS_SW_RESEND
34 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
35 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
36 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
37 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
38 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
39 select HAVE_ARCH_TRACEHOOK
40 select HAVE_ARM_SMCCC if CPU_V7
42 select HAVE_CC_STACKPROTECTOR
43 select HAVE_CONTEXT_TRACKING
44 select HAVE_C_RECORDMCOUNT
45 select HAVE_DEBUG_KMEMLEAK
46 select HAVE_DMA_API_DEBUG
48 select HAVE_DMA_CONTIGUOUS if MMU
49 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
50 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
51 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
52 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
53 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
54 select HAVE_GENERIC_DMA_COHERENT
55 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
56 select HAVE_IDE if PCI || ISA || PCMCIA
57 select HAVE_IRQ_TIME_ACCOUNTING
58 select HAVE_KERNEL_GZIP
59 select HAVE_KERNEL_LZ4
60 select HAVE_KERNEL_LZMA
61 select HAVE_KERNEL_LZO
63 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
64 select HAVE_KRETPROBES if (HAVE_KPROBES)
66 select HAVE_MOD_ARCH_SPECIFIC
67 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
68 select HAVE_OPTPROBES if !THUMB2_KERNEL
69 select HAVE_PERF_EVENTS
71 select HAVE_PERF_USER_STACK_DUMP
72 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
73 select HAVE_REGS_AND_STACK_ACCESS_API
74 select HAVE_SYSCALL_TRACEPOINTS
76 select HAVE_VIRT_CPU_ACCOUNTING_GEN
77 select IRQ_FORCED_THREADING
78 select MODULES_USE_ELF_REL
81 select OLD_SIGSUSPEND3
82 select PERF_USE_VMALLOC
84 select SYS_SUPPORTS_APM_EMULATION
85 # Above selects are sorted alphabetically; please add new ones
86 # according to that. Thanks.
88 The ARM series is a line of low-power-consumption RISC chip designs
89 licensed by ARM Ltd and targeted at embedded applications and
90 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
91 manufactured, but legacy ARM-based PC hardware remains popular in
92 Europe. There is an ARM Linux project with a web page at
93 <http://www.arm.linux.org.uk/>.
95 config ARM_HAS_SG_CHAIN
96 select ARCH_HAS_SG_CHAIN
99 config NEED_SG_DMA_LENGTH
102 config ARM_DMA_USE_IOMMU
104 select ARM_HAS_SG_CHAIN
105 select NEED_SG_DMA_LENGTH
109 config ARM_DMA_IOMMU_ALIGNMENT
110 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
114 DMA mapping framework by default aligns all buffers to the smallest
115 PAGE_SIZE order which is greater than or equal to the requested buffer
116 size. This works well for buffers up to a few hundreds kilobytes, but
117 for larger buffers it just a waste of address space. Drivers which has
118 relatively small addressing window (like 64Mib) might run out of
119 virtual space with just a few allocations.
121 With this parameter you can specify the maximum PAGE_SIZE order for
122 DMA IOMMU buffers. Larger buffers will be aligned only to this
123 specified order. The order is expressed as a power of two multiplied
128 config MIGHT_HAVE_PCI
131 config SYS_SUPPORTS_APM_EMULATION
136 select GENERIC_ALLOCATOR
147 The Extended Industry Standard Architecture (EISA) bus was
148 developed as an open alternative to the IBM MicroChannel bus.
150 The EISA bus provided some of the features of the IBM MicroChannel
151 bus while maintaining backward compatibility with cards made for
152 the older ISA bus. The EISA bus saw limited use between 1988 and
153 1995 when it was made obsolete by the PCI bus.
155 Say Y here if you are building a kernel for an EISA-based machine.
162 config STACKTRACE_SUPPORT
166 config HAVE_LATENCYTOP_SUPPORT
171 config LOCKDEP_SUPPORT
175 config TRACE_IRQFLAGS_SUPPORT
179 config RWSEM_XCHGADD_ALGORITHM
183 config ARCH_HAS_ILOG2_U32
186 config ARCH_HAS_ILOG2_U64
189 config ARCH_HAS_BANDGAP
192 config FIX_EARLYCON_MEM
195 config GENERIC_HWEIGHT
199 config GENERIC_CALIBRATE_DELAY
203 config ARCH_MAY_HAVE_PC_FDC
209 config NEED_DMA_MAP_STATE
212 config ARCH_SUPPORTS_UPROBES
215 config ARCH_HAS_DMA_SET_COHERENT_MASK
218 config GENERIC_ISA_DMA
224 config NEED_RET_TO_USER
232 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
233 default DRAM_BASE if REMAP_VECTORS_TO_RAM
236 The base address of exception vectors. This must be two pages
239 config ARM_PATCH_PHYS_VIRT
240 bool "Patch physical to virtual translations at runtime" if EMBEDDED
242 depends on !XIP_KERNEL && MMU
243 depends on !ARCH_REALVIEW || !SPARSEMEM
245 Patch phys-to-virt and virt-to-phys translation functions at
246 boot and module load time according to the position of the
247 kernel in system memory.
249 This can only be used with non-XIP MMU kernels where the base
250 of physical memory is at a 16MB boundary.
252 Only disable this option if you know that you do not require
253 this feature (eg, building a kernel for a single machine) and
254 you need to shrink the kernel to the minimal size.
256 config NEED_MACH_IO_H
259 Select this when mach/io.h is required to provide special
260 definitions for this platform. The need for mach/io.h should
261 be avoided when possible.
263 config NEED_MACH_MEMORY_H
266 Select this when mach/memory.h is required to provide special
267 definitions for this platform. The need for mach/memory.h should
268 be avoided when possible.
271 hex "Physical address of main memory" if MMU
272 depends on !ARM_PATCH_PHYS_VIRT
273 default DRAM_BASE if !MMU
274 default 0x00000000 if ARCH_EBSA110 || \
279 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
280 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
281 default 0x20000000 if ARCH_S5PV210
282 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
283 default 0xc0000000 if ARCH_SA1100
285 Please provide the physical address corresponding to the
286 location of main memory in your system.
292 config PGTABLE_LEVELS
294 default 3 if ARM_LPAE
297 source "init/Kconfig"
299 source "kernel/Kconfig.freezer"
304 bool "MMU-based Paged Memory Management Support"
307 Select if you want MMU-based virtualised addressing space
308 support by paged memory management. If unsure, say 'Y'.
311 # The "ARM system type" choice list is ordered alphabetically by option
312 # text. Please add new entries in the option alphabetic order.
315 prompt "ARM system type"
316 default ARCH_VERSATILE if !MMU
317 default ARCH_MULTIPLATFORM if MMU
319 config ARCH_MULTIPLATFORM
320 bool "Allow multiple platforms to be selected"
322 select ARCH_WANT_OPTIONAL_GPIOLIB
323 select ARM_HAS_SG_CHAIN
324 select ARM_PATCH_PHYS_VIRT
328 select GENERIC_CLOCKEVENTS
329 select MIGHT_HAVE_PCI
330 select MULTI_IRQ_HANDLER
334 config ARM_SINGLE_ARMV7M
335 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
337 select ARCH_WANT_OPTIONAL_GPIOLIB
343 select GENERIC_CLOCKEVENTS
349 bool "ARM Ltd. RealView family"
350 select ARCH_WANT_OPTIONAL_GPIOLIB
352 select ARM_TIMER_SP804
354 select COMMON_CLK_VERSATILE
355 select GENERIC_CLOCKEVENTS
356 select GPIO_PL061 if GPIOLIB
358 select NEED_MACH_MEMORY_H
359 select PLAT_VERSATILE
360 select PLAT_VERSATILE_SCHED_CLOCK
362 This enables support for ARM Ltd RealView boards.
364 config ARCH_VERSATILE
365 bool "ARM Ltd. Versatile family"
366 select ARCH_WANT_OPTIONAL_GPIOLIB
368 select ARM_TIMER_SP804
371 select GENERIC_CLOCKEVENTS
372 select HAVE_MACH_CLKDEV
374 select PLAT_VERSATILE
375 select PLAT_VERSATILE_CLOCK
376 select PLAT_VERSATILE_SCHED_CLOCK
377 select VERSATILE_FPGA_IRQ
379 This enables support for ARM Ltd Versatile board.
382 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
383 select ARCH_REQUIRE_GPIOLIB
388 select GENERIC_CLOCKEVENTS
392 Support for Cirrus Logic 711x/721x/731x based boards.
395 bool "Cortina Systems Gemini"
396 select ARCH_REQUIRE_GPIOLIB
399 select GENERIC_CLOCKEVENTS
401 Support for the Cortina Systems Gemini family SoCs
405 select ARCH_USES_GETTIMEOFFSET
408 select NEED_MACH_IO_H
409 select NEED_MACH_MEMORY_H
412 This is an evaluation board for the StrongARM processor available
413 from Digital. It has limited hardware on-board, including an
414 Ethernet interface, two PCMCIA sockets, two serial ports and a
419 select ARCH_HAS_HOLES_MEMORYMODEL
420 select ARCH_REQUIRE_GPIOLIB
422 select ARM_PATCH_PHYS_VIRT
428 select GENERIC_CLOCKEVENTS
430 This enables support for the Cirrus EP93xx series of CPUs.
432 config ARCH_FOOTBRIDGE
436 select GENERIC_CLOCKEVENTS
438 select NEED_MACH_IO_H if !MMU
439 select NEED_MACH_MEMORY_H
441 Support for systems based on the DC21285 companion chip
442 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
445 bool "Hilscher NetX based"
449 select GENERIC_CLOCKEVENTS
451 This enables support for systems based on the Hilscher NetX Soc
457 select NEED_MACH_MEMORY_H
458 select NEED_RET_TO_USER
464 Support for Intel's IOP13XX (XScale) family of processors.
469 select ARCH_REQUIRE_GPIOLIB
472 select NEED_RET_TO_USER
476 Support for Intel's 80219 and IOP32X (XScale) family of
482 select ARCH_REQUIRE_GPIOLIB
485 select NEED_RET_TO_USER
489 Support for Intel's IOP33X (XScale) family of processors.
494 select ARCH_HAS_DMA_SET_COHERENT_MASK
495 select ARCH_REQUIRE_GPIOLIB
496 select ARCH_SUPPORTS_BIG_ENDIAN
499 select DMABOUNCE if PCI
500 select GENERIC_CLOCKEVENTS
501 select MIGHT_HAVE_PCI
502 select NEED_MACH_IO_H
503 select USB_EHCI_BIG_ENDIAN_DESC
504 select USB_EHCI_BIG_ENDIAN_MMIO
506 Support for Intel's IXP4XX (XScale) family of processors.
510 select ARCH_REQUIRE_GPIOLIB
512 select GENERIC_CLOCKEVENTS
513 select MIGHT_HAVE_PCI
517 select PLAT_ORION_LEGACY
519 Support for the Marvell Dove SoC 88AP510
522 bool "Marvell MV78xx0"
523 select ARCH_REQUIRE_GPIOLIB
525 select GENERIC_CLOCKEVENTS
528 select PLAT_ORION_LEGACY
530 Support for the following Marvell MV78xx0 series SoCs:
536 select ARCH_REQUIRE_GPIOLIB
538 select GENERIC_CLOCKEVENTS
541 select PLAT_ORION_LEGACY
542 select MULTI_IRQ_HANDLER
544 Support for the following Marvell Orion 5x series SoCs:
545 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
546 Orion-2 (5281), Orion-1-90 (6183).
549 bool "Marvell PXA168/910/MMP2"
551 select ARCH_REQUIRE_GPIOLIB
553 select GENERIC_ALLOCATOR
554 select GENERIC_CLOCKEVENTS
557 select MULTI_IRQ_HANDLER
562 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
565 bool "Micrel/Kendin KS8695"
566 select ARCH_REQUIRE_GPIOLIB
569 select GENERIC_CLOCKEVENTS
570 select NEED_MACH_MEMORY_H
572 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
573 System-on-Chip devices.
576 bool "Nuvoton W90X900 CPU"
577 select ARCH_REQUIRE_GPIOLIB
581 select GENERIC_CLOCKEVENTS
583 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
584 At present, the w90x900 has been renamed nuc900, regarding
585 the ARM series product line, you can login the following
586 link address to know more.
588 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
589 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
593 select ARCH_REQUIRE_GPIOLIB
598 select GENERIC_CLOCKEVENTS
602 Support for the NXP LPC32XX family of processors
605 bool "PXA2xx/PXA3xx-based"
608 select ARCH_REQUIRE_GPIOLIB
609 select ARM_CPU_SUSPEND if PM
615 select GENERIC_CLOCKEVENTS
619 select MULTI_IRQ_HANDLER
623 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
629 select ARCH_MAY_HAVE_PC_FDC
630 select ARCH_SPARSEMEM_ENABLE
631 select ARCH_USES_GETTIMEOFFSET
635 select HAVE_PATA_PLATFORM
637 select NEED_MACH_IO_H
638 select NEED_MACH_MEMORY_H
642 On the Acorn Risc-PC, Linux can support the internal IDE disk and
643 CD-ROM interface, serial and parallel port, and the floppy drive.
648 select ARCH_REQUIRE_GPIOLIB
649 select ARCH_SPARSEMEM_ENABLE
654 select GENERIC_CLOCKEVENTS
658 select MULTI_IRQ_HANDLER
659 select NEED_MACH_MEMORY_H
662 Support for StrongARM 11x0 based boards.
665 bool "Samsung S3C24XX SoCs"
666 select ARCH_REQUIRE_GPIOLIB
669 select CLKSRC_SAMSUNG_PWM
670 select GENERIC_CLOCKEVENTS
672 select HAVE_S3C2410_I2C if I2C
673 select HAVE_S3C2410_WATCHDOG if WATCHDOG
674 select HAVE_S3C_RTC if RTC_CLASS
675 select MULTI_IRQ_HANDLER
676 select NEED_MACH_IO_H
679 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
680 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
681 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
682 Samsung SMDK2410 development board (and derivatives).
685 bool "Samsung S3C64XX"
686 select ARCH_REQUIRE_GPIOLIB
691 select CLKSRC_SAMSUNG_PWM
692 select COMMON_CLK_SAMSUNG
694 select GENERIC_CLOCKEVENTS
696 select HAVE_S3C2410_I2C if I2C
697 select HAVE_S3C2410_WATCHDOG if WATCHDOG
701 select PM_GENERIC_DOMAINS if PM
703 select S3C_GPIO_TRACK
705 select SAMSUNG_WAKEMASK
706 select SAMSUNG_WDT_RESET
708 Samsung S3C64XX series based systems
712 select ARCH_HAS_HOLES_MEMORYMODEL
713 select ARCH_REQUIRE_GPIOLIB
715 select GENERIC_ALLOCATOR
716 select GENERIC_CLOCKEVENTS
717 select GENERIC_IRQ_CHIP
722 Support for TI's DaVinci platform.
727 select ARCH_HAS_HOLES_MEMORYMODEL
729 select ARCH_REQUIRE_GPIOLIB
732 select GENERIC_CLOCKEVENTS
733 select GENERIC_IRQ_CHIP
736 select MULTI_IRQ_HANDLER
737 select NEED_MACH_IO_H if PCCARD
738 select NEED_MACH_MEMORY_H
741 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
745 menu "Multiple platform selection"
746 depends on ARCH_MULTIPLATFORM
748 comment "CPU Core family selection"
751 bool "ARMv4 based platforms (FA526)"
752 depends on !ARCH_MULTI_V6_V7
753 select ARCH_MULTI_V4_V5
756 config ARCH_MULTI_V4T
757 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
758 depends on !ARCH_MULTI_V6_V7
759 select ARCH_MULTI_V4_V5
760 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
761 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
762 CPU_ARM925T || CPU_ARM940T)
765 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
766 depends on !ARCH_MULTI_V6_V7
767 select ARCH_MULTI_V4_V5
768 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
769 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
770 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
772 config ARCH_MULTI_V4_V5
776 bool "ARMv6 based platforms (ARM11)"
777 select ARCH_MULTI_V6_V7
781 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
783 select ARCH_MULTI_V6_V7
787 config ARCH_MULTI_V6_V7
789 select MIGHT_HAVE_CACHE_L2X0
791 config ARCH_MULTI_CPU_AUTO
792 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
798 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
801 select ARM_GIC_V2M if PCI_MSI
804 select HAVE_ARM_ARCH_TIMER
807 # This is sorted alphabetically by mach-* pathname. However, plat-*
808 # Kconfigs may be included either alphabetically (according to the
809 # plat- suffix) or along side the corresponding mach-* source.
811 source "arch/arm/mach-mvebu/Kconfig"
813 source "arch/arm/mach-alpine/Kconfig"
815 source "arch/arm/mach-asm9260/Kconfig"
817 source "arch/arm/mach-at91/Kconfig"
819 source "arch/arm/mach-axxia/Kconfig"
821 source "arch/arm/mach-bcm/Kconfig"
823 source "arch/arm/mach-berlin/Kconfig"
825 source "arch/arm/mach-clps711x/Kconfig"
827 source "arch/arm/mach-cns3xxx/Kconfig"
829 source "arch/arm/mach-davinci/Kconfig"
831 source "arch/arm/mach-digicolor/Kconfig"
833 source "arch/arm/mach-dove/Kconfig"
835 source "arch/arm/mach-ep93xx/Kconfig"
837 source "arch/arm/mach-footbridge/Kconfig"
839 source "arch/arm/mach-gemini/Kconfig"
841 source "arch/arm/mach-highbank/Kconfig"
843 source "arch/arm/mach-hisi/Kconfig"
845 source "arch/arm/mach-integrator/Kconfig"
847 source "arch/arm/mach-iop32x/Kconfig"
849 source "arch/arm/mach-iop33x/Kconfig"
851 source "arch/arm/mach-iop13xx/Kconfig"
853 source "arch/arm/mach-ixp4xx/Kconfig"
855 source "arch/arm/mach-keystone/Kconfig"
857 source "arch/arm/mach-ks8695/Kconfig"
859 source "arch/arm/mach-meson/Kconfig"
861 source "arch/arm/mach-moxart/Kconfig"
863 source "arch/arm/mach-mv78xx0/Kconfig"
865 source "arch/arm/mach-imx/Kconfig"
867 source "arch/arm/mach-mediatek/Kconfig"
869 source "arch/arm/mach-mxs/Kconfig"
871 source "arch/arm/mach-netx/Kconfig"
873 source "arch/arm/mach-nomadik/Kconfig"
875 source "arch/arm/mach-nspire/Kconfig"
877 source "arch/arm/plat-omap/Kconfig"
879 source "arch/arm/mach-omap1/Kconfig"
881 source "arch/arm/mach-omap2/Kconfig"
883 source "arch/arm/mach-orion5x/Kconfig"
885 source "arch/arm/mach-picoxcell/Kconfig"
887 source "arch/arm/mach-pxa/Kconfig"
888 source "arch/arm/plat-pxa/Kconfig"
890 source "arch/arm/mach-mmp/Kconfig"
892 source "arch/arm/mach-qcom/Kconfig"
894 source "arch/arm/mach-realview/Kconfig"
896 source "arch/arm/mach-rockchip/Kconfig"
898 source "arch/arm/mach-sa1100/Kconfig"
900 source "arch/arm/mach-socfpga/Kconfig"
902 source "arch/arm/mach-spear/Kconfig"
904 source "arch/arm/mach-sti/Kconfig"
906 source "arch/arm/mach-s3c24xx/Kconfig"
908 source "arch/arm/mach-s3c64xx/Kconfig"
910 source "arch/arm/mach-s5pv210/Kconfig"
912 source "arch/arm/mach-exynos/Kconfig"
913 source "arch/arm/plat-samsung/Kconfig"
915 source "arch/arm/mach-shmobile/Kconfig"
917 source "arch/arm/mach-sunxi/Kconfig"
919 source "arch/arm/mach-prima2/Kconfig"
921 source "arch/arm/mach-tegra/Kconfig"
923 source "arch/arm/mach-u300/Kconfig"
925 source "arch/arm/mach-uniphier/Kconfig"
927 source "arch/arm/mach-ux500/Kconfig"
929 source "arch/arm/mach-versatile/Kconfig"
931 source "arch/arm/mach-vexpress/Kconfig"
932 source "arch/arm/plat-versatile/Kconfig"
934 source "arch/arm/mach-vt8500/Kconfig"
936 source "arch/arm/mach-w90x900/Kconfig"
938 source "arch/arm/mach-zx/Kconfig"
940 source "arch/arm/mach-zynq/Kconfig"
942 # ARMv7-M architecture
944 bool "Energy Micro efm32"
945 depends on ARM_SINGLE_ARMV7M
946 select ARCH_REQUIRE_GPIOLIB
948 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
952 bool "NXP LPC18xx/LPC43xx"
953 depends on ARM_SINGLE_ARMV7M
954 select ARCH_HAS_RESET_CONTROLLER
956 select CLKSRC_LPC32XX
959 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
960 high performance microcontrollers.
963 bool "STMicrolectronics STM32"
964 depends on ARM_SINGLE_ARMV7M
965 select ARCH_HAS_RESET_CONTROLLER
966 select ARMV7M_SYSTICK
968 select RESET_CONTROLLER
970 Support for STMicroelectronics STM32 processors.
972 # Definitions to make life easier
978 select GENERIC_CLOCKEVENTS
984 select GENERIC_IRQ_CHIP
987 config PLAT_ORION_LEGACY
994 config PLAT_VERSATILE
997 source "arch/arm/firmware/Kconfig"
999 source arch/arm/mm/Kconfig
1002 bool "Enable iWMMXt support"
1003 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1004 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1006 Enable support for iWMMXt context switching at run time if
1007 running on a CPU that supports it.
1009 config MULTI_IRQ_HANDLER
1012 Allow each machine to specify it's own IRQ handler at run time.
1015 source "arch/arm/Kconfig-nommu"
1018 config PJ4B_ERRATA_4742
1019 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1020 depends on CPU_PJ4B && MACH_ARMADA_370
1023 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1024 Event (WFE) IDLE states, a specific timing sensitivity exists between
1025 the retiring WFI/WFE instructions and the newly issued subsequent
1026 instructions. This sensitivity can result in a CPU hang scenario.
1028 The software must insert either a Data Synchronization Barrier (DSB)
1029 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1032 config ARM_ERRATA_326103
1033 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1036 Executing a SWP instruction to read-only memory does not set bit 11
1037 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1038 treat the access as a read, preventing a COW from occurring and
1039 causing the faulting task to livelock.
1041 config ARM_ERRATA_411920
1042 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1043 depends on CPU_V6 || CPU_V6K
1045 Invalidation of the Instruction Cache operation can
1046 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1047 It does not affect the MPCore. This option enables the ARM Ltd.
1048 recommended workaround.
1050 config ARM_ERRATA_430973
1051 bool "ARM errata: Stale prediction on replaced interworking branch"
1054 This option enables the workaround for the 430973 Cortex-A8
1055 r1p* erratum. If a code sequence containing an ARM/Thumb
1056 interworking branch is replaced with another code sequence at the
1057 same virtual address, whether due to self-modifying code or virtual
1058 to physical address re-mapping, Cortex-A8 does not recover from the
1059 stale interworking branch prediction. This results in Cortex-A8
1060 executing the new code sequence in the incorrect ARM or Thumb state.
1061 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1062 and also flushes the branch target cache at every context switch.
1063 Note that setting specific bits in the ACTLR register may not be
1064 available in non-secure mode.
1066 config ARM_ERRATA_458693
1067 bool "ARM errata: Processor deadlock when a false hazard is created"
1069 depends on !ARCH_MULTIPLATFORM
1071 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1072 erratum. For very specific sequences of memory operations, it is
1073 possible for a hazard condition intended for a cache line to instead
1074 be incorrectly associated with a different cache line. This false
1075 hazard might then cause a processor deadlock. The workaround enables
1076 the L1 caching of the NEON accesses and disables the PLD instruction
1077 in the ACTLR register. Note that setting specific bits in the ACTLR
1078 register may not be available in non-secure mode.
1080 config ARM_ERRATA_460075
1081 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1083 depends on !ARCH_MULTIPLATFORM
1085 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1086 erratum. Any asynchronous access to the L2 cache may encounter a
1087 situation in which recent store transactions to the L2 cache are lost
1088 and overwritten with stale memory contents from external memory. The
1089 workaround disables the write-allocate mode for the L2 cache via the
1090 ACTLR register. Note that setting specific bits in the ACTLR register
1091 may not be available in non-secure mode.
1093 config ARM_ERRATA_742230
1094 bool "ARM errata: DMB operation may be faulty"
1095 depends on CPU_V7 && SMP
1096 depends on !ARCH_MULTIPLATFORM
1098 This option enables the workaround for the 742230 Cortex-A9
1099 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1100 between two write operations may not ensure the correct visibility
1101 ordering of the two writes. This workaround sets a specific bit in
1102 the diagnostic register of the Cortex-A9 which causes the DMB
1103 instruction to behave as a DSB, ensuring the correct behaviour of
1106 config ARM_ERRATA_742231
1107 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1108 depends on CPU_V7 && SMP
1109 depends on !ARCH_MULTIPLATFORM
1111 This option enables the workaround for the 742231 Cortex-A9
1112 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1113 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1114 accessing some data located in the same cache line, may get corrupted
1115 data due to bad handling of the address hazard when the line gets
1116 replaced from one of the CPUs at the same time as another CPU is
1117 accessing it. This workaround sets specific bits in the diagnostic
1118 register of the Cortex-A9 which reduces the linefill issuing
1119 capabilities of the processor.
1121 config ARM_ERRATA_643719
1122 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1123 depends on CPU_V7 && SMP
1126 This option enables the workaround for the 643719 Cortex-A9 (prior to
1127 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1128 register returns zero when it should return one. The workaround
1129 corrects this value, ensuring cache maintenance operations which use
1130 it behave as intended and avoiding data corruption.
1132 config ARM_ERRATA_720789
1133 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1136 This option enables the workaround for the 720789 Cortex-A9 (prior to
1137 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1138 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1139 As a consequence of this erratum, some TLB entries which should be
1140 invalidated are not, resulting in an incoherency in the system page
1141 tables. The workaround changes the TLB flushing routines to invalidate
1142 entries regardless of the ASID.
1144 config ARM_ERRATA_743622
1145 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1147 depends on !ARCH_MULTIPLATFORM
1149 This option enables the workaround for the 743622 Cortex-A9
1150 (r2p*) erratum. Under very rare conditions, a faulty
1151 optimisation in the Cortex-A9 Store Buffer may lead to data
1152 corruption. This workaround sets a specific bit in the diagnostic
1153 register of the Cortex-A9 which disables the Store Buffer
1154 optimisation, preventing the defect from occurring. This has no
1155 visible impact on the overall performance or power consumption of the
1158 config ARM_ERRATA_751472
1159 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1161 depends on !ARCH_MULTIPLATFORM
1163 This option enables the workaround for the 751472 Cortex-A9 (prior
1164 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1165 completion of a following broadcasted operation if the second
1166 operation is received by a CPU before the ICIALLUIS has completed,
1167 potentially leading to corrupted entries in the cache or TLB.
1169 config ARM_ERRATA_754322
1170 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1173 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1174 r3p*) erratum. A speculative memory access may cause a page table walk
1175 which starts prior to an ASID switch but completes afterwards. This
1176 can populate the micro-TLB with a stale entry which may be hit with
1177 the new ASID. This workaround places two dsb instructions in the mm
1178 switching code so that no page table walks can cross the ASID switch.
1180 config ARM_ERRATA_754327
1181 bool "ARM errata: no automatic Store Buffer drain"
1182 depends on CPU_V7 && SMP
1184 This option enables the workaround for the 754327 Cortex-A9 (prior to
1185 r2p0) erratum. The Store Buffer does not have any automatic draining
1186 mechanism and therefore a livelock may occur if an external agent
1187 continuously polls a memory location waiting to observe an update.
1188 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1189 written polling loops from denying visibility of updates to memory.
1191 config ARM_ERRATA_364296
1192 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1195 This options enables the workaround for the 364296 ARM1136
1196 r0p2 erratum (possible cache data corruption with
1197 hit-under-miss enabled). It sets the undocumented bit 31 in
1198 the auxiliary control register and the FI bit in the control
1199 register, thus disabling hit-under-miss without putting the
1200 processor into full low interrupt latency mode. ARM11MPCore
1203 config ARM_ERRATA_764369
1204 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1205 depends on CPU_V7 && SMP
1207 This option enables the workaround for erratum 764369
1208 affecting Cortex-A9 MPCore with two or more processors (all
1209 current revisions). Under certain timing circumstances, a data
1210 cache line maintenance operation by MVA targeting an Inner
1211 Shareable memory region may fail to proceed up to either the
1212 Point of Coherency or to the Point of Unification of the
1213 system. This workaround adds a DSB instruction before the
1214 relevant cache maintenance functions and sets a specific bit
1215 in the diagnostic control register of the SCU.
1217 config ARM_ERRATA_775420
1218 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1221 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1222 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1223 operation aborts with MMU exception, it might cause the processor
1224 to deadlock. This workaround puts DSB before executing ISB if
1225 an abort may occur on cache maintenance.
1227 config ARM_ERRATA_798181
1228 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1229 depends on CPU_V7 && SMP
1231 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1232 adequately shooting down all use of the old entries. This
1233 option enables the Linux kernel workaround for this erratum
1234 which sends an IPI to the CPUs that are running the same ASID
1235 as the one being invalidated.
1237 config ARM_ERRATA_773022
1238 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1241 This option enables the workaround for the 773022 Cortex-A15
1242 (up to r0p4) erratum. In certain rare sequences of code, the
1243 loop buffer may deliver incorrect instructions. This
1244 workaround disables the loop buffer to avoid the erratum.
1248 source "arch/arm/common/Kconfig"
1255 Find out whether you have ISA slots on your motherboard. ISA is the
1256 name of a bus system, i.e. the way the CPU talks to the other stuff
1257 inside your box. Other bus systems are PCI, EISA, MicroChannel
1258 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1259 newer boards don't support it. If you have ISA, say Y, otherwise N.
1261 # Select ISA DMA controller support
1266 # Select ISA DMA interface
1271 bool "PCI support" if MIGHT_HAVE_PCI
1273 Find out whether you have a PCI motherboard. PCI is the name of a
1274 bus system, i.e. the way the CPU talks to the other stuff inside
1275 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1276 VESA. If you have PCI, say Y, otherwise N.
1282 config PCI_DOMAINS_GENERIC
1283 def_bool PCI_DOMAINS
1285 config PCI_NANOENGINE
1286 bool "BSE nanoEngine PCI support"
1287 depends on SA1100_NANOENGINE
1289 Enable PCI on the BSE nanoEngine board.
1294 config PCI_HOST_ITE8152
1296 depends on PCI && MACH_ARMCORE
1300 source "drivers/pci/Kconfig"
1301 source "drivers/pci/pcie/Kconfig"
1303 source "drivers/pcmcia/Kconfig"
1307 menu "Kernel Features"
1312 This option should be selected by machines which have an SMP-
1315 The only effect of this option is to make the SMP-related
1316 options available to the user for configuration.
1319 bool "Symmetric Multi-Processing"
1320 depends on CPU_V6K || CPU_V7
1321 depends on GENERIC_CLOCKEVENTS
1323 depends on MMU || ARM_MPU
1326 This enables support for systems with more than one CPU. If you have
1327 a system with only one CPU, say N. If you have a system with more
1328 than one CPU, say Y.
1330 If you say N here, the kernel will run on uni- and multiprocessor
1331 machines, but will use only one CPU of a multiprocessor machine. If
1332 you say Y here, the kernel will run on many, but not all,
1333 uniprocessor machines. On a uniprocessor machine, the kernel
1334 will run faster if you say N here.
1336 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1337 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1338 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1340 If you don't know what to do here, say N.
1343 bool "Allow booting SMP kernel on uniprocessor systems"
1344 depends on SMP && !XIP_KERNEL && MMU
1347 SMP kernels contain instructions which fail on non-SMP processors.
1348 Enabling this option allows the kernel to modify itself to make
1349 these instructions safe. Disabling it allows about 1K of space
1352 If you don't know what to do here, say Y.
1354 config ARM_CPU_TOPOLOGY
1355 bool "Support cpu topology definition"
1356 depends on SMP && CPU_V7
1359 Support ARM cpu topology definition. The MPIDR register defines
1360 affinity between processors which is then used to describe the cpu
1361 topology of an ARM System.
1364 bool "Multi-core scheduler support"
1365 depends on ARM_CPU_TOPOLOGY
1367 Multi-core scheduler support improves the CPU scheduler's decision
1368 making when dealing with multi-core CPU chips at a cost of slightly
1369 increased overhead in some places. If unsure say N here.
1372 bool "SMT scheduler support"
1373 depends on ARM_CPU_TOPOLOGY
1375 Improves the CPU scheduler's decision making when dealing with
1376 MultiThreading at a cost of slightly increased overhead in some
1377 places. If unsure say N here.
1382 This option enables support for the ARM system coherency unit
1384 config HAVE_ARM_ARCH_TIMER
1385 bool "Architected timer support"
1387 select ARM_ARCH_TIMER
1388 select GENERIC_CLOCKEVENTS
1390 This option enables support for the ARM architected timer
1394 select CLKSRC_OF if OF
1396 This options enables support for the ARM timer and watchdog unit
1399 bool "Multi-Cluster Power Management"
1400 depends on CPU_V7 && SMP
1402 This option provides the common power management infrastructure
1403 for (multi-)cluster based systems, such as big.LITTLE based
1406 config MCPM_QUAD_CLUSTER
1410 To avoid wasting resources unnecessarily, MCPM only supports up
1411 to 2 clusters by default.
1412 Platforms with 3 or 4 clusters that use MCPM must select this
1413 option to allow the additional clusters to be managed.
1416 bool "big.LITTLE support (Experimental)"
1417 depends on CPU_V7 && SMP
1420 This option enables support selections for the big.LITTLE
1421 system architecture.
1424 bool "big.LITTLE switcher support"
1425 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1426 select ARM_CPU_SUSPEND
1429 The big.LITTLE "switcher" provides the core functionality to
1430 transparently handle transition between a cluster of A15's
1431 and a cluster of A7's in a big.LITTLE system.
1433 config BL_SWITCHER_DUMMY_IF
1434 tristate "Simple big.LITTLE switcher user interface"
1435 depends on BL_SWITCHER && DEBUG_KERNEL
1437 This is a simple and dummy char dev interface to control
1438 the big.LITTLE switcher core code. It is meant for
1439 debugging purposes only.
1442 prompt "Memory split"
1446 Select the desired split between kernel and user memory.
1448 If you are not absolutely sure what you are doing, leave this
1452 bool "3G/1G user/kernel split"
1453 config VMSPLIT_3G_OPT
1454 bool "3G/1G user/kernel split (for full 1G low memory)"
1456 bool "2G/2G user/kernel split"
1458 bool "1G/3G user/kernel split"
1463 default PHYS_OFFSET if !MMU
1464 default 0x40000000 if VMSPLIT_1G
1465 default 0x80000000 if VMSPLIT_2G
1466 default 0xB0000000 if VMSPLIT_3G_OPT
1470 int "Maximum number of CPUs (2-32)"
1476 bool "Support for hot-pluggable CPUs"
1479 Say Y here to experiment with turning CPUs off and on. CPUs
1480 can be controlled through /sys/devices/system/cpu.
1483 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1487 Say Y here if you want Linux to communicate with system firmware
1488 implementing the PSCI specification for CPU-centric power
1489 management operations described in ARM document number ARM DEN
1490 0022A ("Power State Coordination Interface System Software on
1493 # The GPIO number here must be sorted by descending number. In case of
1494 # a multiplatform kernel, we just want the highest value required by the
1495 # selected platforms.
1498 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1500 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1501 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1502 default 416 if ARCH_SUNXI
1503 default 392 if ARCH_U8500
1504 default 352 if ARCH_VT8500
1505 default 288 if ARCH_ROCKCHIP
1506 default 264 if MACH_H4700
1509 Maximum number of GPIOs in the system.
1511 If unsure, leave the default value.
1513 source kernel/Kconfig.preempt
1517 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1518 ARCH_S5PV210 || ARCH_EXYNOS4
1519 default 128 if SOC_AT91RM9200
1523 depends on HZ_FIXED = 0
1524 prompt "Timer frequency"
1548 default HZ_FIXED if HZ_FIXED != 0
1549 default 100 if HZ_100
1550 default 200 if HZ_200
1551 default 250 if HZ_250
1552 default 300 if HZ_300
1553 default 500 if HZ_500
1557 def_bool HIGH_RES_TIMERS
1559 config THUMB2_KERNEL
1560 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1561 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1562 default y if CPU_THUMBONLY
1564 select ARM_ASM_UNIFIED
1567 By enabling this option, the kernel will be compiled in
1568 Thumb-2 mode. A compiler/assembler that understand the unified
1569 ARM-Thumb syntax is needed.
1573 config THUMB2_AVOID_R_ARM_THM_JUMP11
1574 bool "Work around buggy Thumb-2 short branch relocations in gas"
1575 depends on THUMB2_KERNEL && MODULES
1578 Various binutils versions can resolve Thumb-2 branches to
1579 locally-defined, preemptible global symbols as short-range "b.n"
1580 branch instructions.
1582 This is a problem, because there's no guarantee the final
1583 destination of the symbol, or any candidate locations for a
1584 trampoline, are within range of the branch. For this reason, the
1585 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1586 relocation in modules at all, and it makes little sense to add
1589 The symptom is that the kernel fails with an "unsupported
1590 relocation" error when loading some modules.
1592 Until fixed tools are available, passing
1593 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1594 code which hits this problem, at the cost of a bit of extra runtime
1595 stack usage in some cases.
1597 The problem is described in more detail at:
1598 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1600 Only Thumb-2 kernels are affected.
1602 Unless you are sure your tools don't have this problem, say Y.
1604 config ARM_ASM_UNIFIED
1607 config ARM_PATCH_IDIV
1608 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1609 depends on CPU_32v7 && !XIP_KERNEL
1612 The ARM compiler inserts calls to __aeabi_idiv() and
1613 __aeabi_uidiv() when it needs to perform division on signed
1614 and unsigned integers. Some v7 CPUs have support for the sdiv
1615 and udiv instructions that can be used to implement those
1618 Enabling this option allows the kernel to modify itself to
1619 replace the first two instructions of these library functions
1620 with the sdiv or udiv plus "bx lr" instructions when the CPU
1621 it is running on supports them. Typically this will be faster
1622 and less power intensive than running the original library
1623 code to do integer division.
1626 bool "Use the ARM EABI to compile the kernel"
1628 This option allows for the kernel to be compiled using the latest
1629 ARM ABI (aka EABI). This is only useful if you are using a user
1630 space environment that is also compiled with EABI.
1632 Since there are major incompatibilities between the legacy ABI and
1633 EABI, especially with regard to structure member alignment, this
1634 option also changes the kernel syscall calling convention to
1635 disambiguate both ABIs and allow for backward compatibility support
1636 (selected with CONFIG_OABI_COMPAT).
1638 To use this you need GCC version 4.0.0 or later.
1641 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1642 depends on AEABI && !THUMB2_KERNEL
1644 This option preserves the old syscall interface along with the
1645 new (ARM EABI) one. It also provides a compatibility layer to
1646 intercept syscalls that have structure arguments which layout
1647 in memory differs between the legacy ABI and the new ARM EABI
1648 (only for non "thumb" binaries). This option adds a tiny
1649 overhead to all syscalls and produces a slightly larger kernel.
1651 The seccomp filter system will not be available when this is
1652 selected, since there is no way yet to sensibly distinguish
1653 between calling conventions during filtering.
1655 If you know you'll be using only pure EABI user space then you
1656 can say N here. If this option is not selected and you attempt
1657 to execute a legacy ABI binary then the result will be
1658 UNPREDICTABLE (in fact it can be predicted that it won't work
1659 at all). If in doubt say N.
1661 config ARCH_HAS_HOLES_MEMORYMODEL
1664 config ARCH_SPARSEMEM_ENABLE
1667 config ARCH_SPARSEMEM_DEFAULT
1668 def_bool ARCH_SPARSEMEM_ENABLE
1670 config ARCH_SELECT_MEMORY_MODEL
1671 def_bool ARCH_SPARSEMEM_ENABLE
1673 config HAVE_ARCH_PFN_VALID
1674 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1676 config HAVE_GENERIC_RCU_GUP
1681 bool "High Memory Support"
1684 The address space of ARM processors is only 4 Gigabytes large
1685 and it has to accommodate user address space, kernel address
1686 space as well as some memory mapped IO. That means that, if you
1687 have a large amount of physical memory and/or IO, not all of the
1688 memory can be "permanently mapped" by the kernel. The physical
1689 memory that is not permanently mapped is called "high memory".
1691 Depending on the selected kernel/user memory split, minimum
1692 vmalloc space and actual amount of RAM, you may not need this
1693 option which should result in a slightly faster kernel.
1698 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1702 The VM uses one page of physical memory for each page table.
1703 For systems with a lot of processes, this can use a lot of
1704 precious low memory, eventually leading to low memory being
1705 consumed by page tables. Setting this option will allow
1706 user-space 2nd level page tables to reside in high memory.
1708 config CPU_SW_DOMAIN_PAN
1709 bool "Enable use of CPU domains to implement privileged no-access"
1710 depends on MMU && !ARM_LPAE
1713 Increase kernel security by ensuring that normal kernel accesses
1714 are unable to access userspace addresses. This can help prevent
1715 use-after-free bugs becoming an exploitable privilege escalation
1716 by ensuring that magic values (such as LIST_POISON) will always
1717 fault when dereferenced.
1719 CPUs with low-vector mappings use a best-efforts implementation.
1720 Their lower 1MB needs to remain accessible for the vectors, but
1721 the remainder of userspace will become appropriately inaccessible.
1723 config HW_PERF_EVENTS
1727 config SYS_SUPPORTS_HUGETLBFS
1731 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1735 config ARCH_WANT_GENERAL_HUGETLB
1738 config ARM_MODULE_PLTS
1739 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1742 Allocate PLTs when loading modules so that jumps and calls whose
1743 targets are too far away for their relative offsets to be encoded
1744 in the instructions themselves can be bounced via veneers in the
1745 module's PLT. This allows modules to be allocated in the generic
1746 vmalloc area after the dedicated module memory area has been
1747 exhausted. The modules will use slightly more memory, but after
1748 rounding up to page size, the actual memory footprint is usually
1751 Say y if you are getting out of memory errors while loading modules
1755 config FORCE_MAX_ZONEORDER
1756 int "Maximum zone order"
1757 default "12" if SOC_AM33XX
1758 default "9" if SA1111 || ARCH_EFM32
1761 The kernel memory allocator divides physically contiguous memory
1762 blocks into "zones", where each zone is a power of two number of
1763 pages. This option selects the largest power of two that the kernel
1764 keeps in the memory allocator. If you need to allocate very large
1765 blocks of physically contiguous memory, then you may need to
1766 increase this value.
1768 This config option is actually maximum order plus one. For example,
1769 a value of 11 means that the largest free memory block is 2^10 pages.
1771 config ALIGNMENT_TRAP
1773 depends on CPU_CP15_MMU
1774 default y if !ARCH_EBSA110
1775 select HAVE_PROC_CPU if PROC_FS
1777 ARM processors cannot fetch/store information which is not
1778 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1779 address divisible by 4. On 32-bit ARM processors, these non-aligned
1780 fetch/store instructions will be emulated in software if you say
1781 here, which has a severe performance impact. This is necessary for
1782 correct operation of some network protocols. With an IP-only
1783 configuration it is safe to say N, otherwise say Y.
1785 config UACCESS_WITH_MEMCPY
1786 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1788 default y if CPU_FEROCEON
1790 Implement faster copy_to_user and clear_user methods for CPU
1791 cores where a 8-word STM instruction give significantly higher
1792 memory write throughput than a sequence of individual 32bit stores.
1794 A possible side effect is a slight increase in scheduling latency
1795 between threads sharing the same address space if they invoke
1796 such copy operations with large buffers.
1798 However, if the CPU data cache is using a write-allocate mode,
1799 this option is unlikely to provide any performance gain.
1803 prompt "Enable seccomp to safely compute untrusted bytecode"
1805 This kernel feature is useful for number crunching applications
1806 that may need to compute untrusted bytecode during their
1807 execution. By using pipes or other transports made available to
1808 the process as file descriptors supporting the read/write
1809 syscalls, it's possible to isolate those applications in
1810 their own address space using seccomp. Once seccomp is
1811 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1812 and the task is only allowed to execute a few safe syscalls
1813 defined by each seccomp mode.
1826 bool "Xen guest support on ARM"
1827 depends on ARM && AEABI && OF
1828 depends on CPU_V7 && !CPU_V6
1829 depends on !GENERIC_ATOMIC64
1831 select ARCH_DMA_ADDR_T_64BIT
1835 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1842 bool "Flattened Device Tree support"
1845 select OF_EARLY_FLATTREE
1846 select OF_RESERVED_MEM
1848 Include support for flattened device tree machine descriptions.
1851 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1854 This is the traditional way of passing data to the kernel at boot
1855 time. If you are solely relying on the flattened device tree (or
1856 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1857 to remove ATAGS support from your kernel binary. If unsure,
1860 config DEPRECATED_PARAM_STRUCT
1861 bool "Provide old way to pass kernel parameters"
1864 This was deprecated in 2001 and announced to live on for 5 years.
1865 Some old boot loaders still use this way.
1867 # Compressed boot loader in ROM. Yes, we really want to ask about
1868 # TEXT and BSS so we preserve their values in the config files.
1869 config ZBOOT_ROM_TEXT
1870 hex "Compressed ROM boot loader base address"
1873 The physical address at which the ROM-able zImage is to be
1874 placed in the target. Platforms which normally make use of
1875 ROM-able zImage formats normally set this to a suitable
1876 value in their defconfig file.
1878 If ZBOOT_ROM is not enabled, this has no effect.
1880 config ZBOOT_ROM_BSS
1881 hex "Compressed ROM boot loader BSS address"
1884 The base address of an area of read/write memory in the target
1885 for the ROM-able zImage which must be available while the
1886 decompressor is running. It must be large enough to hold the
1887 entire decompressed kernel plus an additional 128 KiB.
1888 Platforms which normally make use of ROM-able zImage formats
1889 normally set this to a suitable value in their defconfig file.
1891 If ZBOOT_ROM is not enabled, this has no effect.
1894 bool "Compressed boot loader in ROM/flash"
1895 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1896 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1898 Say Y here if you intend to execute your compressed kernel image
1899 (zImage) directly from ROM or flash. If unsure, say N.
1901 config ARM_APPENDED_DTB
1902 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1905 With this option, the boot code will look for a device tree binary
1906 (DTB) appended to zImage
1907 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1909 This is meant as a backward compatibility convenience for those
1910 systems with a bootloader that can't be upgraded to accommodate
1911 the documented boot protocol using a device tree.
1913 Beware that there is very little in terms of protection against
1914 this option being confused by leftover garbage in memory that might
1915 look like a DTB header after a reboot if no actual DTB is appended
1916 to zImage. Do not leave this option active in a production kernel
1917 if you don't intend to always append a DTB. Proper passing of the
1918 location into r2 of a bootloader provided DTB is always preferable
1921 config ARM_ATAG_DTB_COMPAT
1922 bool "Supplement the appended DTB with traditional ATAG information"
1923 depends on ARM_APPENDED_DTB
1925 Some old bootloaders can't be updated to a DTB capable one, yet
1926 they provide ATAGs with memory configuration, the ramdisk address,
1927 the kernel cmdline string, etc. Such information is dynamically
1928 provided by the bootloader and can't always be stored in a static
1929 DTB. To allow a device tree enabled kernel to be used with such
1930 bootloaders, this option allows zImage to extract the information
1931 from the ATAG list and store it at run time into the appended DTB.
1934 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1935 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1937 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1938 bool "Use bootloader kernel arguments if available"
1940 Uses the command-line options passed by the boot loader instead of
1941 the device tree bootargs property. If the boot loader doesn't provide
1942 any, the device tree bootargs property will be used.
1944 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1945 bool "Extend with bootloader kernel arguments"
1947 The command-line arguments provided by the boot loader will be
1948 appended to the the device tree bootargs property.
1953 string "Default kernel command string"
1956 On some architectures (EBSA110 and CATS), there is currently no way
1957 for the boot loader to pass arguments to the kernel. For these
1958 architectures, you should supply some command-line options at build
1959 time by entering them here. As a minimum, you should specify the
1960 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1963 prompt "Kernel command line type" if CMDLINE != ""
1964 default CMDLINE_FROM_BOOTLOADER
1967 config CMDLINE_FROM_BOOTLOADER
1968 bool "Use bootloader kernel arguments if available"
1970 Uses the command-line options passed by the boot loader. If
1971 the boot loader doesn't provide any, the default kernel command
1972 string provided in CMDLINE will be used.
1974 config CMDLINE_EXTEND
1975 bool "Extend bootloader kernel arguments"
1977 The command-line arguments provided by the boot loader will be
1978 appended to the default kernel command string.
1980 config CMDLINE_FORCE
1981 bool "Always use the default kernel command string"
1983 Always use the default kernel command string, even if the boot
1984 loader passes other arguments to the kernel.
1985 This is useful if you cannot or don't want to change the
1986 command-line options your boot loader passes to the kernel.
1990 bool "Kernel Execute-In-Place from ROM"
1991 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1993 Execute-In-Place allows the kernel to run from non-volatile storage
1994 directly addressable by the CPU, such as NOR flash. This saves RAM
1995 space since the text section of the kernel is not loaded from flash
1996 to RAM. Read-write sections, such as the data section and stack,
1997 are still copied to RAM. The XIP kernel is not compressed since
1998 it has to run directly from flash, so it will take more space to
1999 store it. The flash address used to link the kernel object files,
2000 and for storing it, is configuration dependent. Therefore, if you
2001 say Y here, you must know the proper physical address where to
2002 store the kernel image depending on your own flash memory usage.
2004 Also note that the make target becomes "make xipImage" rather than
2005 "make zImage" or "make Image". The final kernel binary to put in
2006 ROM memory will be arch/arm/boot/xipImage.
2010 config XIP_PHYS_ADDR
2011 hex "XIP Kernel Physical Location"
2012 depends on XIP_KERNEL
2013 default "0x00080000"
2015 This is the physical address in your flash memory the kernel will
2016 be linked for and stored to. This address is dependent on your
2020 bool "Kexec system call (EXPERIMENTAL)"
2021 depends on (!SMP || PM_SLEEP_SMP)
2025 kexec is a system call that implements the ability to shutdown your
2026 current kernel, and to start another kernel. It is like a reboot
2027 but it is independent of the system firmware. And like a reboot
2028 you can start any kernel with it, not just Linux.
2030 It is an ongoing process to be certain the hardware in a machine
2031 is properly shutdown, so do not be surprised if this code does not
2032 initially work for you.
2035 bool "Export atags in procfs"
2036 depends on ATAGS && KEXEC
2039 Should the atags used to boot the kernel be exported in an "atags"
2040 file in procfs. Useful with kexec.
2043 bool "Build kdump crash kernel (EXPERIMENTAL)"
2045 Generate crash dump after being started by kexec. This should
2046 be normally only set in special crash dump kernels which are
2047 loaded in the main kernel with kexec-tools into a specially
2048 reserved region and then later executed after a crash by
2049 kdump/kexec. The crash dump kernel must be compiled to a
2050 memory address not used by the main kernel
2052 For more details see Documentation/kdump/kdump.txt
2054 config AUTO_ZRELADDR
2055 bool "Auto calculation of the decompressed kernel image address"
2057 ZRELADDR is the physical address where the decompressed kernel
2058 image will be placed. If AUTO_ZRELADDR is selected, the address
2059 will be determined at run-time by masking the current IP with
2060 0xf8000000. This assumes the zImage being placed in the first 128MB
2061 from start of memory.
2065 menu "CPU Power Management"
2067 source "drivers/cpufreq/Kconfig"
2069 source "drivers/cpuidle/Kconfig"
2073 menu "Floating point emulation"
2075 comment "At least one emulation must be selected"
2078 bool "NWFPE math emulation"
2079 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2081 Say Y to include the NWFPE floating point emulator in the kernel.
2082 This is necessary to run most binaries. Linux does not currently
2083 support floating point hardware so you need to say Y here even if
2084 your machine has an FPA or floating point co-processor podule.
2086 You may say N here if you are going to load the Acorn FPEmulator
2087 early in the bootup.
2090 bool "Support extended precision"
2091 depends on FPE_NWFPE
2093 Say Y to include 80-bit support in the kernel floating-point
2094 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2095 Note that gcc does not generate 80-bit operations by default,
2096 so in most cases this option only enlarges the size of the
2097 floating point emulator without any good reason.
2099 You almost surely want to say N here.
2102 bool "FastFPE math emulation (EXPERIMENTAL)"
2103 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2105 Say Y here to include the FAST floating point emulator in the kernel.
2106 This is an experimental much faster emulator which now also has full
2107 precision for the mantissa. It does not support any exceptions.
2108 It is very simple, and approximately 3-6 times faster than NWFPE.
2110 It should be sufficient for most programs. It may be not suitable
2111 for scientific calculations, but you have to check this for yourself.
2112 If you do not feel you need a faster FP emulation you should better
2116 bool "VFP-format floating point maths"
2117 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2119 Say Y to include VFP support code in the kernel. This is needed
2120 if your hardware includes a VFP unit.
2122 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2123 release notes and additional status information.
2125 Say N if your target does not have VFP hardware.
2133 bool "Advanced SIMD (NEON) Extension support"
2134 depends on VFPv3 && CPU_V7
2136 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2139 config KERNEL_MODE_NEON
2140 bool "Support for NEON in kernel mode"
2141 depends on NEON && AEABI
2143 Say Y to include support for NEON in kernel mode.
2147 menu "Userspace binary formats"
2149 source "fs/Kconfig.binfmt"
2153 menu "Power management options"
2155 source "kernel/power/Kconfig"
2157 config ARCH_SUSPEND_POSSIBLE
2158 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2159 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2162 config ARM_CPU_SUSPEND
2165 config ARCH_HIBERNATION_POSSIBLE
2168 default y if ARCH_SUSPEND_POSSIBLE
2172 source "net/Kconfig"
2174 source "drivers/Kconfig"
2176 source "drivers/firmware/Kconfig"
2180 source "arch/arm/Kconfig.debug"
2182 source "security/Kconfig"
2184 source "crypto/Kconfig"
2186 source "arch/arm/crypto/Kconfig"
2189 source "lib/Kconfig"
2191 source "arch/arm/kvm/Kconfig"