4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_MIGHT_HAVE_PC_PARPORT
10 select ARCH_SUPPORTS_ATOMIC_RMW
11 select ARCH_USE_BUILTIN_BSWAP
12 select ARCH_USE_CMPXCHG_LOCKREF
13 select ARCH_WANT_IPC_PARSE_VERSION
14 select BUILDTIME_EXTABLE_SORT if MMU
15 select CLONE_BACKWARDS
16 select CPU_PM if (SUSPEND || CPU_IDLE)
17 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
18 select GENERIC_ALLOCATOR
19 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
20 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
21 select GENERIC_IDLE_POLL_SETUP
22 select GENERIC_IRQ_PROBE
23 select GENERIC_IRQ_SHOW
24 select GENERIC_IRQ_SHOW_LEVEL
25 select GENERIC_PCI_IOMAP
26 select GENERIC_SCHED_CLOCK
27 select GENERIC_SMP_IDLE_THREAD
28 select GENERIC_STRNCPY_FROM_USER
29 select GENERIC_STRNLEN_USER
30 select HANDLE_DOMAIN_IRQ
31 select HARDIRQS_SW_RESEND
32 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
33 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
34 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
36 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
37 select HAVE_ARCH_TRACEHOOK
39 select HAVE_CC_STACKPROTECTOR
40 select HAVE_CONTEXT_TRACKING
41 select HAVE_C_RECORDMCOUNT
42 select HAVE_DEBUG_KMEMLEAK
43 select HAVE_DMA_API_DEBUG
45 select HAVE_DMA_CONTIGUOUS if MMU
46 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
47 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
48 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
49 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
50 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
51 select HAVE_GENERIC_DMA_COHERENT
52 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
53 select HAVE_IDE if PCI || ISA || PCMCIA
54 select HAVE_IRQ_TIME_ACCOUNTING
55 select HAVE_KERNEL_GZIP
56 select HAVE_KERNEL_LZ4
57 select HAVE_KERNEL_LZMA
58 select HAVE_KERNEL_LZO
60 select HAVE_KPROBES if !XIP_KERNEL
61 select HAVE_KRETPROBES if (HAVE_KPROBES)
63 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
64 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
65 select HAVE_OPTPROBES if !THUMB2_KERNEL
66 select HAVE_PERF_EVENTS
68 select HAVE_PERF_USER_STACK_DUMP
69 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
70 select HAVE_REGS_AND_STACK_ACCESS_API
71 select HAVE_SYSCALL_TRACEPOINTS
73 select HAVE_VIRT_CPU_ACCOUNTING_GEN
74 select IRQ_FORCED_THREADING
75 select MODULES_USE_ELF_REL
78 select OLD_SIGSUSPEND3
79 select PERF_USE_VMALLOC
81 select SYS_SUPPORTS_APM_EMULATION
82 # Above selects are sorted alphabetically; please add new ones
83 # according to that. Thanks.
85 The ARM series is a line of low-power-consumption RISC chip designs
86 licensed by ARM Ltd and targeted at embedded applications and
87 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
88 manufactured, but legacy ARM-based PC hardware remains popular in
89 Europe. There is an ARM Linux project with a web page at
90 <http://www.arm.linux.org.uk/>.
92 config ARM_HAS_SG_CHAIN
93 select ARCH_HAS_SG_CHAIN
96 config NEED_SG_DMA_LENGTH
99 config ARM_DMA_USE_IOMMU
101 select ARM_HAS_SG_CHAIN
102 select NEED_SG_DMA_LENGTH
106 config ARM_DMA_IOMMU_ALIGNMENT
107 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
111 DMA mapping framework by default aligns all buffers to the smallest
112 PAGE_SIZE order which is greater than or equal to the requested buffer
113 size. This works well for buffers up to a few hundreds kilobytes, but
114 for larger buffers it just a waste of address space. Drivers which has
115 relatively small addressing window (like 64Mib) might run out of
116 virtual space with just a few allocations.
118 With this parameter you can specify the maximum PAGE_SIZE order for
119 DMA IOMMU buffers. Larger buffers will be aligned only to this
120 specified order. The order is expressed as a power of two multiplied
125 config MIGHT_HAVE_PCI
128 config SYS_SUPPORTS_APM_EMULATION
133 select GENERIC_ALLOCATOR
144 The Extended Industry Standard Architecture (EISA) bus was
145 developed as an open alternative to the IBM MicroChannel bus.
147 The EISA bus provided some of the features of the IBM MicroChannel
148 bus while maintaining backward compatibility with cards made for
149 the older ISA bus. The EISA bus saw limited use between 1988 and
150 1995 when it was made obsolete by the PCI bus.
152 Say Y here if you are building a kernel for an EISA-based machine.
159 config STACKTRACE_SUPPORT
163 config HAVE_LATENCYTOP_SUPPORT
168 config LOCKDEP_SUPPORT
172 config TRACE_IRQFLAGS_SUPPORT
176 config RWSEM_XCHGADD_ALGORITHM
180 config ARCH_HAS_ILOG2_U32
183 config ARCH_HAS_ILOG2_U64
186 config ARCH_HAS_BANDGAP
189 config GENERIC_HWEIGHT
193 config GENERIC_CALIBRATE_DELAY
197 config ARCH_MAY_HAVE_PC_FDC
203 config NEED_DMA_MAP_STATE
206 config ARCH_SUPPORTS_UPROBES
209 config ARCH_HAS_DMA_SET_COHERENT_MASK
212 config GENERIC_ISA_DMA
218 config NEED_RET_TO_USER
226 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
227 default DRAM_BASE if REMAP_VECTORS_TO_RAM
230 The base address of exception vectors. This must be two pages
233 config ARM_PATCH_PHYS_VIRT
234 bool "Patch physical to virtual translations at runtime" if EMBEDDED
236 depends on !XIP_KERNEL && MMU
237 depends on !ARCH_REALVIEW || !SPARSEMEM
239 Patch phys-to-virt and virt-to-phys translation functions at
240 boot and module load time according to the position of the
241 kernel in system memory.
243 This can only be used with non-XIP MMU kernels where the base
244 of physical memory is at a 16MB boundary.
246 Only disable this option if you know that you do not require
247 this feature (eg, building a kernel for a single machine) and
248 you need to shrink the kernel to the minimal size.
250 config NEED_MACH_IO_H
253 Select this when mach/io.h is required to provide special
254 definitions for this platform. The need for mach/io.h should
255 be avoided when possible.
257 config NEED_MACH_MEMORY_H
260 Select this when mach/memory.h is required to provide special
261 definitions for this platform. The need for mach/memory.h should
262 be avoided when possible.
265 hex "Physical address of main memory" if MMU
266 depends on !ARM_PATCH_PHYS_VIRT
267 default DRAM_BASE if !MMU
268 default 0x00000000 if ARCH_EBSA110 || \
269 EP93XX_SDCE3_SYNC_PHYS_OFFSET || \
274 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
275 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
276 default 0x20000000 if ARCH_S5PV210
277 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
278 default 0xc0000000 if EP93XX_SDCE0_PHYS_OFFSET || ARCH_SA1100
279 default 0xd0000000 if EP93XX_SDCE1_PHYS_OFFSET
280 default 0xe0000000 if EP93XX_SDCE2_PHYS_OFFSET
281 default 0xf0000000 if EP93XX_SDCE3_ASYNC_PHYS_OFFSET
283 Please provide the physical address corresponding to the
284 location of main memory in your system.
290 source "init/Kconfig"
292 source "kernel/Kconfig.freezer"
297 bool "MMU-based Paged Memory Management Support"
300 Select if you want MMU-based virtualised addressing space
301 support by paged memory management. If unsure, say 'Y'.
304 # The "ARM system type" choice list is ordered alphabetically by option
305 # text. Please add new entries in the option alphabetic order.
308 prompt "ARM system type"
309 default ARCH_VERSATILE if !MMU
310 default ARCH_MULTIPLATFORM if MMU
312 config ARCH_MULTIPLATFORM
313 bool "Allow multiple platforms to be selected"
315 select ARCH_WANT_OPTIONAL_GPIOLIB
316 select ARM_HAS_SG_CHAIN
317 select ARM_PATCH_PHYS_VIRT
321 select GENERIC_CLOCKEVENTS
322 select MIGHT_HAVE_PCI
323 select MULTI_IRQ_HANDLER
328 bool "ARM Ltd. RealView family"
329 select ARCH_WANT_OPTIONAL_GPIOLIB
331 select ARM_TIMER_SP804
333 select COMMON_CLK_VERSATILE
334 select GENERIC_CLOCKEVENTS
335 select GPIO_PL061 if GPIOLIB
337 select NEED_MACH_MEMORY_H
338 select PLAT_VERSATILE
339 select PLAT_VERSATILE_SCHED_CLOCK
341 This enables support for ARM Ltd RealView boards.
343 config ARCH_VERSATILE
344 bool "ARM Ltd. Versatile family"
345 select ARCH_WANT_OPTIONAL_GPIOLIB
347 select ARM_TIMER_SP804
350 select GENERIC_CLOCKEVENTS
351 select HAVE_MACH_CLKDEV
353 select PLAT_VERSATILE
354 select PLAT_VERSATILE_CLOCK
355 select PLAT_VERSATILE_SCHED_CLOCK
356 select VERSATILE_FPGA_IRQ
358 This enables support for ARM Ltd Versatile board.
361 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
362 select ARCH_REQUIRE_GPIOLIB
367 select GENERIC_CLOCKEVENTS
371 Support for Cirrus Logic 711x/721x/731x based boards.
374 bool "Cortina Systems Gemini"
375 select ARCH_REQUIRE_GPIOLIB
378 select GENERIC_CLOCKEVENTS
380 Support for the Cortina Systems Gemini family SoCs
384 select ARCH_USES_GETTIMEOFFSET
387 select NEED_MACH_IO_H
388 select NEED_MACH_MEMORY_H
391 This is an evaluation board for the StrongARM processor available
392 from Digital. It has limited hardware on-board, including an
393 Ethernet interface, two PCMCIA sockets, two serial ports and a
397 bool "Energy Micro efm32"
399 select ARCH_REQUIRE_GPIOLIB
405 select GENERIC_CLOCKEVENTS
411 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
416 select ARCH_HAS_HOLES_MEMORYMODEL
417 select ARCH_REQUIRE_GPIOLIB
418 select ARCH_USES_GETTIMEOFFSET
424 This enables support for the Cirrus EP93xx series of CPUs.
426 config ARCH_FOOTBRIDGE
430 select GENERIC_CLOCKEVENTS
432 select NEED_MACH_IO_H if !MMU
433 select NEED_MACH_MEMORY_H
435 Support for systems based on the DC21285 companion chip
436 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
439 bool "Hilscher NetX based"
443 select GENERIC_CLOCKEVENTS
445 This enables support for systems based on the Hilscher NetX Soc
451 select NEED_MACH_MEMORY_H
452 select NEED_RET_TO_USER
458 Support for Intel's IOP13XX (XScale) family of processors.
463 select ARCH_REQUIRE_GPIOLIB
466 select NEED_RET_TO_USER
470 Support for Intel's 80219 and IOP32X (XScale) family of
476 select ARCH_REQUIRE_GPIOLIB
479 select NEED_RET_TO_USER
483 Support for Intel's IOP33X (XScale) family of processors.
488 select ARCH_HAS_DMA_SET_COHERENT_MASK
489 select ARCH_REQUIRE_GPIOLIB
490 select ARCH_SUPPORTS_BIG_ENDIAN
493 select DMABOUNCE if PCI
494 select GENERIC_CLOCKEVENTS
495 select MIGHT_HAVE_PCI
496 select NEED_MACH_IO_H
497 select USB_EHCI_BIG_ENDIAN_DESC
498 select USB_EHCI_BIG_ENDIAN_MMIO
500 Support for Intel's IXP4XX (XScale) family of processors.
504 select ARCH_REQUIRE_GPIOLIB
506 select GENERIC_CLOCKEVENTS
507 select MIGHT_HAVE_PCI
511 select PLAT_ORION_LEGACY
513 Support for the Marvell Dove SoC 88AP510
516 bool "Marvell MV78xx0"
517 select ARCH_REQUIRE_GPIOLIB
519 select GENERIC_CLOCKEVENTS
522 select PLAT_ORION_LEGACY
524 Support for the following Marvell MV78xx0 series SoCs:
530 select ARCH_REQUIRE_GPIOLIB
532 select GENERIC_CLOCKEVENTS
535 select PLAT_ORION_LEGACY
537 Support for the following Marvell Orion 5x series SoCs:
538 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
539 Orion-2 (5281), Orion-1-90 (6183).
542 bool "Marvell PXA168/910/MMP2"
544 select ARCH_REQUIRE_GPIOLIB
546 select GENERIC_ALLOCATOR
547 select GENERIC_CLOCKEVENTS
550 select MULTI_IRQ_HANDLER
555 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
558 bool "Micrel/Kendin KS8695"
559 select ARCH_REQUIRE_GPIOLIB
562 select GENERIC_CLOCKEVENTS
563 select NEED_MACH_MEMORY_H
565 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
566 System-on-Chip devices.
569 bool "Nuvoton W90X900 CPU"
570 select ARCH_REQUIRE_GPIOLIB
574 select GENERIC_CLOCKEVENTS
576 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
577 At present, the w90x900 has been renamed nuc900, regarding
578 the ARM series product line, you can login the following
579 link address to know more.
581 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
582 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
586 select ARCH_REQUIRE_GPIOLIB
591 select GENERIC_CLOCKEVENTS
595 Support for the NXP LPC32XX family of processors
598 bool "PXA2xx/PXA3xx-based"
601 select ARCH_REQUIRE_GPIOLIB
602 select ARM_CPU_SUSPEND if PM
607 select GENERIC_CLOCKEVENTS
611 select MULTI_IRQ_HANDLER
615 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
617 config ARCH_SHMOBILE_LEGACY
618 bool "Renesas ARM SoCs (non-multiplatform)"
620 select ARM_PATCH_PHYS_VIRT if MMU
623 select GENERIC_CLOCKEVENTS
624 select HAVE_ARM_SCU if SMP
625 select HAVE_ARM_TWD if SMP
627 select MIGHT_HAVE_CACHE_L2X0
628 select MULTI_IRQ_HANDLER
631 select PM_GENERIC_DOMAINS if PM
635 Support for Renesas ARM SoC platforms using a non-multiplatform
636 kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
642 select ARCH_MAY_HAVE_PC_FDC
643 select ARCH_SPARSEMEM_ENABLE
644 select ARCH_USES_GETTIMEOFFSET
648 select HAVE_PATA_PLATFORM
650 select NEED_MACH_IO_H
651 select NEED_MACH_MEMORY_H
655 On the Acorn Risc-PC, Linux can support the internal IDE disk and
656 CD-ROM interface, serial and parallel port, and the floppy drive.
661 select ARCH_REQUIRE_GPIOLIB
662 select ARCH_SPARSEMEM_ENABLE
667 select GENERIC_CLOCKEVENTS
671 select MULTI_IRQ_HANDLER
672 select NEED_MACH_MEMORY_H
675 Support for StrongARM 11x0 based boards.
678 bool "Samsung S3C24XX SoCs"
679 select ARCH_REQUIRE_GPIOLIB
682 select CLKSRC_SAMSUNG_PWM
683 select GENERIC_CLOCKEVENTS
685 select HAVE_S3C2410_I2C if I2C
686 select HAVE_S3C2410_WATCHDOG if WATCHDOG
687 select HAVE_S3C_RTC if RTC_CLASS
688 select MULTI_IRQ_HANDLER
689 select NEED_MACH_IO_H
692 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
693 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
694 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
695 Samsung SMDK2410 development board (and derivatives).
698 bool "Samsung S3C64XX"
699 select ARCH_REQUIRE_GPIOLIB
704 select CLKSRC_SAMSUNG_PWM
705 select COMMON_CLK_SAMSUNG
707 select GENERIC_CLOCKEVENTS
709 select HAVE_S3C2410_I2C if I2C
710 select HAVE_S3C2410_WATCHDOG if WATCHDOG
714 select PM_GENERIC_DOMAINS if PM
716 select S3C_GPIO_TRACK
718 select SAMSUNG_WAKEMASK
719 select SAMSUNG_WDT_RESET
721 Samsung S3C64XX series based systems
725 select ARCH_HAS_HOLES_MEMORYMODEL
726 select ARCH_REQUIRE_GPIOLIB
728 select GENERIC_ALLOCATOR
729 select GENERIC_CLOCKEVENTS
730 select GENERIC_IRQ_CHIP
736 Support for TI's DaVinci platform.
741 select ARCH_HAS_HOLES_MEMORYMODEL
743 select ARCH_REQUIRE_GPIOLIB
746 select GENERIC_CLOCKEVENTS
747 select GENERIC_IRQ_CHIP
750 select NEED_MACH_IO_H if PCCARD
751 select NEED_MACH_MEMORY_H
753 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
757 menu "Multiple platform selection"
758 depends on ARCH_MULTIPLATFORM
760 comment "CPU Core family selection"
763 bool "ARMv4 based platforms (FA526)"
764 depends on !ARCH_MULTI_V6_V7
765 select ARCH_MULTI_V4_V5
768 config ARCH_MULTI_V4T
769 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
770 depends on !ARCH_MULTI_V6_V7
771 select ARCH_MULTI_V4_V5
772 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
773 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
774 CPU_ARM925T || CPU_ARM940T)
777 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
778 depends on !ARCH_MULTI_V6_V7
779 select ARCH_MULTI_V4_V5
780 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
781 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
782 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
784 config ARCH_MULTI_V4_V5
788 bool "ARMv6 based platforms (ARM11)"
789 select ARCH_MULTI_V6_V7
793 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
795 select ARCH_MULTI_V6_V7
799 config ARCH_MULTI_V6_V7
801 select MIGHT_HAVE_CACHE_L2X0
803 config ARCH_MULTI_CPU_AUTO
804 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
810 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
814 select HAVE_ARM_ARCH_TIMER
817 # This is sorted alphabetically by mach-* pathname. However, plat-*
818 # Kconfigs may be included either alphabetically (according to the
819 # plat- suffix) or along side the corresponding mach-* source.
821 source "arch/arm/mach-mvebu/Kconfig"
823 source "arch/arm/mach-alpine/Kconfig"
825 source "arch/arm/mach-asm9260/Kconfig"
827 source "arch/arm/mach-at91/Kconfig"
829 source "arch/arm/mach-axxia/Kconfig"
831 source "arch/arm/mach-bcm/Kconfig"
833 source "arch/arm/mach-berlin/Kconfig"
835 source "arch/arm/mach-clps711x/Kconfig"
837 source "arch/arm/mach-cns3xxx/Kconfig"
839 source "arch/arm/mach-davinci/Kconfig"
841 source "arch/arm/mach-digicolor/Kconfig"
843 source "arch/arm/mach-dove/Kconfig"
845 source "arch/arm/mach-ep93xx/Kconfig"
847 source "arch/arm/mach-footbridge/Kconfig"
849 source "arch/arm/mach-gemini/Kconfig"
851 source "arch/arm/mach-highbank/Kconfig"
853 source "arch/arm/mach-hisi/Kconfig"
855 source "arch/arm/mach-integrator/Kconfig"
857 source "arch/arm/mach-iop32x/Kconfig"
859 source "arch/arm/mach-iop33x/Kconfig"
861 source "arch/arm/mach-iop13xx/Kconfig"
863 source "arch/arm/mach-ixp4xx/Kconfig"
865 source "arch/arm/mach-keystone/Kconfig"
867 source "arch/arm/mach-ks8695/Kconfig"
869 source "arch/arm/mach-meson/Kconfig"
871 source "arch/arm/mach-moxart/Kconfig"
873 source "arch/arm/mach-mv78xx0/Kconfig"
875 source "arch/arm/mach-imx/Kconfig"
877 source "arch/arm/mach-mediatek/Kconfig"
879 source "arch/arm/mach-mxs/Kconfig"
881 source "arch/arm/mach-netx/Kconfig"
883 source "arch/arm/mach-nomadik/Kconfig"
885 source "arch/arm/mach-nspire/Kconfig"
887 source "arch/arm/plat-omap/Kconfig"
889 source "arch/arm/mach-omap1/Kconfig"
891 source "arch/arm/mach-omap2/Kconfig"
893 source "arch/arm/mach-orion5x/Kconfig"
895 source "arch/arm/mach-picoxcell/Kconfig"
897 source "arch/arm/mach-pxa/Kconfig"
898 source "arch/arm/plat-pxa/Kconfig"
900 source "arch/arm/mach-mmp/Kconfig"
902 source "arch/arm/mach-qcom/Kconfig"
904 source "arch/arm/mach-realview/Kconfig"
906 source "arch/arm/mach-rockchip/Kconfig"
908 source "arch/arm/mach-sa1100/Kconfig"
910 source "arch/arm/mach-socfpga/Kconfig"
912 source "arch/arm/mach-spear/Kconfig"
914 source "arch/arm/mach-sti/Kconfig"
916 source "arch/arm/mach-s3c24xx/Kconfig"
918 source "arch/arm/mach-s3c64xx/Kconfig"
920 source "arch/arm/mach-s5pv210/Kconfig"
922 source "arch/arm/mach-exynos/Kconfig"
923 source "arch/arm/plat-samsung/Kconfig"
925 source "arch/arm/mach-shmobile/Kconfig"
927 source "arch/arm/mach-sunxi/Kconfig"
929 source "arch/arm/mach-prima2/Kconfig"
931 source "arch/arm/mach-tegra/Kconfig"
933 source "arch/arm/mach-u300/Kconfig"
935 source "arch/arm/mach-ux500/Kconfig"
937 source "arch/arm/mach-versatile/Kconfig"
939 source "arch/arm/mach-vexpress/Kconfig"
940 source "arch/arm/plat-versatile/Kconfig"
942 source "arch/arm/mach-vt8500/Kconfig"
944 source "arch/arm/mach-w90x900/Kconfig"
946 source "arch/arm/mach-zynq/Kconfig"
948 # Definitions to make life easier
954 select GENERIC_CLOCKEVENTS
960 select GENERIC_IRQ_CHIP
963 config PLAT_ORION_LEGACY
970 config PLAT_VERSATILE
973 config ARM_TIMER_SP804
976 select CLKSRC_OF if OF
978 source "arch/arm/firmware/Kconfig"
980 source arch/arm/mm/Kconfig
983 bool "Enable iWMMXt support"
984 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
985 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
987 Enable support for iWMMXt context switching at run time if
988 running on a CPU that supports it.
990 config MULTI_IRQ_HANDLER
993 Allow each machine to specify it's own IRQ handler at run time.
996 source "arch/arm/Kconfig-nommu"
999 config PJ4B_ERRATA_4742
1000 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1001 depends on CPU_PJ4B && MACH_ARMADA_370
1004 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1005 Event (WFE) IDLE states, a specific timing sensitivity exists between
1006 the retiring WFI/WFE instructions and the newly issued subsequent
1007 instructions. This sensitivity can result in a CPU hang scenario.
1009 The software must insert either a Data Synchronization Barrier (DSB)
1010 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1013 config ARM_ERRATA_326103
1014 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1017 Executing a SWP instruction to read-only memory does not set bit 11
1018 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1019 treat the access as a read, preventing a COW from occurring and
1020 causing the faulting task to livelock.
1022 config ARM_ERRATA_411920
1023 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1024 depends on CPU_V6 || CPU_V6K
1026 Invalidation of the Instruction Cache operation can
1027 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1028 It does not affect the MPCore. This option enables the ARM Ltd.
1029 recommended workaround.
1031 config ARM_ERRATA_430973
1032 bool "ARM errata: Stale prediction on replaced interworking branch"
1035 This option enables the workaround for the 430973 Cortex-A8
1036 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1037 interworking branch is replaced with another code sequence at the
1038 same virtual address, whether due to self-modifying code or virtual
1039 to physical address re-mapping, Cortex-A8 does not recover from the
1040 stale interworking branch prediction. This results in Cortex-A8
1041 executing the new code sequence in the incorrect ARM or Thumb state.
1042 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1043 and also flushes the branch target cache at every context switch.
1044 Note that setting specific bits in the ACTLR register may not be
1045 available in non-secure mode.
1047 config ARM_ERRATA_458693
1048 bool "ARM errata: Processor deadlock when a false hazard is created"
1050 depends on !ARCH_MULTIPLATFORM
1052 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1053 erratum. For very specific sequences of memory operations, it is
1054 possible for a hazard condition intended for a cache line to instead
1055 be incorrectly associated with a different cache line. This false
1056 hazard might then cause a processor deadlock. The workaround enables
1057 the L1 caching of the NEON accesses and disables the PLD instruction
1058 in the ACTLR register. Note that setting specific bits in the ACTLR
1059 register may not be available in non-secure mode.
1061 config ARM_ERRATA_460075
1062 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1064 depends on !ARCH_MULTIPLATFORM
1066 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1067 erratum. Any asynchronous access to the L2 cache may encounter a
1068 situation in which recent store transactions to the L2 cache are lost
1069 and overwritten with stale memory contents from external memory. The
1070 workaround disables the write-allocate mode for the L2 cache via the
1071 ACTLR register. Note that setting specific bits in the ACTLR register
1072 may not be available in non-secure mode.
1074 config ARM_ERRATA_742230
1075 bool "ARM errata: DMB operation may be faulty"
1076 depends on CPU_V7 && SMP
1077 depends on !ARCH_MULTIPLATFORM
1079 This option enables the workaround for the 742230 Cortex-A9
1080 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1081 between two write operations may not ensure the correct visibility
1082 ordering of the two writes. This workaround sets a specific bit in
1083 the diagnostic register of the Cortex-A9 which causes the DMB
1084 instruction to behave as a DSB, ensuring the correct behaviour of
1087 config ARM_ERRATA_742231
1088 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1089 depends on CPU_V7 && SMP
1090 depends on !ARCH_MULTIPLATFORM
1092 This option enables the workaround for the 742231 Cortex-A9
1093 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1094 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1095 accessing some data located in the same cache line, may get corrupted
1096 data due to bad handling of the address hazard when the line gets
1097 replaced from one of the CPUs at the same time as another CPU is
1098 accessing it. This workaround sets specific bits in the diagnostic
1099 register of the Cortex-A9 which reduces the linefill issuing
1100 capabilities of the processor.
1102 config ARM_ERRATA_643719
1103 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1104 depends on CPU_V7 && SMP
1106 This option enables the workaround for the 643719 Cortex-A9 (prior to
1107 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1108 register returns zero when it should return one. The workaround
1109 corrects this value, ensuring cache maintenance operations which use
1110 it behave as intended and avoiding data corruption.
1112 config ARM_ERRATA_720789
1113 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1116 This option enables the workaround for the 720789 Cortex-A9 (prior to
1117 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1118 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1119 As a consequence of this erratum, some TLB entries which should be
1120 invalidated are not, resulting in an incoherency in the system page
1121 tables. The workaround changes the TLB flushing routines to invalidate
1122 entries regardless of the ASID.
1124 config ARM_ERRATA_743622
1125 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1127 depends on !ARCH_MULTIPLATFORM
1129 This option enables the workaround for the 743622 Cortex-A9
1130 (r2p*) erratum. Under very rare conditions, a faulty
1131 optimisation in the Cortex-A9 Store Buffer may lead to data
1132 corruption. This workaround sets a specific bit in the diagnostic
1133 register of the Cortex-A9 which disables the Store Buffer
1134 optimisation, preventing the defect from occurring. This has no
1135 visible impact on the overall performance or power consumption of the
1138 config ARM_ERRATA_751472
1139 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1141 depends on !ARCH_MULTIPLATFORM
1143 This option enables the workaround for the 751472 Cortex-A9 (prior
1144 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1145 completion of a following broadcasted operation if the second
1146 operation is received by a CPU before the ICIALLUIS has completed,
1147 potentially leading to corrupted entries in the cache or TLB.
1149 config ARM_ERRATA_754322
1150 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1153 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1154 r3p*) erratum. A speculative memory access may cause a page table walk
1155 which starts prior to an ASID switch but completes afterwards. This
1156 can populate the micro-TLB with a stale entry which may be hit with
1157 the new ASID. This workaround places two dsb instructions in the mm
1158 switching code so that no page table walks can cross the ASID switch.
1160 config ARM_ERRATA_754327
1161 bool "ARM errata: no automatic Store Buffer drain"
1162 depends on CPU_V7 && SMP
1164 This option enables the workaround for the 754327 Cortex-A9 (prior to
1165 r2p0) erratum. The Store Buffer does not have any automatic draining
1166 mechanism and therefore a livelock may occur if an external agent
1167 continuously polls a memory location waiting to observe an update.
1168 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1169 written polling loops from denying visibility of updates to memory.
1171 config ARM_ERRATA_364296
1172 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1175 This options enables the workaround for the 364296 ARM1136
1176 r0p2 erratum (possible cache data corruption with
1177 hit-under-miss enabled). It sets the undocumented bit 31 in
1178 the auxiliary control register and the FI bit in the control
1179 register, thus disabling hit-under-miss without putting the
1180 processor into full low interrupt latency mode. ARM11MPCore
1183 config ARM_ERRATA_764369
1184 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1185 depends on CPU_V7 && SMP
1187 This option enables the workaround for erratum 764369
1188 affecting Cortex-A9 MPCore with two or more processors (all
1189 current revisions). Under certain timing circumstances, a data
1190 cache line maintenance operation by MVA targeting an Inner
1191 Shareable memory region may fail to proceed up to either the
1192 Point of Coherency or to the Point of Unification of the
1193 system. This workaround adds a DSB instruction before the
1194 relevant cache maintenance functions and sets a specific bit
1195 in the diagnostic control register of the SCU.
1197 config ARM_ERRATA_775420
1198 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1201 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1202 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1203 operation aborts with MMU exception, it might cause the processor
1204 to deadlock. This workaround puts DSB before executing ISB if
1205 an abort may occur on cache maintenance.
1207 config ARM_ERRATA_798181
1208 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1209 depends on CPU_V7 && SMP
1211 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1212 adequately shooting down all use of the old entries. This
1213 option enables the Linux kernel workaround for this erratum
1214 which sends an IPI to the CPUs that are running the same ASID
1215 as the one being invalidated.
1217 config ARM_ERRATA_773022
1218 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1221 This option enables the workaround for the 773022 Cortex-A15
1222 (up to r0p4) erratum. In certain rare sequences of code, the
1223 loop buffer may deliver incorrect instructions. This
1224 workaround disables the loop buffer to avoid the erratum.
1228 source "arch/arm/common/Kconfig"
1235 Find out whether you have ISA slots on your motherboard. ISA is the
1236 name of a bus system, i.e. the way the CPU talks to the other stuff
1237 inside your box. Other bus systems are PCI, EISA, MicroChannel
1238 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1239 newer boards don't support it. If you have ISA, say Y, otherwise N.
1241 # Select ISA DMA controller support
1246 # Select ISA DMA interface
1251 bool "PCI support" if MIGHT_HAVE_PCI
1253 Find out whether you have a PCI motherboard. PCI is the name of a
1254 bus system, i.e. the way the CPU talks to the other stuff inside
1255 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1256 VESA. If you have PCI, say Y, otherwise N.
1262 config PCI_DOMAINS_GENERIC
1263 def_bool PCI_DOMAINS
1265 config PCI_NANOENGINE
1266 bool "BSE nanoEngine PCI support"
1267 depends on SA1100_NANOENGINE
1269 Enable PCI on the BSE nanoEngine board.
1274 config PCI_HOST_ITE8152
1276 depends on PCI && MACH_ARMCORE
1280 source "drivers/pci/Kconfig"
1281 source "drivers/pci/pcie/Kconfig"
1283 source "drivers/pcmcia/Kconfig"
1287 menu "Kernel Features"
1292 This option should be selected by machines which have an SMP-
1295 The only effect of this option is to make the SMP-related
1296 options available to the user for configuration.
1299 bool "Symmetric Multi-Processing"
1300 depends on CPU_V6K || CPU_V7
1301 depends on GENERIC_CLOCKEVENTS
1303 depends on MMU || ARM_MPU
1305 This enables support for systems with more than one CPU. If you have
1306 a system with only one CPU, say N. If you have a system with more
1307 than one CPU, say Y.
1309 If you say N here, the kernel will run on uni- and multiprocessor
1310 machines, but will use only one CPU of a multiprocessor machine. If
1311 you say Y here, the kernel will run on many, but not all,
1312 uniprocessor machines. On a uniprocessor machine, the kernel
1313 will run faster if you say N here.
1315 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1316 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1317 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1319 If you don't know what to do here, say N.
1322 bool "Allow booting SMP kernel on uniprocessor systems"
1323 depends on SMP && !XIP_KERNEL && MMU
1326 SMP kernels contain instructions which fail on non-SMP processors.
1327 Enabling this option allows the kernel to modify itself to make
1328 these instructions safe. Disabling it allows about 1K of space
1331 If you don't know what to do here, say Y.
1333 config ARM_CPU_TOPOLOGY
1334 bool "Support cpu topology definition"
1335 depends on SMP && CPU_V7
1338 Support ARM cpu topology definition. The MPIDR register defines
1339 affinity between processors which is then used to describe the cpu
1340 topology of an ARM System.
1343 bool "Multi-core scheduler support"
1344 depends on ARM_CPU_TOPOLOGY
1346 Multi-core scheduler support improves the CPU scheduler's decision
1347 making when dealing with multi-core CPU chips at a cost of slightly
1348 increased overhead in some places. If unsure say N here.
1351 bool "SMT scheduler support"
1352 depends on ARM_CPU_TOPOLOGY
1354 Improves the CPU scheduler's decision making when dealing with
1355 MultiThreading at a cost of slightly increased overhead in some
1356 places. If unsure say N here.
1361 This option enables support for the ARM system coherency unit
1363 config HAVE_ARM_ARCH_TIMER
1364 bool "Architected timer support"
1366 select ARM_ARCH_TIMER
1367 select GENERIC_CLOCKEVENTS
1369 This option enables support for the ARM architected timer
1374 select CLKSRC_OF if OF
1376 This options enables support for the ARM timer and watchdog unit
1379 bool "Multi-Cluster Power Management"
1380 depends on CPU_V7 && SMP
1382 This option provides the common power management infrastructure
1383 for (multi-)cluster based systems, such as big.LITTLE based
1386 config MCPM_QUAD_CLUSTER
1390 To avoid wasting resources unnecessarily, MCPM only supports up
1391 to 2 clusters by default.
1392 Platforms with 3 or 4 clusters that use MCPM must select this
1393 option to allow the additional clusters to be managed.
1396 bool "big.LITTLE support (Experimental)"
1397 depends on CPU_V7 && SMP
1400 This option enables support selections for the big.LITTLE
1401 system architecture.
1404 bool "big.LITTLE switcher support"
1405 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1406 select ARM_CPU_SUSPEND
1409 The big.LITTLE "switcher" provides the core functionality to
1410 transparently handle transition between a cluster of A15's
1411 and a cluster of A7's in a big.LITTLE system.
1413 config BL_SWITCHER_DUMMY_IF
1414 tristate "Simple big.LITTLE switcher user interface"
1415 depends on BL_SWITCHER && DEBUG_KERNEL
1417 This is a simple and dummy char dev interface to control
1418 the big.LITTLE switcher core code. It is meant for
1419 debugging purposes only.
1422 prompt "Memory split"
1426 Select the desired split between kernel and user memory.
1428 If you are not absolutely sure what you are doing, leave this
1432 bool "3G/1G user/kernel split"
1434 bool "2G/2G user/kernel split"
1436 bool "1G/3G user/kernel split"
1441 default PHYS_OFFSET if !MMU
1442 default 0x40000000 if VMSPLIT_1G
1443 default 0x80000000 if VMSPLIT_2G
1447 int "Maximum number of CPUs (2-32)"
1453 bool "Support for hot-pluggable CPUs"
1456 Say Y here to experiment with turning CPUs off and on. CPUs
1457 can be controlled through /sys/devices/system/cpu.
1460 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1463 Say Y here if you want Linux to communicate with system firmware
1464 implementing the PSCI specification for CPU-centric power
1465 management operations described in ARM document number ARM DEN
1466 0022A ("Power State Coordination Interface System Software on
1469 # The GPIO number here must be sorted by descending number. In case of
1470 # a multiplatform kernel, we just want the highest value required by the
1471 # selected platforms.
1474 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA || ARCH_ZYNQ
1475 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1476 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1477 default 416 if ARCH_SUNXI
1478 default 392 if ARCH_U8500
1479 default 352 if ARCH_VT8500
1480 default 288 if ARCH_ROCKCHIP
1481 default 264 if MACH_H4700
1484 Maximum number of GPIOs in the system.
1486 If unsure, leave the default value.
1488 source kernel/Kconfig.preempt
1492 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1493 ARCH_S5PV210 || ARCH_EXYNOS4
1494 default 128 if SOC_AT91RM9200
1495 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1499 depends on HZ_FIXED = 0
1500 prompt "Timer frequency"
1524 default HZ_FIXED if HZ_FIXED != 0
1525 default 100 if HZ_100
1526 default 200 if HZ_200
1527 default 250 if HZ_250
1528 default 300 if HZ_300
1529 default 500 if HZ_500
1533 def_bool HIGH_RES_TIMERS
1535 config THUMB2_KERNEL
1536 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1537 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1538 default y if CPU_THUMBONLY
1540 select ARM_ASM_UNIFIED
1543 By enabling this option, the kernel will be compiled in
1544 Thumb-2 mode. A compiler/assembler that understand the unified
1545 ARM-Thumb syntax is needed.
1549 config THUMB2_AVOID_R_ARM_THM_JUMP11
1550 bool "Work around buggy Thumb-2 short branch relocations in gas"
1551 depends on THUMB2_KERNEL && MODULES
1554 Various binutils versions can resolve Thumb-2 branches to
1555 locally-defined, preemptible global symbols as short-range "b.n"
1556 branch instructions.
1558 This is a problem, because there's no guarantee the final
1559 destination of the symbol, or any candidate locations for a
1560 trampoline, are within range of the branch. For this reason, the
1561 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1562 relocation in modules at all, and it makes little sense to add
1565 The symptom is that the kernel fails with an "unsupported
1566 relocation" error when loading some modules.
1568 Until fixed tools are available, passing
1569 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1570 code which hits this problem, at the cost of a bit of extra runtime
1571 stack usage in some cases.
1573 The problem is described in more detail at:
1574 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1576 Only Thumb-2 kernels are affected.
1578 Unless you are sure your tools don't have this problem, say Y.
1580 config ARM_ASM_UNIFIED
1584 bool "Use the ARM EABI to compile the kernel"
1586 This option allows for the kernel to be compiled using the latest
1587 ARM ABI (aka EABI). This is only useful if you are using a user
1588 space environment that is also compiled with EABI.
1590 Since there are major incompatibilities between the legacy ABI and
1591 EABI, especially with regard to structure member alignment, this
1592 option also changes the kernel syscall calling convention to
1593 disambiguate both ABIs and allow for backward compatibility support
1594 (selected with CONFIG_OABI_COMPAT).
1596 To use this you need GCC version 4.0.0 or later.
1599 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1600 depends on AEABI && !THUMB2_KERNEL
1602 This option preserves the old syscall interface along with the
1603 new (ARM EABI) one. It also provides a compatibility layer to
1604 intercept syscalls that have structure arguments which layout
1605 in memory differs between the legacy ABI and the new ARM EABI
1606 (only for non "thumb" binaries). This option adds a tiny
1607 overhead to all syscalls and produces a slightly larger kernel.
1609 The seccomp filter system will not be available when this is
1610 selected, since there is no way yet to sensibly distinguish
1611 between calling conventions during filtering.
1613 If you know you'll be using only pure EABI user space then you
1614 can say N here. If this option is not selected and you attempt
1615 to execute a legacy ABI binary then the result will be
1616 UNPREDICTABLE (in fact it can be predicted that it won't work
1617 at all). If in doubt say N.
1619 config ARCH_HAS_HOLES_MEMORYMODEL
1622 config ARCH_SPARSEMEM_ENABLE
1625 config ARCH_SPARSEMEM_DEFAULT
1626 def_bool ARCH_SPARSEMEM_ENABLE
1628 config ARCH_SELECT_MEMORY_MODEL
1629 def_bool ARCH_SPARSEMEM_ENABLE
1631 config HAVE_ARCH_PFN_VALID
1632 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1634 config HAVE_GENERIC_RCU_GUP
1639 bool "High Memory Support"
1642 The address space of ARM processors is only 4 Gigabytes large
1643 and it has to accommodate user address space, kernel address
1644 space as well as some memory mapped IO. That means that, if you
1645 have a large amount of physical memory and/or IO, not all of the
1646 memory can be "permanently mapped" by the kernel. The physical
1647 memory that is not permanently mapped is called "high memory".
1649 Depending on the selected kernel/user memory split, minimum
1650 vmalloc space and actual amount of RAM, you may not need this
1651 option which should result in a slightly faster kernel.
1656 bool "Allocate 2nd-level pagetables from highmem"
1659 config HW_PERF_EVENTS
1660 bool "Enable hardware performance counter support for perf events"
1661 depends on PERF_EVENTS
1664 Enable hardware performance counter support for perf events. If
1665 disabled, perf events will use software events only.
1667 config SYS_SUPPORTS_HUGETLBFS
1671 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1675 config ARCH_WANT_GENERAL_HUGETLB
1680 config FORCE_MAX_ZONEORDER
1681 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1682 range 11 64 if ARCH_SHMOBILE_LEGACY
1683 default "12" if SOC_AM33XX
1684 default "9" if SA1111 || ARCH_EFM32
1687 The kernel memory allocator divides physically contiguous memory
1688 blocks into "zones", where each zone is a power of two number of
1689 pages. This option selects the largest power of two that the kernel
1690 keeps in the memory allocator. If you need to allocate very large
1691 blocks of physically contiguous memory, then you may need to
1692 increase this value.
1694 This config option is actually maximum order plus one. For example,
1695 a value of 11 means that the largest free memory block is 2^10 pages.
1697 config ALIGNMENT_TRAP
1699 depends on CPU_CP15_MMU
1700 default y if !ARCH_EBSA110
1701 select HAVE_PROC_CPU if PROC_FS
1703 ARM processors cannot fetch/store information which is not
1704 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1705 address divisible by 4. On 32-bit ARM processors, these non-aligned
1706 fetch/store instructions will be emulated in software if you say
1707 here, which has a severe performance impact. This is necessary for
1708 correct operation of some network protocols. With an IP-only
1709 configuration it is safe to say N, otherwise say Y.
1711 config UACCESS_WITH_MEMCPY
1712 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1714 default y if CPU_FEROCEON
1716 Implement faster copy_to_user and clear_user methods for CPU
1717 cores where a 8-word STM instruction give significantly higher
1718 memory write throughput than a sequence of individual 32bit stores.
1720 A possible side effect is a slight increase in scheduling latency
1721 between threads sharing the same address space if they invoke
1722 such copy operations with large buffers.
1724 However, if the CPU data cache is using a write-allocate mode,
1725 this option is unlikely to provide any performance gain.
1729 prompt "Enable seccomp to safely compute untrusted bytecode"
1731 This kernel feature is useful for number crunching applications
1732 that may need to compute untrusted bytecode during their
1733 execution. By using pipes or other transports made available to
1734 the process as file descriptors supporting the read/write
1735 syscalls, it's possible to isolate those applications in
1736 their own address space using seccomp. Once seccomp is
1737 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1738 and the task is only allowed to execute a few safe syscalls
1739 defined by each seccomp mode.
1752 bool "Xen guest support on ARM"
1753 depends on ARM && AEABI && OF
1754 depends on CPU_V7 && !CPU_V6
1755 depends on !GENERIC_ATOMIC64
1757 select ARCH_DMA_ADDR_T_64BIT
1761 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1768 bool "Flattened Device Tree support"
1771 select OF_EARLY_FLATTREE
1772 select OF_RESERVED_MEM
1774 Include support for flattened device tree machine descriptions.
1777 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1780 This is the traditional way of passing data to the kernel at boot
1781 time. If you are solely relying on the flattened device tree (or
1782 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1783 to remove ATAGS support from your kernel binary. If unsure,
1786 config DEPRECATED_PARAM_STRUCT
1787 bool "Provide old way to pass kernel parameters"
1790 This was deprecated in 2001 and announced to live on for 5 years.
1791 Some old boot loaders still use this way.
1793 # Compressed boot loader in ROM. Yes, we really want to ask about
1794 # TEXT and BSS so we preserve their values in the config files.
1795 config ZBOOT_ROM_TEXT
1796 hex "Compressed ROM boot loader base address"
1799 The physical address at which the ROM-able zImage is to be
1800 placed in the target. Platforms which normally make use of
1801 ROM-able zImage formats normally set this to a suitable
1802 value in their defconfig file.
1804 If ZBOOT_ROM is not enabled, this has no effect.
1806 config ZBOOT_ROM_BSS
1807 hex "Compressed ROM boot loader BSS address"
1810 The base address of an area of read/write memory in the target
1811 for the ROM-able zImage which must be available while the
1812 decompressor is running. It must be large enough to hold the
1813 entire decompressed kernel plus an additional 128 KiB.
1814 Platforms which normally make use of ROM-able zImage formats
1815 normally set this to a suitable value in their defconfig file.
1817 If ZBOOT_ROM is not enabled, this has no effect.
1820 bool "Compressed boot loader in ROM/flash"
1821 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1822 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1824 Say Y here if you intend to execute your compressed kernel image
1825 (zImage) directly from ROM or flash. If unsure, say N.
1827 config ARM_APPENDED_DTB
1828 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1831 With this option, the boot code will look for a device tree binary
1832 (DTB) appended to zImage
1833 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1835 This is meant as a backward compatibility convenience for those
1836 systems with a bootloader that can't be upgraded to accommodate
1837 the documented boot protocol using a device tree.
1839 Beware that there is very little in terms of protection against
1840 this option being confused by leftover garbage in memory that might
1841 look like a DTB header after a reboot if no actual DTB is appended
1842 to zImage. Do not leave this option active in a production kernel
1843 if you don't intend to always append a DTB. Proper passing of the
1844 location into r2 of a bootloader provided DTB is always preferable
1847 config ARM_ATAG_DTB_COMPAT
1848 bool "Supplement the appended DTB with traditional ATAG information"
1849 depends on ARM_APPENDED_DTB
1851 Some old bootloaders can't be updated to a DTB capable one, yet
1852 they provide ATAGs with memory configuration, the ramdisk address,
1853 the kernel cmdline string, etc. Such information is dynamically
1854 provided by the bootloader and can't always be stored in a static
1855 DTB. To allow a device tree enabled kernel to be used with such
1856 bootloaders, this option allows zImage to extract the information
1857 from the ATAG list and store it at run time into the appended DTB.
1860 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1861 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1863 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1864 bool "Use bootloader kernel arguments if available"
1866 Uses the command-line options passed by the boot loader instead of
1867 the device tree bootargs property. If the boot loader doesn't provide
1868 any, the device tree bootargs property will be used.
1870 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1871 bool "Extend with bootloader kernel arguments"
1873 The command-line arguments provided by the boot loader will be
1874 appended to the the device tree bootargs property.
1879 string "Default kernel command string"
1882 On some architectures (EBSA110 and CATS), there is currently no way
1883 for the boot loader to pass arguments to the kernel. For these
1884 architectures, you should supply some command-line options at build
1885 time by entering them here. As a minimum, you should specify the
1886 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1889 prompt "Kernel command line type" if CMDLINE != ""
1890 default CMDLINE_FROM_BOOTLOADER
1893 config CMDLINE_FROM_BOOTLOADER
1894 bool "Use bootloader kernel arguments if available"
1896 Uses the command-line options passed by the boot loader. If
1897 the boot loader doesn't provide any, the default kernel command
1898 string provided in CMDLINE will be used.
1900 config CMDLINE_EXTEND
1901 bool "Extend bootloader kernel arguments"
1903 The command-line arguments provided by the boot loader will be
1904 appended to the default kernel command string.
1906 config CMDLINE_FORCE
1907 bool "Always use the default kernel command string"
1909 Always use the default kernel command string, even if the boot
1910 loader passes other arguments to the kernel.
1911 This is useful if you cannot or don't want to change the
1912 command-line options your boot loader passes to the kernel.
1916 bool "Kernel Execute-In-Place from ROM"
1917 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1919 Execute-In-Place allows the kernel to run from non-volatile storage
1920 directly addressable by the CPU, such as NOR flash. This saves RAM
1921 space since the text section of the kernel is not loaded from flash
1922 to RAM. Read-write sections, such as the data section and stack,
1923 are still copied to RAM. The XIP kernel is not compressed since
1924 it has to run directly from flash, so it will take more space to
1925 store it. The flash address used to link the kernel object files,
1926 and for storing it, is configuration dependent. Therefore, if you
1927 say Y here, you must know the proper physical address where to
1928 store the kernel image depending on your own flash memory usage.
1930 Also note that the make target becomes "make xipImage" rather than
1931 "make zImage" or "make Image". The final kernel binary to put in
1932 ROM memory will be arch/arm/boot/xipImage.
1936 config XIP_PHYS_ADDR
1937 hex "XIP Kernel Physical Location"
1938 depends on XIP_KERNEL
1939 default "0x00080000"
1941 This is the physical address in your flash memory the kernel will
1942 be linked for and stored to. This address is dependent on your
1946 bool "Kexec system call (EXPERIMENTAL)"
1947 depends on (!SMP || PM_SLEEP_SMP)
1949 kexec is a system call that implements the ability to shutdown your
1950 current kernel, and to start another kernel. It is like a reboot
1951 but it is independent of the system firmware. And like a reboot
1952 you can start any kernel with it, not just Linux.
1954 It is an ongoing process to be certain the hardware in a machine
1955 is properly shutdown, so do not be surprised if this code does not
1956 initially work for you.
1959 bool "Export atags in procfs"
1960 depends on ATAGS && KEXEC
1963 Should the atags used to boot the kernel be exported in an "atags"
1964 file in procfs. Useful with kexec.
1967 bool "Build kdump crash kernel (EXPERIMENTAL)"
1969 Generate crash dump after being started by kexec. This should
1970 be normally only set in special crash dump kernels which are
1971 loaded in the main kernel with kexec-tools into a specially
1972 reserved region and then later executed after a crash by
1973 kdump/kexec. The crash dump kernel must be compiled to a
1974 memory address not used by the main kernel
1976 For more details see Documentation/kdump/kdump.txt
1978 config AUTO_ZRELADDR
1979 bool "Auto calculation of the decompressed kernel image address"
1981 ZRELADDR is the physical address where the decompressed kernel
1982 image will be placed. If AUTO_ZRELADDR is selected, the address
1983 will be determined at run-time by masking the current IP with
1984 0xf8000000. This assumes the zImage being placed in the first 128MB
1985 from start of memory.
1989 menu "CPU Power Management"
1991 source "drivers/cpufreq/Kconfig"
1993 source "drivers/cpuidle/Kconfig"
1997 menu "Floating point emulation"
1999 comment "At least one emulation must be selected"
2002 bool "NWFPE math emulation"
2003 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2005 Say Y to include the NWFPE floating point emulator in the kernel.
2006 This is necessary to run most binaries. Linux does not currently
2007 support floating point hardware so you need to say Y here even if
2008 your machine has an FPA or floating point co-processor podule.
2010 You may say N here if you are going to load the Acorn FPEmulator
2011 early in the bootup.
2014 bool "Support extended precision"
2015 depends on FPE_NWFPE
2017 Say Y to include 80-bit support in the kernel floating-point
2018 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2019 Note that gcc does not generate 80-bit operations by default,
2020 so in most cases this option only enlarges the size of the
2021 floating point emulator without any good reason.
2023 You almost surely want to say N here.
2026 bool "FastFPE math emulation (EXPERIMENTAL)"
2027 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2029 Say Y here to include the FAST floating point emulator in the kernel.
2030 This is an experimental much faster emulator which now also has full
2031 precision for the mantissa. It does not support any exceptions.
2032 It is very simple, and approximately 3-6 times faster than NWFPE.
2034 It should be sufficient for most programs. It may be not suitable
2035 for scientific calculations, but you have to check this for yourself.
2036 If you do not feel you need a faster FP emulation you should better
2040 bool "VFP-format floating point maths"
2041 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2043 Say Y to include VFP support code in the kernel. This is needed
2044 if your hardware includes a VFP unit.
2046 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2047 release notes and additional status information.
2049 Say N if your target does not have VFP hardware.
2057 bool "Advanced SIMD (NEON) Extension support"
2058 depends on VFPv3 && CPU_V7
2060 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2063 config KERNEL_MODE_NEON
2064 bool "Support for NEON in kernel mode"
2065 depends on NEON && AEABI
2067 Say Y to include support for NEON in kernel mode.
2071 menu "Userspace binary formats"
2073 source "fs/Kconfig.binfmt"
2076 tristate "RISC OS personality"
2079 Say Y here to include the kernel code necessary if you want to run
2080 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2081 experimental; if this sounds frightening, say N and sleep in peace.
2082 You can also say M here to compile this support as a module (which
2083 will be called arthur).
2087 menu "Power management options"
2089 source "kernel/power/Kconfig"
2091 config ARCH_SUSPEND_POSSIBLE
2092 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2093 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2096 config ARM_CPU_SUSPEND
2099 config ARCH_HIBERNATION_POSSIBLE
2102 default y if ARCH_SUSPEND_POSSIBLE
2106 source "net/Kconfig"
2108 source "drivers/Kconfig"
2110 source "drivers/firmware/Kconfig"
2114 source "arch/arm/Kconfig.debug"
2116 source "security/Kconfig"
2118 source "crypto/Kconfig"
2120 source "lib/Kconfig"
2122 source "arch/arm/kvm/Kconfig"