5 select HAVE_DMA_API_DEBUG
6 select HAVE_IDE if PCI || ISA || PCMCIA
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if !XIP_KERNEL
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
32 select CPU_PM if (SUSPEND || CPU_IDLE)
34 The ARM series is a line of low-power-consumption RISC chip designs
35 licensed by ARM Ltd and targeted at embedded applications and
36 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
37 manufactured, but legacy ARM-based PC hardware remains popular in
38 Europe. There is an ARM Linux project with a web page at
39 <http://www.arm.linux.org.uk/>.
41 config ARM_HAS_SG_CHAIN
50 config SYS_SUPPORTS_APM_EMULATION
53 config HAVE_SCHED_CLOCK
59 config ARCH_USES_GETTIMEOFFSET
63 config GENERIC_CLOCKEVENTS
66 config GENERIC_CLOCKEVENTS_BROADCAST
68 depends on GENERIC_CLOCKEVENTS
77 select GENERIC_ALLOCATOR
88 The Extended Industry Standard Architecture (EISA) bus was
89 developed as an open alternative to the IBM MicroChannel bus.
91 The EISA bus provided some of the features of the IBM MicroChannel
92 bus while maintaining backward compatibility with cards made for
93 the older ISA bus. The EISA bus saw limited use between 1988 and
94 1995 when it was made obsolete by the PCI bus.
96 Say Y here if you are building a kernel for an EISA-based machine.
106 MicroChannel Architecture is found in some IBM PS/2 machines and
107 laptops. It is a bus system similar to PCI or ISA. See
108 <file:Documentation/mca.txt> (and especially the web page given
109 there) before attempting to build an MCA bus kernel.
111 config STACKTRACE_SUPPORT
115 config HAVE_LATENCYTOP_SUPPORT
120 config LOCKDEP_SUPPORT
124 config TRACE_IRQFLAGS_SUPPORT
128 config HARDIRQS_SW_RESEND
132 config GENERIC_IRQ_PROBE
136 config GENERIC_LOCKBREAK
139 depends on SMP && PREEMPT
141 config RWSEM_GENERIC_SPINLOCK
145 config RWSEM_XCHGADD_ALGORITHM
148 config ARCH_HAS_ILOG2_U32
151 config ARCH_HAS_ILOG2_U64
154 config ARCH_HAS_CPUFREQ
157 Internal node to signify that the ARCH has CPUFREQ support
158 and that the relevant menu configurations are displayed for
161 config ARCH_HAS_CPU_IDLE_WAIT
164 config GENERIC_HWEIGHT
168 config GENERIC_CALIBRATE_DELAY
172 config ARCH_MAY_HAVE_PC_FDC
178 config NEED_DMA_MAP_STATE
181 config GENERIC_ISA_DMA
192 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
193 default DRAM_BASE if REMAP_VECTORS_TO_RAM
196 The base address of exception vectors.
198 config ARM_PATCH_PHYS_VIRT
199 bool "Patch physical to virtual translations at runtime" if EMBEDDED
201 depends on !XIP_KERNEL && MMU
202 depends on !ARCH_REALVIEW || !SPARSEMEM
204 Patch phys-to-virt and virt-to-phys translation functions at
205 boot and module load time according to the position of the
206 kernel in system memory.
208 This can only be used with non-XIP MMU kernels where the base
209 of physical memory is at a 16MB boundary.
211 Only disable this option if you know that you do not require
212 this feature (eg, building a kernel for a single machine) and
213 you need to shrink the kernel to the minimal size.
215 config NEED_MACH_MEMORY_H
218 Select this when mach/memory.h is required to provide special
219 definitions for this platform. The need for mach/memory.h should
220 be avoided when possible.
223 hex "Physical address of main memory" if MMU
224 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
225 default DRAM_BASE if !MMU
227 Please provide the physical address corresponding to the
228 location of main memory in your system.
234 source "init/Kconfig"
236 source "kernel/Kconfig.freezer"
241 bool "MMU-based Paged Memory Management Support"
244 Select if you want MMU-based virtualised addressing space
245 support by paged memory management. If unsure, say 'Y'.
248 # The "ARM system type" choice list is ordered alphabetically by option
249 # text. Please add new entries in the option alphabetic order.
252 prompt "ARM system type"
253 default ARCH_VERSATILE
255 config ARCH_INTEGRATOR
256 bool "ARM Ltd. Integrator family"
258 select ARCH_HAS_CPUFREQ
260 select HAVE_MACH_CLKDEV
263 select GENERIC_CLOCKEVENTS
264 select PLAT_VERSATILE
265 select PLAT_VERSATILE_FPGA_IRQ
266 select NEED_MACH_MEMORY_H
268 Support for ARM's Integrator platform.
271 bool "ARM Ltd. RealView family"
274 select HAVE_MACH_CLKDEV
276 select GENERIC_CLOCKEVENTS
277 select ARCH_WANT_OPTIONAL_GPIOLIB
278 select PLAT_VERSATILE
279 select PLAT_VERSATILE_CLCD
280 select ARM_TIMER_SP804
281 select GPIO_PL061 if GPIOLIB
282 select NEED_MACH_MEMORY_H
284 This enables support for ARM Ltd RealView boards.
286 config ARCH_VERSATILE
287 bool "ARM Ltd. Versatile family"
291 select HAVE_MACH_CLKDEV
293 select GENERIC_CLOCKEVENTS
294 select ARCH_WANT_OPTIONAL_GPIOLIB
295 select PLAT_VERSATILE
296 select PLAT_VERSATILE_CLCD
297 select PLAT_VERSATILE_FPGA_IRQ
298 select ARM_TIMER_SP804
300 This enables support for ARM Ltd Versatile board.
303 bool "ARM Ltd. Versatile Express family"
304 select ARCH_WANT_OPTIONAL_GPIOLIB
306 select ARM_TIMER_SP804
308 select HAVE_MACH_CLKDEV
309 select GENERIC_CLOCKEVENTS
311 select HAVE_PATA_PLATFORM
313 select PLAT_VERSATILE
314 select PLAT_VERSATILE_CLCD
316 This enables support for the ARM Ltd Versatile Express boards.
320 select ARCH_REQUIRE_GPIOLIB
324 This enables support for systems based on the Atmel AT91RM9200,
325 AT91SAM9 and AT91CAP9 processors.
328 bool "Broadcom BCMRING"
332 select ARM_TIMER_SP804
334 select GENERIC_CLOCKEVENTS
335 select ARCH_WANT_OPTIONAL_GPIOLIB
337 Support for Broadcom's BCMRing platform.
340 bool "Calxeda Highbank-based"
341 select ARCH_WANT_OPTIONAL_GPIOLIB
344 select ARM_TIMER_SP804
348 select GENERIC_CLOCKEVENTS
353 Support for the Calxeda Highbank SoC based boards.
356 bool "Cirrus Logic CLPS711x/EP721x-based"
358 select ARCH_USES_GETTIMEOFFSET
359 select NEED_MACH_MEMORY_H
361 Support for Cirrus Logic 711x/721x based boards.
364 bool "Cavium Networks CNS3XXX family"
366 select GENERIC_CLOCKEVENTS
368 select MIGHT_HAVE_CACHE_L2X0
369 select MIGHT_HAVE_PCI
370 select PCI_DOMAINS if PCI
372 Support for Cavium Networks CNS3XXX platform.
375 bool "Cortina Systems Gemini"
377 select ARCH_REQUIRE_GPIOLIB
378 select ARCH_USES_GETTIMEOFFSET
380 Support for the Cortina Systems Gemini family SoCs
383 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
386 select GENERIC_CLOCKEVENTS
388 select GENERIC_IRQ_CHIP
389 select MIGHT_HAVE_CACHE_L2X0
393 Support for CSR SiRFSoC ARM Cortex A9 Platform
400 select ARCH_USES_GETTIMEOFFSET
401 select NEED_MACH_MEMORY_H
403 This is an evaluation board for the StrongARM processor available
404 from Digital. It has limited hardware on-board, including an
405 Ethernet interface, two PCMCIA sockets, two serial ports and a
414 select ARCH_REQUIRE_GPIOLIB
415 select ARCH_HAS_HOLES_MEMORYMODEL
416 select ARCH_USES_GETTIMEOFFSET
417 select NEED_MACH_MEMORY_H
419 This enables support for the Cirrus EP93xx series of CPUs.
421 config ARCH_FOOTBRIDGE
425 select GENERIC_CLOCKEVENTS
427 select NEED_MACH_MEMORY_H
429 Support for systems based on the DC21285 companion chip
430 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
433 bool "Freescale MXC/iMX-based"
434 select GENERIC_CLOCKEVENTS
435 select ARCH_REQUIRE_GPIOLIB
438 select GENERIC_IRQ_CHIP
439 select HAVE_SCHED_CLOCK
440 select MULTI_IRQ_HANDLER
442 Support for Freescale MXC/iMX-based family of processors
445 bool "Freescale MXS-based"
446 select GENERIC_CLOCKEVENTS
447 select ARCH_REQUIRE_GPIOLIB
451 Support for Freescale MXS-based family of processors
454 bool "Hilscher NetX based"
458 select GENERIC_CLOCKEVENTS
460 This enables support for systems based on the Hilscher NetX Soc
463 bool "Hynix HMS720x-based"
466 select ARCH_USES_GETTIMEOFFSET
468 This enables support for systems based on the Hynix HMS720x
476 select ARCH_SUPPORTS_MSI
478 select NEED_MACH_MEMORY_H
480 Support for Intel's IOP13XX (XScale) family of processors.
488 select ARCH_REQUIRE_GPIOLIB
490 Support for Intel's 80219 and IOP32X (XScale) family of
499 select ARCH_REQUIRE_GPIOLIB
501 Support for Intel's IOP33X (XScale) family of processors.
508 select ARCH_USES_GETTIMEOFFSET
509 select NEED_MACH_MEMORY_H
511 Support for Intel's IXP23xx (XScale) family of processors.
514 bool "IXP2400/2800-based"
518 select ARCH_USES_GETTIMEOFFSET
519 select NEED_MACH_MEMORY_H
521 Support for Intel's IXP2400/2800 (XScale) family of processors.
529 select GENERIC_CLOCKEVENTS
530 select HAVE_SCHED_CLOCK
531 select MIGHT_HAVE_PCI
532 select DMABOUNCE if PCI
534 Support for Intel's IXP4XX (XScale) family of processors.
540 select ARCH_REQUIRE_GPIOLIB
541 select GENERIC_CLOCKEVENTS
544 Support for the Marvell Dove SoC 88AP510
547 bool "Marvell Kirkwood"
550 select ARCH_REQUIRE_GPIOLIB
551 select GENERIC_CLOCKEVENTS
554 Support for the following Marvell Kirkwood series SoCs:
555 88F6180, 88F6192 and 88F6281.
561 select ARCH_REQUIRE_GPIOLIB
564 select USB_ARCH_HAS_OHCI
566 select GENERIC_CLOCKEVENTS
568 Support for the NXP LPC32XX family of processors
571 bool "Marvell MV78xx0"
574 select ARCH_REQUIRE_GPIOLIB
575 select GENERIC_CLOCKEVENTS
578 Support for the following Marvell MV78xx0 series SoCs:
586 select ARCH_REQUIRE_GPIOLIB
587 select GENERIC_CLOCKEVENTS
590 Support for the following Marvell Orion 5x series SoCs:
591 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
592 Orion-2 (5281), Orion-1-90 (6183).
595 bool "Marvell PXA168/910/MMP2"
597 select ARCH_REQUIRE_GPIOLIB
599 select GENERIC_CLOCKEVENTS
601 select HAVE_SCHED_CLOCK
605 select GENERIC_ALLOCATOR
607 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
610 bool "Micrel/Kendin KS8695"
612 select ARCH_REQUIRE_GPIOLIB
613 select ARCH_USES_GETTIMEOFFSET
614 select NEED_MACH_MEMORY_H
616 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
617 System-on-Chip devices.
620 bool "Nuvoton W90X900 CPU"
622 select ARCH_REQUIRE_GPIOLIB
625 select GENERIC_CLOCKEVENTS
627 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
628 At present, the w90x900 has been renamed nuc900, regarding
629 the ARM series product line, you can login the following
630 link address to know more.
632 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
633 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
639 select GENERIC_CLOCKEVENTS
642 select HAVE_SCHED_CLOCK
644 select MIGHT_HAVE_CACHE_L2X0
645 select ARCH_HAS_CPUFREQ
647 This enables support for NVIDIA Tegra based systems (Tegra APX,
648 Tegra 6xx and Tegra 2 series).
650 config ARCH_PICOXCELL
651 bool "Picochip picoXcell"
652 select ARCH_REQUIRE_GPIOLIB
653 select ARM_PATCH_PHYS_VIRT
657 select GENERIC_CLOCKEVENTS
659 select HAVE_SCHED_CLOCK
665 This enables support for systems based on the Picochip picoXcell
666 family of Femtocell devices. The picoxcell support requires device tree
670 bool "Philips Nexperia PNX4008 Mobile"
673 select ARCH_USES_GETTIMEOFFSET
675 This enables support for Philips PNX4008 mobile platform.
678 bool "PXA2xx/PXA3xx-based"
681 select ARCH_HAS_CPUFREQ
684 select ARCH_REQUIRE_GPIOLIB
685 select GENERIC_CLOCKEVENTS
687 select HAVE_SCHED_CLOCK
692 select MULTI_IRQ_HANDLER
693 select ARM_CPU_SUSPEND if PM
696 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
701 select GENERIC_CLOCKEVENTS
702 select ARCH_REQUIRE_GPIOLIB
705 Support for Qualcomm MSM/QSD based systems. This runs on the
706 apps processor of the MSM/QSD and depends on a shared memory
707 interface to the modem processor which runs the baseband
708 stack and controls some vital subsystems
709 (clock and power control, etc).
712 bool "Renesas SH-Mobile / R-Mobile"
715 select HAVE_MACH_CLKDEV
717 select GENERIC_CLOCKEVENTS
718 select MIGHT_HAVE_CACHE_L2X0
721 select MULTI_IRQ_HANDLER
722 select PM_GENERIC_DOMAINS if PM
723 select NEED_MACH_MEMORY_H
725 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
732 select ARCH_MAY_HAVE_PC_FDC
733 select HAVE_PATA_PLATFORM
736 select ARCH_SPARSEMEM_ENABLE
737 select ARCH_USES_GETTIMEOFFSET
739 select NEED_MACH_MEMORY_H
741 On the Acorn Risc-PC, Linux can support the internal IDE disk and
742 CD-ROM interface, serial and parallel port, and the floppy drive.
749 select ARCH_SPARSEMEM_ENABLE
751 select ARCH_HAS_CPUFREQ
753 select GENERIC_CLOCKEVENTS
755 select HAVE_SCHED_CLOCK
757 select ARCH_REQUIRE_GPIOLIB
759 select NEED_MACH_MEMORY_H
761 Support for StrongARM 11x0 based boards.
764 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
766 select ARCH_HAS_CPUFREQ
769 select ARCH_USES_GETTIMEOFFSET
770 select HAVE_S3C2410_I2C if I2C
772 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
773 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
774 the Samsung SMDK2410 development board (and derivatives).
776 Note, the S3C2416 and the S3C2450 are so close that they even share
777 the same SoC ID code. This means that there is no separate machine
778 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
781 bool "Samsung S3C64XX"
789 select ARCH_USES_GETTIMEOFFSET
790 select ARCH_HAS_CPUFREQ
791 select ARCH_REQUIRE_GPIOLIB
792 select SAMSUNG_CLKSRC
793 select SAMSUNG_IRQ_VIC_TIMER
794 select S3C_GPIO_TRACK
796 select USB_ARCH_HAS_OHCI
797 select SAMSUNG_GPIOLIB_4BIT
798 select HAVE_S3C2410_I2C if I2C
799 select HAVE_S3C2410_WATCHDOG if WATCHDOG
801 Samsung S3C64XX series based systems
804 bool "Samsung S5P6440 S5P6450"
810 select HAVE_S3C2410_WATCHDOG if WATCHDOG
811 select GENERIC_CLOCKEVENTS
812 select HAVE_SCHED_CLOCK
813 select HAVE_S3C2410_I2C if I2C
814 select HAVE_S3C_RTC if RTC_CLASS
816 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
820 bool "Samsung S5PC100"
825 select ARM_L1_CACHE_SHIFT_6
826 select ARCH_USES_GETTIMEOFFSET
827 select HAVE_S3C2410_I2C if I2C
828 select HAVE_S3C_RTC if RTC_CLASS
829 select HAVE_S3C2410_WATCHDOG if WATCHDOG
831 Samsung S5PC100 series based systems
834 bool "Samsung S5PV210/S5PC110"
836 select ARCH_SPARSEMEM_ENABLE
837 select ARCH_HAS_HOLES_MEMORYMODEL
842 select ARM_L1_CACHE_SHIFT_6
843 select ARCH_HAS_CPUFREQ
844 select GENERIC_CLOCKEVENTS
845 select HAVE_SCHED_CLOCK
846 select HAVE_S3C2410_I2C if I2C
847 select HAVE_S3C_RTC if RTC_CLASS
848 select HAVE_S3C2410_WATCHDOG if WATCHDOG
849 select NEED_MACH_MEMORY_H
851 Samsung S5PV210/S5PC110 series based systems
854 bool "SAMSUNG EXYNOS"
856 select ARCH_SPARSEMEM_ENABLE
857 select ARCH_HAS_HOLES_MEMORYMODEL
861 select ARCH_HAS_CPUFREQ
862 select GENERIC_CLOCKEVENTS
863 select HAVE_S3C_RTC if RTC_CLASS
864 select HAVE_S3C2410_I2C if I2C
865 select HAVE_S3C2410_WATCHDOG if WATCHDOG
866 select NEED_MACH_MEMORY_H
868 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
877 select ARCH_USES_GETTIMEOFFSET
878 select NEED_MACH_MEMORY_H
880 Support for the StrongARM based Digital DNARD machine, also known
881 as "Shark" (<http://www.shark-linux.de/shark.html>).
884 bool "ST-Ericsson U300 Series"
888 select HAVE_SCHED_CLOCK
891 select ARM_PATCH_PHYS_VIRT
893 select GENERIC_CLOCKEVENTS
895 select HAVE_MACH_CLKDEV
897 select ARCH_REQUIRE_GPIOLIB
899 Support for ST-Ericsson U300 series mobile platforms.
902 bool "ST-Ericsson U8500 Series"
905 select GENERIC_CLOCKEVENTS
907 select ARCH_REQUIRE_GPIOLIB
908 select ARCH_HAS_CPUFREQ
910 select MIGHT_HAVE_CACHE_L2X0
912 Support for ST-Ericsson's Ux500 architecture
915 bool "STMicroelectronics Nomadik"
920 select GENERIC_CLOCKEVENTS
921 select MIGHT_HAVE_CACHE_L2X0
922 select ARCH_REQUIRE_GPIOLIB
924 Support for the Nomadik platform by ST-Ericsson
928 select GENERIC_CLOCKEVENTS
929 select ARCH_REQUIRE_GPIOLIB
933 select GENERIC_ALLOCATOR
934 select GENERIC_IRQ_CHIP
935 select ARCH_HAS_HOLES_MEMORYMODEL
937 Support for TI's DaVinci platform.
942 select ARCH_REQUIRE_GPIOLIB
943 select ARCH_HAS_CPUFREQ
945 select GENERIC_CLOCKEVENTS
946 select HAVE_SCHED_CLOCK
947 select ARCH_HAS_HOLES_MEMORYMODEL
949 Support for TI's OMAP platform (OMAP1/2/3/4).
954 select ARCH_REQUIRE_GPIOLIB
957 select GENERIC_CLOCKEVENTS
960 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
963 bool "VIA/WonderMedia 85xx"
966 select ARCH_HAS_CPUFREQ
967 select GENERIC_CLOCKEVENTS
968 select ARCH_REQUIRE_GPIOLIB
971 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
974 bool "Xilinx Zynq ARM Cortex A9 Platform"
976 select GENERIC_CLOCKEVENTS
981 select MIGHT_HAVE_CACHE_L2X0
984 Support for Xilinx Zynq ARM Cortex A9 Platform
988 # This is sorted alphabetically by mach-* pathname. However, plat-*
989 # Kconfigs may be included either alphabetically (according to the
990 # plat- suffix) or along side the corresponding mach-* source.
992 source "arch/arm/mach-at91/Kconfig"
994 source "arch/arm/mach-bcmring/Kconfig"
996 source "arch/arm/mach-clps711x/Kconfig"
998 source "arch/arm/mach-cns3xxx/Kconfig"
1000 source "arch/arm/mach-davinci/Kconfig"
1002 source "arch/arm/mach-dove/Kconfig"
1004 source "arch/arm/mach-ep93xx/Kconfig"
1006 source "arch/arm/mach-footbridge/Kconfig"
1008 source "arch/arm/mach-gemini/Kconfig"
1010 source "arch/arm/mach-h720x/Kconfig"
1012 source "arch/arm/mach-integrator/Kconfig"
1014 source "arch/arm/mach-iop32x/Kconfig"
1016 source "arch/arm/mach-iop33x/Kconfig"
1018 source "arch/arm/mach-iop13xx/Kconfig"
1020 source "arch/arm/mach-ixp4xx/Kconfig"
1022 source "arch/arm/mach-ixp2000/Kconfig"
1024 source "arch/arm/mach-ixp23xx/Kconfig"
1026 source "arch/arm/mach-kirkwood/Kconfig"
1028 source "arch/arm/mach-ks8695/Kconfig"
1030 source "arch/arm/mach-lpc32xx/Kconfig"
1032 source "arch/arm/mach-msm/Kconfig"
1034 source "arch/arm/mach-mv78xx0/Kconfig"
1036 source "arch/arm/plat-mxc/Kconfig"
1038 source "arch/arm/mach-mxs/Kconfig"
1040 source "arch/arm/mach-netx/Kconfig"
1042 source "arch/arm/mach-nomadik/Kconfig"
1043 source "arch/arm/plat-nomadik/Kconfig"
1045 source "arch/arm/plat-omap/Kconfig"
1047 source "arch/arm/mach-omap1/Kconfig"
1049 source "arch/arm/mach-omap2/Kconfig"
1051 source "arch/arm/mach-orion5x/Kconfig"
1053 source "arch/arm/mach-pxa/Kconfig"
1054 source "arch/arm/plat-pxa/Kconfig"
1056 source "arch/arm/mach-mmp/Kconfig"
1058 source "arch/arm/mach-realview/Kconfig"
1060 source "arch/arm/mach-sa1100/Kconfig"
1062 source "arch/arm/plat-samsung/Kconfig"
1063 source "arch/arm/plat-s3c24xx/Kconfig"
1064 source "arch/arm/plat-s5p/Kconfig"
1066 source "arch/arm/plat-spear/Kconfig"
1069 source "arch/arm/mach-s3c2410/Kconfig"
1070 source "arch/arm/mach-s3c2412/Kconfig"
1071 source "arch/arm/mach-s3c2416/Kconfig"
1072 source "arch/arm/mach-s3c2440/Kconfig"
1073 source "arch/arm/mach-s3c2443/Kconfig"
1077 source "arch/arm/mach-s3c64xx/Kconfig"
1080 source "arch/arm/mach-s5p64x0/Kconfig"
1082 source "arch/arm/mach-s5pc100/Kconfig"
1084 source "arch/arm/mach-s5pv210/Kconfig"
1086 source "arch/arm/mach-exynos/Kconfig"
1088 source "arch/arm/mach-shmobile/Kconfig"
1090 source "arch/arm/mach-tegra/Kconfig"
1092 source "arch/arm/mach-u300/Kconfig"
1094 source "arch/arm/mach-ux500/Kconfig"
1096 source "arch/arm/mach-versatile/Kconfig"
1098 source "arch/arm/mach-vexpress/Kconfig"
1099 source "arch/arm/plat-versatile/Kconfig"
1101 source "arch/arm/mach-vt8500/Kconfig"
1103 source "arch/arm/mach-w90x900/Kconfig"
1105 # Definitions to make life easier
1111 select GENERIC_CLOCKEVENTS
1112 select HAVE_SCHED_CLOCK
1117 select GENERIC_IRQ_CHIP
1118 select HAVE_SCHED_CLOCK
1123 config PLAT_VERSATILE
1126 config ARM_TIMER_SP804
1130 source arch/arm/mm/Kconfig
1134 default 16 if ARCH_EP93XX
1138 bool "Enable iWMMXt support"
1139 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1140 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1142 Enable support for iWMMXt context switching at run time if
1143 running on a CPU that supports it.
1145 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1148 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1152 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1153 (!ARCH_OMAP3 || OMAP3_EMU)
1157 config MULTI_IRQ_HANDLER
1160 Allow each machine to specify it's own IRQ handler at run time.
1163 source "arch/arm/Kconfig-nommu"
1166 config ARM_ERRATA_411920
1167 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1168 depends on CPU_V6 || CPU_V6K
1170 Invalidation of the Instruction Cache operation can
1171 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1172 It does not affect the MPCore. This option enables the ARM Ltd.
1173 recommended workaround.
1175 config ARM_ERRATA_430973
1176 bool "ARM errata: Stale prediction on replaced interworking branch"
1179 This option enables the workaround for the 430973 Cortex-A8
1180 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1181 interworking branch is replaced with another code sequence at the
1182 same virtual address, whether due to self-modifying code or virtual
1183 to physical address re-mapping, Cortex-A8 does not recover from the
1184 stale interworking branch prediction. This results in Cortex-A8
1185 executing the new code sequence in the incorrect ARM or Thumb state.
1186 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1187 and also flushes the branch target cache at every context switch.
1188 Note that setting specific bits in the ACTLR register may not be
1189 available in non-secure mode.
1191 config ARM_ERRATA_458693
1192 bool "ARM errata: Processor deadlock when a false hazard is created"
1195 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1196 erratum. For very specific sequences of memory operations, it is
1197 possible for a hazard condition intended for a cache line to instead
1198 be incorrectly associated with a different cache line. This false
1199 hazard might then cause a processor deadlock. The workaround enables
1200 the L1 caching of the NEON accesses and disables the PLD instruction
1201 in the ACTLR register. Note that setting specific bits in the ACTLR
1202 register may not be available in non-secure mode.
1204 config ARM_ERRATA_460075
1205 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1208 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1209 erratum. Any asynchronous access to the L2 cache may encounter a
1210 situation in which recent store transactions to the L2 cache are lost
1211 and overwritten with stale memory contents from external memory. The
1212 workaround disables the write-allocate mode for the L2 cache via the
1213 ACTLR register. Note that setting specific bits in the ACTLR register
1214 may not be available in non-secure mode.
1216 config ARM_ERRATA_742230
1217 bool "ARM errata: DMB operation may be faulty"
1218 depends on CPU_V7 && SMP
1220 This option enables the workaround for the 742230 Cortex-A9
1221 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1222 between two write operations may not ensure the correct visibility
1223 ordering of the two writes. This workaround sets a specific bit in
1224 the diagnostic register of the Cortex-A9 which causes the DMB
1225 instruction to behave as a DSB, ensuring the correct behaviour of
1228 config ARM_ERRATA_742231
1229 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1230 depends on CPU_V7 && SMP
1232 This option enables the workaround for the 742231 Cortex-A9
1233 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1234 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1235 accessing some data located in the same cache line, may get corrupted
1236 data due to bad handling of the address hazard when the line gets
1237 replaced from one of the CPUs at the same time as another CPU is
1238 accessing it. This workaround sets specific bits in the diagnostic
1239 register of the Cortex-A9 which reduces the linefill issuing
1240 capabilities of the processor.
1242 config PL310_ERRATA_588369
1243 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1244 depends on CACHE_L2X0
1246 The PL310 L2 cache controller implements three types of Clean &
1247 Invalidate maintenance operations: by Physical Address
1248 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1249 They are architecturally defined to behave as the execution of a
1250 clean operation followed immediately by an invalidate operation,
1251 both performing to the same memory location. This functionality
1252 is not correctly implemented in PL310 as clean lines are not
1253 invalidated as a result of these operations.
1255 config ARM_ERRATA_720789
1256 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1259 This option enables the workaround for the 720789 Cortex-A9 (prior to
1260 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1261 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1262 As a consequence of this erratum, some TLB entries which should be
1263 invalidated are not, resulting in an incoherency in the system page
1264 tables. The workaround changes the TLB flushing routines to invalidate
1265 entries regardless of the ASID.
1267 config PL310_ERRATA_727915
1268 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1269 depends on CACHE_L2X0
1271 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1272 operation (offset 0x7FC). This operation runs in background so that
1273 PL310 can handle normal accesses while it is in progress. Under very
1274 rare circumstances, due to this erratum, write data can be lost when
1275 PL310 treats a cacheable write transaction during a Clean &
1276 Invalidate by Way operation.
1278 config ARM_ERRATA_743622
1279 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1282 This option enables the workaround for the 743622 Cortex-A9
1283 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1284 optimisation in the Cortex-A9 Store Buffer may lead to data
1285 corruption. This workaround sets a specific bit in the diagnostic
1286 register of the Cortex-A9 which disables the Store Buffer
1287 optimisation, preventing the defect from occurring. This has no
1288 visible impact on the overall performance or power consumption of the
1291 config ARM_ERRATA_751472
1292 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1295 This option enables the workaround for the 751472 Cortex-A9 (prior
1296 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1297 completion of a following broadcasted operation if the second
1298 operation is received by a CPU before the ICIALLUIS has completed,
1299 potentially leading to corrupted entries in the cache or TLB.
1301 config PL310_ERRATA_753970
1302 bool "PL310 errata: cache sync operation may be faulty"
1303 depends on CACHE_PL310
1305 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1307 Under some condition the effect of cache sync operation on
1308 the store buffer still remains when the operation completes.
1309 This means that the store buffer is always asked to drain and
1310 this prevents it from merging any further writes. The workaround
1311 is to replace the normal offset of cache sync operation (0x730)
1312 by another offset targeting an unmapped PL310 register 0x740.
1313 This has the same effect as the cache sync operation: store buffer
1314 drain and waiting for all buffers empty.
1316 config ARM_ERRATA_754322
1317 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1320 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1321 r3p*) erratum. A speculative memory access may cause a page table walk
1322 which starts prior to an ASID switch but completes afterwards. This
1323 can populate the micro-TLB with a stale entry which may be hit with
1324 the new ASID. This workaround places two dsb instructions in the mm
1325 switching code so that no page table walks can cross the ASID switch.
1327 config ARM_ERRATA_754327
1328 bool "ARM errata: no automatic Store Buffer drain"
1329 depends on CPU_V7 && SMP
1331 This option enables the workaround for the 754327 Cortex-A9 (prior to
1332 r2p0) erratum. The Store Buffer does not have any automatic draining
1333 mechanism and therefore a livelock may occur if an external agent
1334 continuously polls a memory location waiting to observe an update.
1335 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1336 written polling loops from denying visibility of updates to memory.
1338 config ARM_ERRATA_364296
1339 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1340 depends on CPU_V6 && !SMP
1342 This options enables the workaround for the 364296 ARM1136
1343 r0p2 erratum (possible cache data corruption with
1344 hit-under-miss enabled). It sets the undocumented bit 31 in
1345 the auxiliary control register and the FI bit in the control
1346 register, thus disabling hit-under-miss without putting the
1347 processor into full low interrupt latency mode. ARM11MPCore
1350 config ARM_ERRATA_764369
1351 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1352 depends on CPU_V7 && SMP
1354 This option enables the workaround for erratum 764369
1355 affecting Cortex-A9 MPCore with two or more processors (all
1356 current revisions). Under certain timing circumstances, a data
1357 cache line maintenance operation by MVA targeting an Inner
1358 Shareable memory region may fail to proceed up to either the
1359 Point of Coherency or to the Point of Unification of the
1360 system. This workaround adds a DSB instruction before the
1361 relevant cache maintenance functions and sets a specific bit
1362 in the diagnostic control register of the SCU.
1364 config PL310_ERRATA_769419
1365 bool "PL310 errata: no automatic Store Buffer drain"
1366 depends on CACHE_L2X0
1368 On revisions of the PL310 prior to r3p2, the Store Buffer does
1369 not automatically drain. This can cause normal, non-cacheable
1370 writes to be retained when the memory system is idle, leading
1371 to suboptimal I/O performance for drivers using coherent DMA.
1372 This option adds a write barrier to the cpu_idle loop so that,
1373 on systems with an outer cache, the store buffer is drained
1378 source "arch/arm/common/Kconfig"
1388 Find out whether you have ISA slots on your motherboard. ISA is the
1389 name of a bus system, i.e. the way the CPU talks to the other stuff
1390 inside your box. Other bus systems are PCI, EISA, MicroChannel
1391 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1392 newer boards don't support it. If you have ISA, say Y, otherwise N.
1394 # Select ISA DMA controller support
1399 # Select ISA DMA interface
1404 bool "PCI support" if MIGHT_HAVE_PCI
1406 Find out whether you have a PCI motherboard. PCI is the name of a
1407 bus system, i.e. the way the CPU talks to the other stuff inside
1408 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1409 VESA. If you have PCI, say Y, otherwise N.
1415 config PCI_NANOENGINE
1416 bool "BSE nanoEngine PCI support"
1417 depends on SA1100_NANOENGINE
1419 Enable PCI on the BSE nanoEngine board.
1424 # Select the host bridge type
1425 config PCI_HOST_VIA82C505
1427 depends on PCI && ARCH_SHARK
1430 config PCI_HOST_ITE8152
1432 depends on PCI && MACH_ARMCORE
1436 source "drivers/pci/Kconfig"
1438 source "drivers/pcmcia/Kconfig"
1442 menu "Kernel Features"
1444 source "kernel/time/Kconfig"
1449 This option should be selected by machines which have an SMP-
1452 The only effect of this option is to make the SMP-related
1453 options available to the user for configuration.
1456 bool "Symmetric Multi-Processing"
1457 depends on CPU_V6K || CPU_V7
1458 depends on GENERIC_CLOCKEVENTS
1461 select USE_GENERIC_SMP_HELPERS
1462 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1464 This enables support for systems with more than one CPU. If you have
1465 a system with only one CPU, like most personal computers, say N. If
1466 you have a system with more than one CPU, say Y.
1468 If you say N here, the kernel will run on single and multiprocessor
1469 machines, but will use only one CPU of a multiprocessor machine. If
1470 you say Y here, the kernel will run on many, but not all, single
1471 processor machines. On a single processor machine, the kernel will
1472 run faster if you say N here.
1474 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1475 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1476 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1478 If you don't know what to do here, say N.
1481 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1482 depends on EXPERIMENTAL
1483 depends on SMP && !XIP_KERNEL
1486 SMP kernels contain instructions which fail on non-SMP processors.
1487 Enabling this option allows the kernel to modify itself to make
1488 these instructions safe. Disabling it allows about 1K of space
1491 If you don't know what to do here, say Y.
1493 config ARM_CPU_TOPOLOGY
1494 bool "Support cpu topology definition"
1495 depends on SMP && CPU_V7
1498 Support ARM cpu topology definition. The MPIDR register defines
1499 affinity between processors which is then used to describe the cpu
1500 topology of an ARM System.
1503 bool "Multi-core scheduler support"
1504 depends on ARM_CPU_TOPOLOGY
1506 Multi-core scheduler support improves the CPU scheduler's decision
1507 making when dealing with multi-core CPU chips at a cost of slightly
1508 increased overhead in some places. If unsure say N here.
1511 bool "SMT scheduler support"
1512 depends on ARM_CPU_TOPOLOGY
1514 Improves the CPU scheduler's decision making when dealing with
1515 MultiThreading at a cost of slightly increased overhead in some
1516 places. If unsure say N here.
1521 This option enables support for the ARM system coherency unit
1528 This options enables support for the ARM timer and watchdog unit
1531 prompt "Memory split"
1534 Select the desired split between kernel and user memory.
1536 If you are not absolutely sure what you are doing, leave this
1540 bool "3G/1G user/kernel split"
1542 bool "2G/2G user/kernel split"
1544 bool "1G/3G user/kernel split"
1549 default 0x40000000 if VMSPLIT_1G
1550 default 0x80000000 if VMSPLIT_2G
1554 int "Maximum number of CPUs (2-32)"
1560 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1561 depends on SMP && HOTPLUG && EXPERIMENTAL
1563 Say Y here to experiment with turning CPUs off and on. CPUs
1564 can be controlled through /sys/devices/system/cpu.
1567 bool "Use local timer interrupts"
1570 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1572 Enable support for local timers on SMP platforms, rather then the
1573 legacy IPI broadcast method. Local timers allows the system
1574 accounting to be spread across the timer interval, preventing a
1575 "thundering herd" at every timer tick.
1579 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1580 default 350 if ARCH_U8500
1583 Maximum number of GPIOs in the system.
1585 If unsure, leave the default value.
1587 source kernel/Kconfig.preempt
1591 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1592 ARCH_S5PV210 || ARCH_EXYNOS4
1593 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1594 default AT91_TIMER_HZ if ARCH_AT91
1595 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1598 config THUMB2_KERNEL
1599 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1600 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1602 select ARM_ASM_UNIFIED
1605 By enabling this option, the kernel will be compiled in
1606 Thumb-2 mode. A compiler/assembler that understand the unified
1607 ARM-Thumb syntax is needed.
1611 config THUMB2_AVOID_R_ARM_THM_JUMP11
1612 bool "Work around buggy Thumb-2 short branch relocations in gas"
1613 depends on THUMB2_KERNEL && MODULES
1616 Various binutils versions can resolve Thumb-2 branches to
1617 locally-defined, preemptible global symbols as short-range "b.n"
1618 branch instructions.
1620 This is a problem, because there's no guarantee the final
1621 destination of the symbol, or any candidate locations for a
1622 trampoline, are within range of the branch. For this reason, the
1623 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1624 relocation in modules at all, and it makes little sense to add
1627 The symptom is that the kernel fails with an "unsupported
1628 relocation" error when loading some modules.
1630 Until fixed tools are available, passing
1631 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1632 code which hits this problem, at the cost of a bit of extra runtime
1633 stack usage in some cases.
1635 The problem is described in more detail at:
1636 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1638 Only Thumb-2 kernels are affected.
1640 Unless you are sure your tools don't have this problem, say Y.
1642 config ARM_ASM_UNIFIED
1646 bool "Use the ARM EABI to compile the kernel"
1648 This option allows for the kernel to be compiled using the latest
1649 ARM ABI (aka EABI). This is only useful if you are using a user
1650 space environment that is also compiled with EABI.
1652 Since there are major incompatibilities between the legacy ABI and
1653 EABI, especially with regard to structure member alignment, this
1654 option also changes the kernel syscall calling convention to
1655 disambiguate both ABIs and allow for backward compatibility support
1656 (selected with CONFIG_OABI_COMPAT).
1658 To use this you need GCC version 4.0.0 or later.
1661 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1662 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1665 This option preserves the old syscall interface along with the
1666 new (ARM EABI) one. It also provides a compatibility layer to
1667 intercept syscalls that have structure arguments which layout
1668 in memory differs between the legacy ABI and the new ARM EABI
1669 (only for non "thumb" binaries). This option adds a tiny
1670 overhead to all syscalls and produces a slightly larger kernel.
1671 If you know you'll be using only pure EABI user space then you
1672 can say N here. If this option is not selected and you attempt
1673 to execute a legacy ABI binary then the result will be
1674 UNPREDICTABLE (in fact it can be predicted that it won't work
1675 at all). If in doubt say Y.
1677 config ARCH_HAS_HOLES_MEMORYMODEL
1680 config ARCH_SPARSEMEM_ENABLE
1683 config ARCH_SPARSEMEM_DEFAULT
1684 def_bool ARCH_SPARSEMEM_ENABLE
1686 config ARCH_SELECT_MEMORY_MODEL
1687 def_bool ARCH_SPARSEMEM_ENABLE
1689 config HAVE_ARCH_PFN_VALID
1690 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1693 bool "High Memory Support"
1696 The address space of ARM processors is only 4 Gigabytes large
1697 and it has to accommodate user address space, kernel address
1698 space as well as some memory mapped IO. That means that, if you
1699 have a large amount of physical memory and/or IO, not all of the
1700 memory can be "permanently mapped" by the kernel. The physical
1701 memory that is not permanently mapped is called "high memory".
1703 Depending on the selected kernel/user memory split, minimum
1704 vmalloc space and actual amount of RAM, you may not need this
1705 option which should result in a slightly faster kernel.
1710 bool "Allocate 2nd-level pagetables from highmem"
1713 config HW_PERF_EVENTS
1714 bool "Enable hardware performance counter support for perf events"
1715 depends on PERF_EVENTS && CPU_HAS_PMU
1718 Enable hardware performance counter support for perf events. If
1719 disabled, perf events will use software events only.
1723 config FORCE_MAX_ZONEORDER
1724 int "Maximum zone order" if ARCH_SHMOBILE
1725 range 11 64 if ARCH_SHMOBILE
1726 default "9" if SA1111
1729 The kernel memory allocator divides physically contiguous memory
1730 blocks into "zones", where each zone is a power of two number of
1731 pages. This option selects the largest power of two that the kernel
1732 keeps in the memory allocator. If you need to allocate very large
1733 blocks of physically contiguous memory, then you may need to
1734 increase this value.
1736 This config option is actually maximum order plus one. For example,
1737 a value of 11 means that the largest free memory block is 2^10 pages.
1740 bool "Timer and CPU usage LEDs"
1741 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1742 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1743 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1744 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1745 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1746 ARCH_AT91 || ARCH_DAVINCI || \
1747 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1749 If you say Y here, the LEDs on your machine will be used
1750 to provide useful information about your current system status.
1752 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1753 be able to select which LEDs are active using the options below. If
1754 you are compiling a kernel for the EBSA-110 or the LART however, the
1755 red LED will simply flash regularly to indicate that the system is
1756 still functional. It is safe to say Y here if you have a CATS
1757 system, but the driver will do nothing.
1760 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1761 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1762 || MACH_OMAP_PERSEUS2
1764 depends on !GENERIC_CLOCKEVENTS
1765 default y if ARCH_EBSA110
1767 If you say Y here, one of the system LEDs (the green one on the
1768 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1769 will flash regularly to indicate that the system is still
1770 operational. This is mainly useful to kernel hackers who are
1771 debugging unstable kernels.
1773 The LART uses the same LED for both Timer LED and CPU usage LED
1774 functions. You may choose to use both, but the Timer LED function
1775 will overrule the CPU usage LED.
1778 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1780 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1781 || MACH_OMAP_PERSEUS2
1784 If you say Y here, the red LED will be used to give a good real
1785 time indication of CPU usage, by lighting whenever the idle task
1786 is not currently executing.
1788 The LART uses the same LED for both Timer LED and CPU usage LED
1789 functions. You may choose to use both, but the Timer LED function
1790 will overrule the CPU usage LED.
1792 config ALIGNMENT_TRAP
1794 depends on CPU_CP15_MMU
1795 default y if !ARCH_EBSA110
1796 select HAVE_PROC_CPU if PROC_FS
1798 ARM processors cannot fetch/store information which is not
1799 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1800 address divisible by 4. On 32-bit ARM processors, these non-aligned
1801 fetch/store instructions will be emulated in software if you say
1802 here, which has a severe performance impact. This is necessary for
1803 correct operation of some network protocols. With an IP-only
1804 configuration it is safe to say N, otherwise say Y.
1806 config UACCESS_WITH_MEMCPY
1807 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1808 depends on MMU && EXPERIMENTAL
1809 default y if CPU_FEROCEON
1811 Implement faster copy_to_user and clear_user methods for CPU
1812 cores where a 8-word STM instruction give significantly higher
1813 memory write throughput than a sequence of individual 32bit stores.
1815 A possible side effect is a slight increase in scheduling latency
1816 between threads sharing the same address space if they invoke
1817 such copy operations with large buffers.
1819 However, if the CPU data cache is using a write-allocate mode,
1820 this option is unlikely to provide any performance gain.
1824 prompt "Enable seccomp to safely compute untrusted bytecode"
1826 This kernel feature is useful for number crunching applications
1827 that may need to compute untrusted bytecode during their
1828 execution. By using pipes or other transports made available to
1829 the process as file descriptors supporting the read/write
1830 syscalls, it's possible to isolate those applications in
1831 their own address space using seccomp. Once seccomp is
1832 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1833 and the task is only allowed to execute a few safe syscalls
1834 defined by each seccomp mode.
1836 config CC_STACKPROTECTOR
1837 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1838 depends on EXPERIMENTAL
1840 This option turns on the -fstack-protector GCC feature. This
1841 feature puts, at the beginning of functions, a canary value on
1842 the stack just before the return address, and validates
1843 the value just before actually returning. Stack based buffer
1844 overflows (that need to overwrite this return address) now also
1845 overwrite the canary, which gets detected and the attack is then
1846 neutralized via a kernel panic.
1847 This feature requires gcc version 4.2 or above.
1849 config DEPRECATED_PARAM_STRUCT
1850 bool "Provide old way to pass kernel parameters"
1852 This was deprecated in 2001 and announced to live on for 5 years.
1853 Some old boot loaders still use this way.
1860 bool "Flattened Device Tree support"
1862 select OF_EARLY_FLATTREE
1865 Include support for flattened device tree machine descriptions.
1867 # Compressed boot loader in ROM. Yes, we really want to ask about
1868 # TEXT and BSS so we preserve their values in the config files.
1869 config ZBOOT_ROM_TEXT
1870 hex "Compressed ROM boot loader base address"
1873 The physical address at which the ROM-able zImage is to be
1874 placed in the target. Platforms which normally make use of
1875 ROM-able zImage formats normally set this to a suitable
1876 value in their defconfig file.
1878 If ZBOOT_ROM is not enabled, this has no effect.
1880 config ZBOOT_ROM_BSS
1881 hex "Compressed ROM boot loader BSS address"
1884 The base address of an area of read/write memory in the target
1885 for the ROM-able zImage which must be available while the
1886 decompressor is running. It must be large enough to hold the
1887 entire decompressed kernel plus an additional 128 KiB.
1888 Platforms which normally make use of ROM-able zImage formats
1889 normally set this to a suitable value in their defconfig file.
1891 If ZBOOT_ROM is not enabled, this has no effect.
1894 bool "Compressed boot loader in ROM/flash"
1895 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1897 Say Y here if you intend to execute your compressed kernel image
1898 (zImage) directly from ROM or flash. If unsure, say N.
1901 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1902 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1903 default ZBOOT_ROM_NONE
1905 Include experimental SD/MMC loading code in the ROM-able zImage.
1906 With this enabled it is possible to write the the ROM-able zImage
1907 kernel image to an MMC or SD card and boot the kernel straight
1908 from the reset vector. At reset the processor Mask ROM will load
1909 the first part of the the ROM-able zImage which in turn loads the
1910 rest the kernel image to RAM.
1912 config ZBOOT_ROM_NONE
1913 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1915 Do not load image from SD or MMC
1917 config ZBOOT_ROM_MMCIF
1918 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1920 Load image from MMCIF hardware block.
1922 config ZBOOT_ROM_SH_MOBILE_SDHI
1923 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1925 Load image from SDHI hardware block
1929 config ARM_APPENDED_DTB
1930 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1931 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1933 With this option, the boot code will look for a device tree binary
1934 (DTB) appended to zImage
1935 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1937 This is meant as a backward compatibility convenience for those
1938 systems with a bootloader that can't be upgraded to accommodate
1939 the documented boot protocol using a device tree.
1941 Beware that there is very little in terms of protection against
1942 this option being confused by leftover garbage in memory that might
1943 look like a DTB header after a reboot if no actual DTB is appended
1944 to zImage. Do not leave this option active in a production kernel
1945 if you don't intend to always append a DTB. Proper passing of the
1946 location into r2 of a bootloader provided DTB is always preferable
1949 config ARM_ATAG_DTB_COMPAT
1950 bool "Supplement the appended DTB with traditional ATAG information"
1951 depends on ARM_APPENDED_DTB
1953 Some old bootloaders can't be updated to a DTB capable one, yet
1954 they provide ATAGs with memory configuration, the ramdisk address,
1955 the kernel cmdline string, etc. Such information is dynamically
1956 provided by the bootloader and can't always be stored in a static
1957 DTB. To allow a device tree enabled kernel to be used with such
1958 bootloaders, this option allows zImage to extract the information
1959 from the ATAG list and store it at run time into the appended DTB.
1962 string "Default kernel command string"
1965 On some architectures (EBSA110 and CATS), there is currently no way
1966 for the boot loader to pass arguments to the kernel. For these
1967 architectures, you should supply some command-line options at build
1968 time by entering them here. As a minimum, you should specify the
1969 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1972 prompt "Kernel command line type" if CMDLINE != ""
1973 default CMDLINE_FROM_BOOTLOADER
1975 config CMDLINE_FROM_BOOTLOADER
1976 bool "Use bootloader kernel arguments if available"
1978 Uses the command-line options passed by the boot loader. If
1979 the boot loader doesn't provide any, the default kernel command
1980 string provided in CMDLINE will be used.
1982 config CMDLINE_EXTEND
1983 bool "Extend bootloader kernel arguments"
1985 The command-line arguments provided by the boot loader will be
1986 appended to the default kernel command string.
1988 config CMDLINE_FORCE
1989 bool "Always use the default kernel command string"
1991 Always use the default kernel command string, even if the boot
1992 loader passes other arguments to the kernel.
1993 This is useful if you cannot or don't want to change the
1994 command-line options your boot loader passes to the kernel.
1998 bool "Kernel Execute-In-Place from ROM"
1999 depends on !ZBOOT_ROM && !ARM_LPAE
2001 Execute-In-Place allows the kernel to run from non-volatile storage
2002 directly addressable by the CPU, such as NOR flash. This saves RAM
2003 space since the text section of the kernel is not loaded from flash
2004 to RAM. Read-write sections, such as the data section and stack,
2005 are still copied to RAM. The XIP kernel is not compressed since
2006 it has to run directly from flash, so it will take more space to
2007 store it. The flash address used to link the kernel object files,
2008 and for storing it, is configuration dependent. Therefore, if you
2009 say Y here, you must know the proper physical address where to
2010 store the kernel image depending on your own flash memory usage.
2012 Also note that the make target becomes "make xipImage" rather than
2013 "make zImage" or "make Image". The final kernel binary to put in
2014 ROM memory will be arch/arm/boot/xipImage.
2018 config XIP_PHYS_ADDR
2019 hex "XIP Kernel Physical Location"
2020 depends on XIP_KERNEL
2021 default "0x00080000"
2023 This is the physical address in your flash memory the kernel will
2024 be linked for and stored to. This address is dependent on your
2028 bool "Kexec system call (EXPERIMENTAL)"
2029 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2031 kexec is a system call that implements the ability to shutdown your
2032 current kernel, and to start another kernel. It is like a reboot
2033 but it is independent of the system firmware. And like a reboot
2034 you can start any kernel with it, not just Linux.
2036 It is an ongoing process to be certain the hardware in a machine
2037 is properly shutdown, so do not be surprised if this code does not
2038 initially work for you. It may help to enable device hotplugging
2042 bool "Export atags in procfs"
2046 Should the atags used to boot the kernel be exported in an "atags"
2047 file in procfs. Useful with kexec.
2050 bool "Build kdump crash kernel (EXPERIMENTAL)"
2051 depends on EXPERIMENTAL
2053 Generate crash dump after being started by kexec. This should
2054 be normally only set in special crash dump kernels which are
2055 loaded in the main kernel with kexec-tools into a specially
2056 reserved region and then later executed after a crash by
2057 kdump/kexec. The crash dump kernel must be compiled to a
2058 memory address not used by the main kernel
2060 For more details see Documentation/kdump/kdump.txt
2062 config AUTO_ZRELADDR
2063 bool "Auto calculation of the decompressed kernel image address"
2064 depends on !ZBOOT_ROM && !ARCH_U300
2066 ZRELADDR is the physical address where the decompressed kernel
2067 image will be placed. If AUTO_ZRELADDR is selected, the address
2068 will be determined at run-time by masking the current IP with
2069 0xf8000000. This assumes the zImage being placed in the first 128MB
2070 from start of memory.
2074 menu "CPU Power Management"
2078 source "drivers/cpufreq/Kconfig"
2081 tristate "CPUfreq driver for i.MX CPUs"
2082 depends on ARCH_MXC && CPU_FREQ
2084 This enables the CPUfreq driver for i.MX CPUs.
2086 config CPU_FREQ_SA1100
2089 config CPU_FREQ_SA1110
2092 config CPU_FREQ_INTEGRATOR
2093 tristate "CPUfreq driver for ARM Integrator CPUs"
2094 depends on ARCH_INTEGRATOR && CPU_FREQ
2097 This enables the CPUfreq driver for ARM Integrator CPUs.
2099 For details, take a look at <file:Documentation/cpu-freq>.
2105 depends on CPU_FREQ && ARCH_PXA && PXA25x
2107 select CPU_FREQ_TABLE
2108 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2113 Internal configuration node for common cpufreq on Samsung SoC
2115 config CPU_FREQ_S3C24XX
2116 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2117 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
2120 This enables the CPUfreq driver for the Samsung S3C24XX family
2123 For details, take a look at <file:Documentation/cpu-freq>.
2127 config CPU_FREQ_S3C24XX_PLL
2128 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2129 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2131 Compile in support for changing the PLL frequency from the
2132 S3C24XX series CPUfreq driver. The PLL takes time to settle
2133 after a frequency change, so by default it is not enabled.
2135 This also means that the PLL tables for the selected CPU(s) will
2136 be built which may increase the size of the kernel image.
2138 config CPU_FREQ_S3C24XX_DEBUG
2139 bool "Debug CPUfreq Samsung driver core"
2140 depends on CPU_FREQ_S3C24XX
2142 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2144 config CPU_FREQ_S3C24XX_IODEBUG
2145 bool "Debug CPUfreq Samsung driver IO timing"
2146 depends on CPU_FREQ_S3C24XX
2148 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2150 config CPU_FREQ_S3C24XX_DEBUGFS
2151 bool "Export debugfs for CPUFreq"
2152 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2154 Export status information via debugfs.
2158 source "drivers/cpuidle/Kconfig"
2162 menu "Floating point emulation"
2164 comment "At least one emulation must be selected"
2167 bool "NWFPE math emulation"
2168 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2170 Say Y to include the NWFPE floating point emulator in the kernel.
2171 This is necessary to run most binaries. Linux does not currently
2172 support floating point hardware so you need to say Y here even if
2173 your machine has an FPA or floating point co-processor podule.
2175 You may say N here if you are going to load the Acorn FPEmulator
2176 early in the bootup.
2179 bool "Support extended precision"
2180 depends on FPE_NWFPE
2182 Say Y to include 80-bit support in the kernel floating-point
2183 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2184 Note that gcc does not generate 80-bit operations by default,
2185 so in most cases this option only enlarges the size of the
2186 floating point emulator without any good reason.
2188 You almost surely want to say N here.
2191 bool "FastFPE math emulation (EXPERIMENTAL)"
2192 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2194 Say Y here to include the FAST floating point emulator in the kernel.
2195 This is an experimental much faster emulator which now also has full
2196 precision for the mantissa. It does not support any exceptions.
2197 It is very simple, and approximately 3-6 times faster than NWFPE.
2199 It should be sufficient for most programs. It may be not suitable
2200 for scientific calculations, but you have to check this for yourself.
2201 If you do not feel you need a faster FP emulation you should better
2205 bool "VFP-format floating point maths"
2206 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2208 Say Y to include VFP support code in the kernel. This is needed
2209 if your hardware includes a VFP unit.
2211 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2212 release notes and additional status information.
2214 Say N if your target does not have VFP hardware.
2222 bool "Advanced SIMD (NEON) Extension support"
2223 depends on VFPv3 && CPU_V7
2225 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2230 menu "Userspace binary formats"
2232 source "fs/Kconfig.binfmt"
2235 tristate "RISC OS personality"
2238 Say Y here to include the kernel code necessary if you want to run
2239 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2240 experimental; if this sounds frightening, say N and sleep in peace.
2241 You can also say M here to compile this support as a module (which
2242 will be called arthur).
2246 menu "Power management options"
2248 source "kernel/power/Kconfig"
2250 config ARCH_SUSPEND_POSSIBLE
2251 depends on !ARCH_S5PC100
2252 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2253 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2256 config ARM_CPU_SUSPEND
2261 source "net/Kconfig"
2263 source "drivers/Kconfig"
2267 source "arch/arm/Kconfig.debug"
2269 source "security/Kconfig"
2271 source "crypto/Kconfig"
2273 source "lib/Kconfig"