4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_USE_CMPXCHG_LOCKREF
9 select ARCH_WANT_IPC_PARSE_VERSION
10 select BUILDTIME_EXTABLE_SORT if MMU
11 select CLONE_BACKWARDS
12 select CPU_PM if (SUSPEND || CPU_IDLE)
13 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
14 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
15 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
16 select GENERIC_IDLE_POLL_SETUP
17 select GENERIC_IRQ_PROBE
18 select GENERIC_IRQ_SHOW
19 select GENERIC_PCI_IOMAP
20 select GENERIC_SCHED_CLOCK
21 select GENERIC_SMP_IDLE_THREAD
22 select GENERIC_STRNCPY_FROM_USER
23 select GENERIC_STRNLEN_USER
24 select HARDIRQS_SW_RESEND
25 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
27 select HAVE_ARCH_SECCOMP_FILTER
28 select HAVE_ARCH_TRACEHOOK
30 select HAVE_CONTEXT_TRACKING
31 select HAVE_C_RECORDMCOUNT
32 select HAVE_DEBUG_KMEMLEAK
33 select HAVE_DMA_API_DEBUG
35 select HAVE_DMA_CONTIGUOUS if MMU
36 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
37 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
38 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
39 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
40 select HAVE_GENERIC_DMA_COHERENT
41 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
42 select HAVE_IDE if PCI || ISA || PCMCIA
43 select HAVE_IRQ_TIME_ACCOUNTING
44 select HAVE_KERNEL_GZIP
45 select HAVE_KERNEL_LZ4
46 select HAVE_KERNEL_LZMA
47 select HAVE_KERNEL_LZO
49 select HAVE_KPROBES if !XIP_KERNEL
50 select HAVE_KRETPROBES if (HAVE_KPROBES)
52 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
53 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
54 select HAVE_PERF_EVENTS
55 select HAVE_REGS_AND_STACK_ACCESS_API
56 select HAVE_SYSCALL_TRACEPOINTS
58 select IRQ_FORCED_THREADING
60 select MODULES_USE_ELF_REL
62 select OLD_SIGSUSPEND3
63 select PERF_USE_VMALLOC
65 select SYS_SUPPORTS_APM_EMULATION
66 # Above selects are sorted alphabetically; please add new ones
67 # according to that. Thanks.
69 The ARM series is a line of low-power-consumption RISC chip designs
70 licensed by ARM Ltd and targeted at embedded applications and
71 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
72 manufactured, but legacy ARM-based PC hardware remains popular in
73 Europe. There is an ARM Linux project with a web page at
74 <http://www.arm.linux.org.uk/>.
76 config ARM_HAS_SG_CHAIN
79 config NEED_SG_DMA_LENGTH
82 config ARM_DMA_USE_IOMMU
84 select ARM_HAS_SG_CHAIN
85 select NEED_SG_DMA_LENGTH
89 config ARM_DMA_IOMMU_ALIGNMENT
90 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
94 DMA mapping framework by default aligns all buffers to the smallest
95 PAGE_SIZE order which is greater than or equal to the requested buffer
96 size. This works well for buffers up to a few hundreds kilobytes, but
97 for larger buffers it just a waste of address space. Drivers which has
98 relatively small addressing window (like 64Mib) might run out of
99 virtual space with just a few allocations.
101 With this parameter you can specify the maximum PAGE_SIZE order for
102 DMA IOMMU buffers. Larger buffers will be aligned only to this
103 specified order. The order is expressed as a power of two multiplied
111 config MIGHT_HAVE_PCI
114 config SYS_SUPPORTS_APM_EMULATION
119 select GENERIC_ALLOCATOR
130 The Extended Industry Standard Architecture (EISA) bus was
131 developed as an open alternative to the IBM MicroChannel bus.
133 The EISA bus provided some of the features of the IBM MicroChannel
134 bus while maintaining backward compatibility with cards made for
135 the older ISA bus. The EISA bus saw limited use between 1988 and
136 1995 when it was made obsolete by the PCI bus.
138 Say Y here if you are building a kernel for an EISA-based machine.
145 config STACKTRACE_SUPPORT
149 config HAVE_LATENCYTOP_SUPPORT
154 config LOCKDEP_SUPPORT
158 config TRACE_IRQFLAGS_SUPPORT
162 config RWSEM_GENERIC_SPINLOCK
166 config RWSEM_XCHGADD_ALGORITHM
169 config ARCH_HAS_ILOG2_U32
172 config ARCH_HAS_ILOG2_U64
175 config ARCH_HAS_CPUFREQ
178 Internal node to signify that the ARCH has CPUFREQ support
179 and that the relevant menu configurations are displayed for
182 config ARCH_HAS_BANDGAP
185 config GENERIC_HWEIGHT
189 config GENERIC_CALIBRATE_DELAY
193 config ARCH_MAY_HAVE_PC_FDC
199 config NEED_DMA_MAP_STATE
202 config ARCH_HAS_DMA_SET_COHERENT_MASK
205 config GENERIC_ISA_DMA
211 config NEED_RET_TO_USER
219 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
220 default DRAM_BASE if REMAP_VECTORS_TO_RAM
223 The base address of exception vectors. This must be two pages
226 config ARM_PATCH_PHYS_VIRT
227 bool "Patch physical to virtual translations at runtime" if EMBEDDED
229 depends on !XIP_KERNEL && MMU
230 depends on !ARCH_REALVIEW || !SPARSEMEM
232 Patch phys-to-virt and virt-to-phys translation functions at
233 boot and module load time according to the position of the
234 kernel in system memory.
236 This can only be used with non-XIP MMU kernels where the base
237 of physical memory is at a 16MB boundary.
239 Only disable this option if you know that you do not require
240 this feature (eg, building a kernel for a single machine) and
241 you need to shrink the kernel to the minimal size.
243 config NEED_MACH_GPIO_H
246 Select this when mach/gpio.h is required to provide special
247 definitions for this platform. The need for mach/gpio.h should
248 be avoided when possible.
250 config NEED_MACH_IO_H
253 Select this when mach/io.h is required to provide special
254 definitions for this platform. The need for mach/io.h should
255 be avoided when possible.
257 config NEED_MACH_MEMORY_H
260 Select this when mach/memory.h is required to provide special
261 definitions for this platform. The need for mach/memory.h should
262 be avoided when possible.
265 hex "Physical address of main memory" if MMU
266 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
267 default DRAM_BASE if !MMU
269 Please provide the physical address corresponding to the
270 location of main memory in your system.
276 source "init/Kconfig"
278 source "kernel/Kconfig.freezer"
283 bool "MMU-based Paged Memory Management Support"
286 Select if you want MMU-based virtualised addressing space
287 support by paged memory management. If unsure, say 'Y'.
290 # The "ARM system type" choice list is ordered alphabetically by option
291 # text. Please add new entries in the option alphabetic order.
294 prompt "ARM system type"
295 default ARCH_VERSATILE if !MMU
296 default ARCH_MULTIPLATFORM if MMU
298 config ARCH_MULTIPLATFORM
299 bool "Allow multiple platforms to be selected"
301 select ARM_PATCH_PHYS_VIRT
304 select MULTI_IRQ_HANDLER
308 config ARCH_INTEGRATOR
309 bool "ARM Ltd. Integrator family"
310 select ARCH_HAS_CPUFREQ
313 select COMMON_CLK_VERSATILE
314 select GENERIC_CLOCKEVENTS
317 select MULTI_IRQ_HANDLER
318 select NEED_MACH_MEMORY_H
319 select PLAT_VERSATILE
321 select VERSATILE_FPGA_IRQ
323 Support for ARM's Integrator platform.
326 bool "ARM Ltd. RealView family"
327 select ARCH_WANT_OPTIONAL_GPIOLIB
329 select ARM_TIMER_SP804
331 select COMMON_CLK_VERSATILE
332 select GENERIC_CLOCKEVENTS
333 select GPIO_PL061 if GPIOLIB
335 select NEED_MACH_MEMORY_H
336 select PLAT_VERSATILE
337 select PLAT_VERSATILE_CLCD
339 This enables support for ARM Ltd RealView boards.
341 config ARCH_VERSATILE
342 bool "ARM Ltd. Versatile family"
343 select ARCH_WANT_OPTIONAL_GPIOLIB
345 select ARM_TIMER_SP804
348 select GENERIC_CLOCKEVENTS
349 select HAVE_MACH_CLKDEV
351 select PLAT_VERSATILE
352 select PLAT_VERSATILE_CLCD
353 select PLAT_VERSATILE_CLOCK
354 select VERSATILE_FPGA_IRQ
356 This enables support for ARM Ltd Versatile board.
360 select ARCH_REQUIRE_GPIOLIB
364 select NEED_MACH_GPIO_H
365 select NEED_MACH_IO_H if PCCARD
367 select PINCTRL_AT91 if USE_OF
369 This enables support for systems based on Atmel
370 AT91RM9200 and AT91SAM9* processors.
373 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
374 select ARCH_REQUIRE_GPIOLIB
380 select GENERIC_CLOCKEVENTS
382 select MULTI_IRQ_HANDLER
385 Support for Cirrus Logic 711x/721x/731x based boards.
388 bool "Cortina Systems Gemini"
389 select ARCH_REQUIRE_GPIOLIB
390 select ARCH_USES_GETTIMEOFFSET
392 select NEED_MACH_GPIO_H
394 Support for the Cortina Systems Gemini family SoCs
398 select ARCH_USES_GETTIMEOFFSET
401 select NEED_MACH_IO_H
402 select NEED_MACH_MEMORY_H
405 This is an evaluation board for the StrongARM processor available
406 from Digital. It has limited hardware on-board, including an
407 Ethernet interface, two PCMCIA sockets, two serial ports and a
412 select ARCH_HAS_HOLES_MEMORYMODEL
413 select ARCH_REQUIRE_GPIOLIB
414 select ARCH_USES_GETTIMEOFFSET
419 select NEED_MACH_MEMORY_H
421 This enables support for the Cirrus EP93xx series of CPUs.
423 config ARCH_FOOTBRIDGE
427 select GENERIC_CLOCKEVENTS
429 select NEED_MACH_IO_H if !MMU
430 select NEED_MACH_MEMORY_H
432 Support for systems based on the DC21285 companion chip
433 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
436 bool "Hilscher NetX based"
440 select GENERIC_CLOCKEVENTS
442 This enables support for systems based on the Hilscher NetX Soc
448 select NEED_MACH_MEMORY_H
449 select NEED_RET_TO_USER
454 Support for Intel's IOP13XX (XScale) family of processors.
459 select ARCH_REQUIRE_GPIOLIB
461 select NEED_MACH_GPIO_H
462 select NEED_RET_TO_USER
466 Support for Intel's 80219 and IOP32X (XScale) family of
472 select ARCH_REQUIRE_GPIOLIB
474 select NEED_MACH_GPIO_H
475 select NEED_RET_TO_USER
479 Support for Intel's IOP33X (XScale) family of processors.
484 select ARCH_HAS_DMA_SET_COHERENT_MASK
485 select ARCH_REQUIRE_GPIOLIB
488 select DMABOUNCE if PCI
489 select GENERIC_CLOCKEVENTS
490 select MIGHT_HAVE_PCI
491 select NEED_MACH_IO_H
492 select USB_EHCI_BIG_ENDIAN_DESC
493 select USB_EHCI_BIG_ENDIAN_MMIO
495 Support for Intel's IXP4XX (XScale) family of processors.
499 select ARCH_REQUIRE_GPIOLIB
501 select GENERIC_CLOCKEVENTS
502 select MIGHT_HAVE_PCI
506 select PLAT_ORION_LEGACY
507 select USB_ARCH_HAS_EHCI
509 Support for the Marvell Dove SoC 88AP510
512 bool "Marvell Kirkwood"
513 select ARCH_HAS_CPUFREQ
514 select ARCH_REQUIRE_GPIOLIB
516 select GENERIC_CLOCKEVENTS
521 select PINCTRL_KIRKWOOD
522 select PLAT_ORION_LEGACY
524 Support for the following Marvell Kirkwood series SoCs:
525 88F6180, 88F6192 and 88F6281.
528 bool "Marvell MV78xx0"
529 select ARCH_REQUIRE_GPIOLIB
531 select GENERIC_CLOCKEVENTS
534 select PLAT_ORION_LEGACY
536 Support for the following Marvell MV78xx0 series SoCs:
542 select ARCH_REQUIRE_GPIOLIB
544 select GENERIC_CLOCKEVENTS
547 select PLAT_ORION_LEGACY
549 Support for the following Marvell Orion 5x series SoCs:
550 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
551 Orion-2 (5281), Orion-1-90 (6183).
554 bool "Marvell PXA168/910/MMP2"
556 select ARCH_REQUIRE_GPIOLIB
558 select GENERIC_ALLOCATOR
559 select GENERIC_CLOCKEVENTS
562 select MULTI_IRQ_HANDLER
563 select NEED_MACH_GPIO_H
568 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
571 bool "Micrel/Kendin KS8695"
572 select ARCH_REQUIRE_GPIOLIB
575 select GENERIC_CLOCKEVENTS
576 select NEED_MACH_MEMORY_H
578 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
579 System-on-Chip devices.
582 bool "Nuvoton W90X900 CPU"
583 select ARCH_REQUIRE_GPIOLIB
587 select GENERIC_CLOCKEVENTS
589 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
590 At present, the w90x900 has been renamed nuc900, regarding
591 the ARM series product line, you can login the following
592 link address to know more.
594 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
595 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
599 select ARCH_REQUIRE_GPIOLIB
604 select GENERIC_CLOCKEVENTS
607 select USB_ARCH_HAS_OHCI
610 Support for the NXP LPC32XX family of processors
613 bool "PXA2xx/PXA3xx-based"
615 select ARCH_HAS_CPUFREQ
617 select ARCH_REQUIRE_GPIOLIB
618 select ARM_CPU_SUSPEND if PM
622 select GENERIC_CLOCKEVENTS
625 select MULTI_IRQ_HANDLER
626 select NEED_MACH_GPIO_H
630 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
634 select ARCH_REQUIRE_GPIOLIB
636 select CLKSRC_OF if OF
638 select GENERIC_CLOCKEVENTS
640 Support for Qualcomm MSM/QSD based systems. This runs on the
641 apps processor of the MSM/QSD and depends on a shared memory
642 interface to the modem processor which runs the baseband
643 stack and controls some vital subsystems
644 (clock and power control, etc).
647 bool "Renesas SH-Mobile / R-Mobile"
648 select ARM_PATCH_PHYS_VIRT
650 select GENERIC_CLOCKEVENTS
651 select HAVE_ARM_SCU if SMP
652 select HAVE_ARM_TWD if SMP
654 select HAVE_MACH_CLKDEV
656 select MIGHT_HAVE_CACHE_L2X0
657 select MULTI_IRQ_HANDLER
660 select PM_GENERIC_DOMAINS if PM
663 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
668 select ARCH_MAY_HAVE_PC_FDC
669 select ARCH_SPARSEMEM_ENABLE
670 select ARCH_USES_GETTIMEOFFSET
673 select HAVE_PATA_PLATFORM
675 select NEED_MACH_IO_H
676 select NEED_MACH_MEMORY_H
680 On the Acorn Risc-PC, Linux can support the internal IDE disk and
681 CD-ROM interface, serial and parallel port, and the floppy drive.
685 select ARCH_HAS_CPUFREQ
687 select ARCH_REQUIRE_GPIOLIB
688 select ARCH_SPARSEMEM_ENABLE
693 select GENERIC_CLOCKEVENTS
696 select NEED_MACH_GPIO_H
697 select NEED_MACH_MEMORY_H
700 Support for StrongARM 11x0 based boards.
703 bool "Samsung S3C24XX SoCs"
704 select ARCH_HAS_CPUFREQ
705 select ARCH_REQUIRE_GPIOLIB
707 select CLKSRC_SAMSUNG_PWM
708 select GENERIC_CLOCKEVENTS
711 select HAVE_S3C2410_I2C if I2C
712 select HAVE_S3C2410_WATCHDOG if WATCHDOG
713 select HAVE_S3C_RTC if RTC_CLASS
714 select MULTI_IRQ_HANDLER
715 select NEED_MACH_GPIO_H
716 select NEED_MACH_IO_H
719 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
720 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
721 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
722 Samsung SMDK2410 development board (and derivatives).
725 bool "Samsung S3C64XX"
726 select ARCH_HAS_CPUFREQ
727 select ARCH_REQUIRE_GPIOLIB
730 select CLKSRC_SAMSUNG_PWM
732 select GENERIC_CLOCKEVENTS
735 select HAVE_S3C2410_I2C if I2C
736 select HAVE_S3C2410_WATCHDOG if WATCHDOG
738 select NEED_MACH_GPIO_H
742 select S3C_GPIO_TRACK
744 select SAMSUNG_CLKSRC
745 select SAMSUNG_GPIOLIB_4BIT
746 select SAMSUNG_WDT_RESET
747 select USB_ARCH_HAS_OHCI
749 Samsung S3C64XX series based systems
752 bool "Samsung S5P6440 S5P6450"
754 select CLKSRC_SAMSUNG_PWM
756 select GENERIC_CLOCKEVENTS
759 select HAVE_S3C2410_I2C if I2C
760 select HAVE_S3C2410_WATCHDOG if WATCHDOG
761 select HAVE_S3C_RTC if RTC_CLASS
762 select NEED_MACH_GPIO_H
764 select SAMSUNG_WDT_RESET
766 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
770 bool "Samsung S5PC100"
771 select ARCH_REQUIRE_GPIOLIB
773 select CLKSRC_SAMSUNG_PWM
775 select GENERIC_CLOCKEVENTS
778 select HAVE_S3C2410_I2C if I2C
779 select HAVE_S3C2410_WATCHDOG if WATCHDOG
780 select HAVE_S3C_RTC if RTC_CLASS
781 select NEED_MACH_GPIO_H
783 select SAMSUNG_WDT_RESET
785 Samsung S5PC100 series based systems
788 bool "Samsung S5PV210/S5PC110"
789 select ARCH_HAS_CPUFREQ
790 select ARCH_HAS_HOLES_MEMORYMODEL
791 select ARCH_SPARSEMEM_ENABLE
793 select CLKSRC_SAMSUNG_PWM
795 select GENERIC_CLOCKEVENTS
798 select HAVE_S3C2410_I2C if I2C
799 select HAVE_S3C2410_WATCHDOG if WATCHDOG
800 select HAVE_S3C_RTC if RTC_CLASS
801 select NEED_MACH_GPIO_H
802 select NEED_MACH_MEMORY_H
805 Samsung S5PV210/S5PC110 series based systems
808 bool "Samsung EXYNOS"
809 select ARCH_HAS_CPUFREQ
810 select ARCH_HAS_HOLES_MEMORYMODEL
811 select ARCH_REQUIRE_GPIOLIB
812 select ARCH_SPARSEMEM_ENABLE
817 select GENERIC_CLOCKEVENTS
819 select HAVE_S3C2410_I2C if I2C
820 select HAVE_S3C2410_WATCHDOG if WATCHDOG
821 select HAVE_S3C_RTC if RTC_CLASS
822 select NEED_MACH_MEMORY_H
826 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
830 select ARCH_USES_GETTIMEOFFSET
834 select NEED_MACH_MEMORY_H
839 Support for the StrongARM based Digital DNARD machine, also known
840 as "Shark" (<http://www.shark-linux.de/shark.html>).
844 select ARCH_HAS_HOLES_MEMORYMODEL
845 select ARCH_REQUIRE_GPIOLIB
847 select GENERIC_ALLOCATOR
848 select GENERIC_CLOCKEVENTS
849 select GENERIC_IRQ_CHIP
851 select NEED_MACH_GPIO_H
856 Support for TI's DaVinci platform.
861 select ARCH_HAS_CPUFREQ
862 select ARCH_HAS_HOLES_MEMORYMODEL
864 select ARCH_REQUIRE_GPIOLIB
867 select GENERIC_CLOCKEVENTS
868 select GENERIC_IRQ_CHIP
872 select NEED_MACH_IO_H if PCCARD
873 select NEED_MACH_MEMORY_H
875 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
879 menu "Multiple platform selection"
880 depends on ARCH_MULTIPLATFORM
882 comment "CPU Core family selection"
884 config ARCH_MULTI_V4T
885 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
886 depends on !ARCH_MULTI_V6_V7
887 select ARCH_MULTI_V4_V5
888 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
889 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
890 CPU_ARM925T || CPU_ARM940T)
893 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
894 depends on !ARCH_MULTI_V6_V7
895 select ARCH_MULTI_V4_V5
896 select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \
897 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
898 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
900 config ARCH_MULTI_V4_V5
904 bool "ARMv6 based platforms (ARM11)"
905 select ARCH_MULTI_V6_V7
909 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
911 select ARCH_MULTI_V6_V7
914 config ARCH_MULTI_V6_V7
917 config ARCH_MULTI_CPU_AUTO
918 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
924 # This is sorted alphabetically by mach-* pathname. However, plat-*
925 # Kconfigs may be included either alphabetically (according to the
926 # plat- suffix) or along side the corresponding mach-* source.
928 source "arch/arm/mach-mvebu/Kconfig"
930 source "arch/arm/mach-at91/Kconfig"
932 source "arch/arm/mach-bcm/Kconfig"
934 source "arch/arm/mach-bcm2835/Kconfig"
936 source "arch/arm/mach-clps711x/Kconfig"
938 source "arch/arm/mach-cns3xxx/Kconfig"
940 source "arch/arm/mach-davinci/Kconfig"
942 source "arch/arm/mach-dove/Kconfig"
944 source "arch/arm/mach-ep93xx/Kconfig"
946 source "arch/arm/mach-footbridge/Kconfig"
948 source "arch/arm/mach-gemini/Kconfig"
950 source "arch/arm/mach-highbank/Kconfig"
952 source "arch/arm/mach-integrator/Kconfig"
954 source "arch/arm/mach-iop32x/Kconfig"
956 source "arch/arm/mach-iop33x/Kconfig"
958 source "arch/arm/mach-iop13xx/Kconfig"
960 source "arch/arm/mach-ixp4xx/Kconfig"
962 source "arch/arm/mach-keystone/Kconfig"
964 source "arch/arm/mach-kirkwood/Kconfig"
966 source "arch/arm/mach-ks8695/Kconfig"
968 source "arch/arm/mach-msm/Kconfig"
970 source "arch/arm/mach-mv78xx0/Kconfig"
972 source "arch/arm/mach-imx/Kconfig"
974 source "arch/arm/mach-mxs/Kconfig"
976 source "arch/arm/mach-netx/Kconfig"
978 source "arch/arm/mach-nomadik/Kconfig"
980 source "arch/arm/mach-nspire/Kconfig"
982 source "arch/arm/plat-omap/Kconfig"
984 source "arch/arm/mach-omap1/Kconfig"
986 source "arch/arm/mach-omap2/Kconfig"
988 source "arch/arm/mach-orion5x/Kconfig"
990 source "arch/arm/mach-picoxcell/Kconfig"
992 source "arch/arm/mach-pxa/Kconfig"
993 source "arch/arm/plat-pxa/Kconfig"
995 source "arch/arm/mach-mmp/Kconfig"
997 source "arch/arm/mach-realview/Kconfig"
999 source "arch/arm/mach-rockchip/Kconfig"
1001 source "arch/arm/mach-sa1100/Kconfig"
1003 source "arch/arm/plat-samsung/Kconfig"
1005 source "arch/arm/mach-socfpga/Kconfig"
1007 source "arch/arm/mach-spear/Kconfig"
1009 source "arch/arm/mach-sti/Kconfig"
1011 source "arch/arm/mach-s3c24xx/Kconfig"
1014 source "arch/arm/mach-s3c64xx/Kconfig"
1017 source "arch/arm/mach-s5p64x0/Kconfig"
1019 source "arch/arm/mach-s5pc100/Kconfig"
1021 source "arch/arm/mach-s5pv210/Kconfig"
1023 source "arch/arm/mach-exynos/Kconfig"
1025 source "arch/arm/mach-shmobile/Kconfig"
1027 source "arch/arm/mach-sunxi/Kconfig"
1029 source "arch/arm/mach-prima2/Kconfig"
1031 source "arch/arm/mach-tegra/Kconfig"
1033 source "arch/arm/mach-u300/Kconfig"
1035 source "arch/arm/mach-ux500/Kconfig"
1037 source "arch/arm/mach-versatile/Kconfig"
1039 source "arch/arm/mach-vexpress/Kconfig"
1040 source "arch/arm/plat-versatile/Kconfig"
1042 source "arch/arm/mach-virt/Kconfig"
1044 source "arch/arm/mach-vt8500/Kconfig"
1046 source "arch/arm/mach-w90x900/Kconfig"
1048 source "arch/arm/mach-zynq/Kconfig"
1050 # Definitions to make life easier
1056 select GENERIC_CLOCKEVENTS
1062 select GENERIC_IRQ_CHIP
1065 config PLAT_ORION_LEGACY
1072 config PLAT_VERSATILE
1075 config ARM_TIMER_SP804
1078 select CLKSRC_OF if OF
1080 source arch/arm/mm/Kconfig
1084 default 16 if ARCH_EP93XX
1088 bool "Enable iWMMXt support" if !CPU_PJ4
1089 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1090 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1092 Enable support for iWMMXt context switching at run time if
1093 running on a CPU that supports it.
1095 config MULTI_IRQ_HANDLER
1098 Allow each machine to specify it's own IRQ handler at run time.
1101 source "arch/arm/Kconfig-nommu"
1104 config PJ4B_ERRATA_4742
1105 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1106 depends on CPU_PJ4B && MACH_ARMADA_370
1109 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1110 Event (WFE) IDLE states, a specific timing sensitivity exists between
1111 the retiring WFI/WFE instructions and the newly issued subsequent
1112 instructions. This sensitivity can result in a CPU hang scenario.
1114 The software must insert either a Data Synchronization Barrier (DSB)
1115 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1118 config ARM_ERRATA_326103
1119 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1122 Executing a SWP instruction to read-only memory does not set bit 11
1123 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1124 treat the access as a read, preventing a COW from occurring and
1125 causing the faulting task to livelock.
1127 config ARM_ERRATA_411920
1128 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1129 depends on CPU_V6 || CPU_V6K
1131 Invalidation of the Instruction Cache operation can
1132 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1133 It does not affect the MPCore. This option enables the ARM Ltd.
1134 recommended workaround.
1136 config ARM_ERRATA_430973
1137 bool "ARM errata: Stale prediction on replaced interworking branch"
1140 This option enables the workaround for the 430973 Cortex-A8
1141 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1142 interworking branch is replaced with another code sequence at the
1143 same virtual address, whether due to self-modifying code or virtual
1144 to physical address re-mapping, Cortex-A8 does not recover from the
1145 stale interworking branch prediction. This results in Cortex-A8
1146 executing the new code sequence in the incorrect ARM or Thumb state.
1147 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1148 and also flushes the branch target cache at every context switch.
1149 Note that setting specific bits in the ACTLR register may not be
1150 available in non-secure mode.
1152 config ARM_ERRATA_458693
1153 bool "ARM errata: Processor deadlock when a false hazard is created"
1155 depends on !ARCH_MULTIPLATFORM
1157 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1158 erratum. For very specific sequences of memory operations, it is
1159 possible for a hazard condition intended for a cache line to instead
1160 be incorrectly associated with a different cache line. This false
1161 hazard might then cause a processor deadlock. The workaround enables
1162 the L1 caching of the NEON accesses and disables the PLD instruction
1163 in the ACTLR register. Note that setting specific bits in the ACTLR
1164 register may not be available in non-secure mode.
1166 config ARM_ERRATA_460075
1167 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1169 depends on !ARCH_MULTIPLATFORM
1171 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1172 erratum. Any asynchronous access to the L2 cache may encounter a
1173 situation in which recent store transactions to the L2 cache are lost
1174 and overwritten with stale memory contents from external memory. The
1175 workaround disables the write-allocate mode for the L2 cache via the
1176 ACTLR register. Note that setting specific bits in the ACTLR register
1177 may not be available in non-secure mode.
1179 config ARM_ERRATA_742230
1180 bool "ARM errata: DMB operation may be faulty"
1181 depends on CPU_V7 && SMP
1182 depends on !ARCH_MULTIPLATFORM
1184 This option enables the workaround for the 742230 Cortex-A9
1185 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1186 between two write operations may not ensure the correct visibility
1187 ordering of the two writes. This workaround sets a specific bit in
1188 the diagnostic register of the Cortex-A9 which causes the DMB
1189 instruction to behave as a DSB, ensuring the correct behaviour of
1192 config ARM_ERRATA_742231
1193 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1194 depends on CPU_V7 && SMP
1195 depends on !ARCH_MULTIPLATFORM
1197 This option enables the workaround for the 742231 Cortex-A9
1198 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1199 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1200 accessing some data located in the same cache line, may get corrupted
1201 data due to bad handling of the address hazard when the line gets
1202 replaced from one of the CPUs at the same time as another CPU is
1203 accessing it. This workaround sets specific bits in the diagnostic
1204 register of the Cortex-A9 which reduces the linefill issuing
1205 capabilities of the processor.
1207 config PL310_ERRATA_588369
1208 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1209 depends on CACHE_L2X0
1211 The PL310 L2 cache controller implements three types of Clean &
1212 Invalidate maintenance operations: by Physical Address
1213 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1214 They are architecturally defined to behave as the execution of a
1215 clean operation followed immediately by an invalidate operation,
1216 both performing to the same memory location. This functionality
1217 is not correctly implemented in PL310 as clean lines are not
1218 invalidated as a result of these operations.
1220 config ARM_ERRATA_643719
1221 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1222 depends on CPU_V7 && SMP
1224 This option enables the workaround for the 643719 Cortex-A9 (prior to
1225 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1226 register returns zero when it should return one. The workaround
1227 corrects this value, ensuring cache maintenance operations which use
1228 it behave as intended and avoiding data corruption.
1230 config ARM_ERRATA_720789
1231 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1234 This option enables the workaround for the 720789 Cortex-A9 (prior to
1235 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1236 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1237 As a consequence of this erratum, some TLB entries which should be
1238 invalidated are not, resulting in an incoherency in the system page
1239 tables. The workaround changes the TLB flushing routines to invalidate
1240 entries regardless of the ASID.
1242 config PL310_ERRATA_727915
1243 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1244 depends on CACHE_L2X0
1246 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1247 operation (offset 0x7FC). This operation runs in background so that
1248 PL310 can handle normal accesses while it is in progress. Under very
1249 rare circumstances, due to this erratum, write data can be lost when
1250 PL310 treats a cacheable write transaction during a Clean &
1251 Invalidate by Way operation.
1253 config ARM_ERRATA_743622
1254 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1256 depends on !ARCH_MULTIPLATFORM
1258 This option enables the workaround for the 743622 Cortex-A9
1259 (r2p*) erratum. Under very rare conditions, a faulty
1260 optimisation in the Cortex-A9 Store Buffer may lead to data
1261 corruption. This workaround sets a specific bit in the diagnostic
1262 register of the Cortex-A9 which disables the Store Buffer
1263 optimisation, preventing the defect from occurring. This has no
1264 visible impact on the overall performance or power consumption of the
1267 config ARM_ERRATA_751472
1268 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1270 depends on !ARCH_MULTIPLATFORM
1272 This option enables the workaround for the 751472 Cortex-A9 (prior
1273 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1274 completion of a following broadcasted operation if the second
1275 operation is received by a CPU before the ICIALLUIS has completed,
1276 potentially leading to corrupted entries in the cache or TLB.
1278 config PL310_ERRATA_753970
1279 bool "PL310 errata: cache sync operation may be faulty"
1280 depends on CACHE_PL310
1282 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1284 Under some condition the effect of cache sync operation on
1285 the store buffer still remains when the operation completes.
1286 This means that the store buffer is always asked to drain and
1287 this prevents it from merging any further writes. The workaround
1288 is to replace the normal offset of cache sync operation (0x730)
1289 by another offset targeting an unmapped PL310 register 0x740.
1290 This has the same effect as the cache sync operation: store buffer
1291 drain and waiting for all buffers empty.
1293 config ARM_ERRATA_754322
1294 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1297 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1298 r3p*) erratum. A speculative memory access may cause a page table walk
1299 which starts prior to an ASID switch but completes afterwards. This
1300 can populate the micro-TLB with a stale entry which may be hit with
1301 the new ASID. This workaround places two dsb instructions in the mm
1302 switching code so that no page table walks can cross the ASID switch.
1304 config ARM_ERRATA_754327
1305 bool "ARM errata: no automatic Store Buffer drain"
1306 depends on CPU_V7 && SMP
1308 This option enables the workaround for the 754327 Cortex-A9 (prior to
1309 r2p0) erratum. The Store Buffer does not have any automatic draining
1310 mechanism and therefore a livelock may occur if an external agent
1311 continuously polls a memory location waiting to observe an update.
1312 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1313 written polling loops from denying visibility of updates to memory.
1315 config ARM_ERRATA_364296
1316 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1319 This options enables the workaround for the 364296 ARM1136
1320 r0p2 erratum (possible cache data corruption with
1321 hit-under-miss enabled). It sets the undocumented bit 31 in
1322 the auxiliary control register and the FI bit in the control
1323 register, thus disabling hit-under-miss without putting the
1324 processor into full low interrupt latency mode. ARM11MPCore
1327 config ARM_ERRATA_764369
1328 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1329 depends on CPU_V7 && SMP
1331 This option enables the workaround for erratum 764369
1332 affecting Cortex-A9 MPCore with two or more processors (all
1333 current revisions). Under certain timing circumstances, a data
1334 cache line maintenance operation by MVA targeting an Inner
1335 Shareable memory region may fail to proceed up to either the
1336 Point of Coherency or to the Point of Unification of the
1337 system. This workaround adds a DSB instruction before the
1338 relevant cache maintenance functions and sets a specific bit
1339 in the diagnostic control register of the SCU.
1341 config PL310_ERRATA_769419
1342 bool "PL310 errata: no automatic Store Buffer drain"
1343 depends on CACHE_L2X0
1345 On revisions of the PL310 prior to r3p2, the Store Buffer does
1346 not automatically drain. This can cause normal, non-cacheable
1347 writes to be retained when the memory system is idle, leading
1348 to suboptimal I/O performance for drivers using coherent DMA.
1349 This option adds a write barrier to the cpu_idle loop so that,
1350 on systems with an outer cache, the store buffer is drained
1353 config ARM_ERRATA_775420
1354 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1357 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1358 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1359 operation aborts with MMU exception, it might cause the processor
1360 to deadlock. This workaround puts DSB before executing ISB if
1361 an abort may occur on cache maintenance.
1363 config ARM_ERRATA_798181
1364 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1365 depends on CPU_V7 && SMP
1367 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1368 adequately shooting down all use of the old entries. This
1369 option enables the Linux kernel workaround for this erratum
1370 which sends an IPI to the CPUs that are running the same ASID
1371 as the one being invalidated.
1373 config ARM_ERRATA_773022
1374 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1377 This option enables the workaround for the 773022 Cortex-A15
1378 (up to r0p4) erratum. In certain rare sequences of code, the
1379 loop buffer may deliver incorrect instructions. This
1380 workaround disables the loop buffer to avoid the erratum.
1384 source "arch/arm/common/Kconfig"
1394 Find out whether you have ISA slots on your motherboard. ISA is the
1395 name of a bus system, i.e. the way the CPU talks to the other stuff
1396 inside your box. Other bus systems are PCI, EISA, MicroChannel
1397 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1398 newer boards don't support it. If you have ISA, say Y, otherwise N.
1400 # Select ISA DMA controller support
1405 # Select ISA DMA interface
1410 bool "PCI support" if MIGHT_HAVE_PCI
1412 Find out whether you have a PCI motherboard. PCI is the name of a
1413 bus system, i.e. the way the CPU talks to the other stuff inside
1414 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1415 VESA. If you have PCI, say Y, otherwise N.
1421 config PCI_NANOENGINE
1422 bool "BSE nanoEngine PCI support"
1423 depends on SA1100_NANOENGINE
1425 Enable PCI on the BSE nanoEngine board.
1430 # Select the host bridge type
1431 config PCI_HOST_VIA82C505
1433 depends on PCI && ARCH_SHARK
1436 config PCI_HOST_ITE8152
1438 depends on PCI && MACH_ARMCORE
1442 source "drivers/pci/Kconfig"
1443 source "drivers/pci/pcie/Kconfig"
1445 source "drivers/pcmcia/Kconfig"
1449 menu "Kernel Features"
1454 This option should be selected by machines which have an SMP-
1457 The only effect of this option is to make the SMP-related
1458 options available to the user for configuration.
1461 bool "Symmetric Multi-Processing"
1462 depends on CPU_V6K || CPU_V7
1463 depends on GENERIC_CLOCKEVENTS
1465 depends on MMU || ARM_MPU
1466 select USE_GENERIC_SMP_HELPERS
1468 This enables support for systems with more than one CPU. If you have
1469 a system with only one CPU, like most personal computers, say N. If
1470 you have a system with more than one CPU, say Y.
1472 If you say N here, the kernel will run on single and multiprocessor
1473 machines, but will use only one CPU of a multiprocessor machine. If
1474 you say Y here, the kernel will run on many, but not all, single
1475 processor machines. On a single processor machine, the kernel will
1476 run faster if you say N here.
1478 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1479 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1480 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1482 If you don't know what to do here, say N.
1485 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1486 depends on SMP && !XIP_KERNEL && MMU
1489 SMP kernels contain instructions which fail on non-SMP processors.
1490 Enabling this option allows the kernel to modify itself to make
1491 these instructions safe. Disabling it allows about 1K of space
1494 If you don't know what to do here, say Y.
1496 config ARM_CPU_TOPOLOGY
1497 bool "Support cpu topology definition"
1498 depends on SMP && CPU_V7
1501 Support ARM cpu topology definition. The MPIDR register defines
1502 affinity between processors which is then used to describe the cpu
1503 topology of an ARM System.
1506 bool "Multi-core scheduler support"
1507 depends on ARM_CPU_TOPOLOGY
1509 Multi-core scheduler support improves the CPU scheduler's decision
1510 making when dealing with multi-core CPU chips at a cost of slightly
1511 increased overhead in some places. If unsure say N here.
1514 bool "SMT scheduler support"
1515 depends on ARM_CPU_TOPOLOGY
1517 Improves the CPU scheduler's decision making when dealing with
1518 MultiThreading at a cost of slightly increased overhead in some
1519 places. If unsure say N here.
1524 This option enables support for the ARM system coherency unit
1526 config HAVE_ARM_ARCH_TIMER
1527 bool "Architected timer support"
1529 select ARM_ARCH_TIMER
1531 This option enables support for the ARM architected timer
1536 select CLKSRC_OF if OF
1538 This options enables support for the ARM timer and watchdog unit
1541 bool "Multi-Cluster Power Management"
1542 depends on CPU_V7 && SMP
1544 This option provides the common power management infrastructure
1545 for (multi-)cluster based systems, such as big.LITTLE based
1549 prompt "Memory split"
1552 Select the desired split between kernel and user memory.
1554 If you are not absolutely sure what you are doing, leave this
1558 bool "3G/1G user/kernel split"
1560 bool "2G/2G user/kernel split"
1562 bool "1G/3G user/kernel split"
1567 default 0x40000000 if VMSPLIT_1G
1568 default 0x80000000 if VMSPLIT_2G
1572 int "Maximum number of CPUs (2-32)"
1578 bool "Support for hot-pluggable CPUs"
1581 Say Y here to experiment with turning CPUs off and on. CPUs
1582 can be controlled through /sys/devices/system/cpu.
1585 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1588 Say Y here if you want Linux to communicate with system firmware
1589 implementing the PSCI specification for CPU-centric power
1590 management operations described in ARM document number ARM DEN
1591 0022A ("Power State Coordination Interface System Software on
1594 # The GPIO number here must be sorted by descending number. In case of
1595 # a multiplatform kernel, we just want the highest value required by the
1596 # selected platforms.
1599 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1600 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX
1601 default 392 if ARCH_U8500
1602 default 352 if ARCH_VT8500
1603 default 288 if ARCH_SUNXI
1604 default 264 if MACH_H4700
1607 Maximum number of GPIOs in the system.
1609 If unsure, leave the default value.
1611 source kernel/Kconfig.preempt
1615 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1616 ARCH_S5PV210 || ARCH_EXYNOS4
1617 default AT91_TIMER_HZ if ARCH_AT91
1618 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1622 depends on HZ_FIXED = 0
1623 prompt "Timer frequency"
1647 default HZ_FIXED if HZ_FIXED != 0
1648 default 100 if HZ_100
1649 default 200 if HZ_200
1650 default 250 if HZ_250
1651 default 300 if HZ_300
1652 default 500 if HZ_500
1656 def_bool HIGH_RES_TIMERS
1659 def_bool HIGH_RES_TIMERS
1661 config THUMB2_KERNEL
1662 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1663 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1664 default y if CPU_THUMBONLY
1666 select ARM_ASM_UNIFIED
1669 By enabling this option, the kernel will be compiled in
1670 Thumb-2 mode. A compiler/assembler that understand the unified
1671 ARM-Thumb syntax is needed.
1675 config THUMB2_AVOID_R_ARM_THM_JUMP11
1676 bool "Work around buggy Thumb-2 short branch relocations in gas"
1677 depends on THUMB2_KERNEL && MODULES
1680 Various binutils versions can resolve Thumb-2 branches to
1681 locally-defined, preemptible global symbols as short-range "b.n"
1682 branch instructions.
1684 This is a problem, because there's no guarantee the final
1685 destination of the symbol, or any candidate locations for a
1686 trampoline, are within range of the branch. For this reason, the
1687 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1688 relocation in modules at all, and it makes little sense to add
1691 The symptom is that the kernel fails with an "unsupported
1692 relocation" error when loading some modules.
1694 Until fixed tools are available, passing
1695 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1696 code which hits this problem, at the cost of a bit of extra runtime
1697 stack usage in some cases.
1699 The problem is described in more detail at:
1700 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1702 Only Thumb-2 kernels are affected.
1704 Unless you are sure your tools don't have this problem, say Y.
1706 config ARM_ASM_UNIFIED
1710 bool "Use the ARM EABI to compile the kernel"
1712 This option allows for the kernel to be compiled using the latest
1713 ARM ABI (aka EABI). This is only useful if you are using a user
1714 space environment that is also compiled with EABI.
1716 Since there are major incompatibilities between the legacy ABI and
1717 EABI, especially with regard to structure member alignment, this
1718 option also changes the kernel syscall calling convention to
1719 disambiguate both ABIs and allow for backward compatibility support
1720 (selected with CONFIG_OABI_COMPAT).
1722 To use this you need GCC version 4.0.0 or later.
1725 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1726 depends on AEABI && !THUMB2_KERNEL
1729 This option preserves the old syscall interface along with the
1730 new (ARM EABI) one. It also provides a compatibility layer to
1731 intercept syscalls that have structure arguments which layout
1732 in memory differs between the legacy ABI and the new ARM EABI
1733 (only for non "thumb" binaries). This option adds a tiny
1734 overhead to all syscalls and produces a slightly larger kernel.
1735 If you know you'll be using only pure EABI user space then you
1736 can say N here. If this option is not selected and you attempt
1737 to execute a legacy ABI binary then the result will be
1738 UNPREDICTABLE (in fact it can be predicted that it won't work
1739 at all). If in doubt say Y.
1741 config ARCH_HAS_HOLES_MEMORYMODEL
1744 config ARCH_SPARSEMEM_ENABLE
1747 config ARCH_SPARSEMEM_DEFAULT
1748 def_bool ARCH_SPARSEMEM_ENABLE
1750 config ARCH_SELECT_MEMORY_MODEL
1751 def_bool ARCH_SPARSEMEM_ENABLE
1753 config HAVE_ARCH_PFN_VALID
1754 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1757 bool "High Memory Support"
1760 The address space of ARM processors is only 4 Gigabytes large
1761 and it has to accommodate user address space, kernel address
1762 space as well as some memory mapped IO. That means that, if you
1763 have a large amount of physical memory and/or IO, not all of the
1764 memory can be "permanently mapped" by the kernel. The physical
1765 memory that is not permanently mapped is called "high memory".
1767 Depending on the selected kernel/user memory split, minimum
1768 vmalloc space and actual amount of RAM, you may not need this
1769 option which should result in a slightly faster kernel.
1774 bool "Allocate 2nd-level pagetables from highmem"
1777 config HW_PERF_EVENTS
1778 bool "Enable hardware performance counter support for perf events"
1779 depends on PERF_EVENTS
1782 Enable hardware performance counter support for perf events. If
1783 disabled, perf events will use software events only.
1785 config SYS_SUPPORTS_HUGETLBFS
1789 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1793 config ARCH_WANT_GENERAL_HUGETLB
1798 config FORCE_MAX_ZONEORDER
1799 int "Maximum zone order" if ARCH_SHMOBILE
1800 range 11 64 if ARCH_SHMOBILE
1801 default "12" if SOC_AM33XX
1802 default "9" if SA1111
1805 The kernel memory allocator divides physically contiguous memory
1806 blocks into "zones", where each zone is a power of two number of
1807 pages. This option selects the largest power of two that the kernel
1808 keeps in the memory allocator. If you need to allocate very large
1809 blocks of physically contiguous memory, then you may need to
1810 increase this value.
1812 This config option is actually maximum order plus one. For example,
1813 a value of 11 means that the largest free memory block is 2^10 pages.
1815 config ALIGNMENT_TRAP
1817 depends on CPU_CP15_MMU
1818 default y if !ARCH_EBSA110
1819 select HAVE_PROC_CPU if PROC_FS
1821 ARM processors cannot fetch/store information which is not
1822 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1823 address divisible by 4. On 32-bit ARM processors, these non-aligned
1824 fetch/store instructions will be emulated in software if you say
1825 here, which has a severe performance impact. This is necessary for
1826 correct operation of some network protocols. With an IP-only
1827 configuration it is safe to say N, otherwise say Y.
1829 config UACCESS_WITH_MEMCPY
1830 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1832 default y if CPU_FEROCEON
1834 Implement faster copy_to_user and clear_user methods for CPU
1835 cores where a 8-word STM instruction give significantly higher
1836 memory write throughput than a sequence of individual 32bit stores.
1838 A possible side effect is a slight increase in scheduling latency
1839 between threads sharing the same address space if they invoke
1840 such copy operations with large buffers.
1842 However, if the CPU data cache is using a write-allocate mode,
1843 this option is unlikely to provide any performance gain.
1847 prompt "Enable seccomp to safely compute untrusted bytecode"
1849 This kernel feature is useful for number crunching applications
1850 that may need to compute untrusted bytecode during their
1851 execution. By using pipes or other transports made available to
1852 the process as file descriptors supporting the read/write
1853 syscalls, it's possible to isolate those applications in
1854 their own address space using seccomp. Once seccomp is
1855 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1856 and the task is only allowed to execute a few safe syscalls
1857 defined by each seccomp mode.
1859 config CC_STACKPROTECTOR
1860 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1862 This option turns on the -fstack-protector GCC feature. This
1863 feature puts, at the beginning of functions, a canary value on
1864 the stack just before the return address, and validates
1865 the value just before actually returning. Stack based buffer
1866 overflows (that need to overwrite this return address) now also
1867 overwrite the canary, which gets detected and the attack is then
1868 neutralized via a kernel panic.
1869 This feature requires gcc version 4.2 or above.
1876 bool "Xen guest support on ARM (EXPERIMENTAL)"
1877 depends on ARM && AEABI && OF
1878 depends on CPU_V7 && !CPU_V6
1879 depends on !GENERIC_ATOMIC64
1882 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1889 bool "Flattened Device Tree support"
1892 select OF_EARLY_FLATTREE
1894 Include support for flattened device tree machine descriptions.
1897 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1900 This is the traditional way of passing data to the kernel at boot
1901 time. If you are solely relying on the flattened device tree (or
1902 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1903 to remove ATAGS support from your kernel binary. If unsure,
1906 config DEPRECATED_PARAM_STRUCT
1907 bool "Provide old way to pass kernel parameters"
1910 This was deprecated in 2001 and announced to live on for 5 years.
1911 Some old boot loaders still use this way.
1913 # Compressed boot loader in ROM. Yes, we really want to ask about
1914 # TEXT and BSS so we preserve their values in the config files.
1915 config ZBOOT_ROM_TEXT
1916 hex "Compressed ROM boot loader base address"
1919 The physical address at which the ROM-able zImage is to be
1920 placed in the target. Platforms which normally make use of
1921 ROM-able zImage formats normally set this to a suitable
1922 value in their defconfig file.
1924 If ZBOOT_ROM is not enabled, this has no effect.
1926 config ZBOOT_ROM_BSS
1927 hex "Compressed ROM boot loader BSS address"
1930 The base address of an area of read/write memory in the target
1931 for the ROM-able zImage which must be available while the
1932 decompressor is running. It must be large enough to hold the
1933 entire decompressed kernel plus an additional 128 KiB.
1934 Platforms which normally make use of ROM-able zImage formats
1935 normally set this to a suitable value in their defconfig file.
1937 If ZBOOT_ROM is not enabled, this has no effect.
1940 bool "Compressed boot loader in ROM/flash"
1941 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1943 Say Y here if you intend to execute your compressed kernel image
1944 (zImage) directly from ROM or flash. If unsure, say N.
1947 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1948 depends on ZBOOT_ROM && ARCH_SH7372
1949 default ZBOOT_ROM_NONE
1951 Include experimental SD/MMC loading code in the ROM-able zImage.
1952 With this enabled it is possible to write the ROM-able zImage
1953 kernel image to an MMC or SD card and boot the kernel straight
1954 from the reset vector. At reset the processor Mask ROM will load
1955 the first part of the ROM-able zImage which in turn loads the
1956 rest the kernel image to RAM.
1958 config ZBOOT_ROM_NONE
1959 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1961 Do not load image from SD or MMC
1963 config ZBOOT_ROM_MMCIF
1964 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1966 Load image from MMCIF hardware block.
1968 config ZBOOT_ROM_SH_MOBILE_SDHI
1969 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1971 Load image from SDHI hardware block
1975 config ARM_APPENDED_DTB
1976 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1977 depends on OF && !ZBOOT_ROM
1979 With this option, the boot code will look for a device tree binary
1980 (DTB) appended to zImage
1981 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1983 This is meant as a backward compatibility convenience for those
1984 systems with a bootloader that can't be upgraded to accommodate
1985 the documented boot protocol using a device tree.
1987 Beware that there is very little in terms of protection against
1988 this option being confused by leftover garbage in memory that might
1989 look like a DTB header after a reboot if no actual DTB is appended
1990 to zImage. Do not leave this option active in a production kernel
1991 if you don't intend to always append a DTB. Proper passing of the
1992 location into r2 of a bootloader provided DTB is always preferable
1995 config ARM_ATAG_DTB_COMPAT
1996 bool "Supplement the appended DTB with traditional ATAG information"
1997 depends on ARM_APPENDED_DTB
1999 Some old bootloaders can't be updated to a DTB capable one, yet
2000 they provide ATAGs with memory configuration, the ramdisk address,
2001 the kernel cmdline string, etc. Such information is dynamically
2002 provided by the bootloader and can't always be stored in a static
2003 DTB. To allow a device tree enabled kernel to be used with such
2004 bootloaders, this option allows zImage to extract the information
2005 from the ATAG list and store it at run time into the appended DTB.
2008 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2009 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2011 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2012 bool "Use bootloader kernel arguments if available"
2014 Uses the command-line options passed by the boot loader instead of
2015 the device tree bootargs property. If the boot loader doesn't provide
2016 any, the device tree bootargs property will be used.
2018 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2019 bool "Extend with bootloader kernel arguments"
2021 The command-line arguments provided by the boot loader will be
2022 appended to the the device tree bootargs property.
2027 string "Default kernel command string"
2030 On some architectures (EBSA110 and CATS), there is currently no way
2031 for the boot loader to pass arguments to the kernel. For these
2032 architectures, you should supply some command-line options at build
2033 time by entering them here. As a minimum, you should specify the
2034 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2037 prompt "Kernel command line type" if CMDLINE != ""
2038 default CMDLINE_FROM_BOOTLOADER
2041 config CMDLINE_FROM_BOOTLOADER
2042 bool "Use bootloader kernel arguments if available"
2044 Uses the command-line options passed by the boot loader. If
2045 the boot loader doesn't provide any, the default kernel command
2046 string provided in CMDLINE will be used.
2048 config CMDLINE_EXTEND
2049 bool "Extend bootloader kernel arguments"
2051 The command-line arguments provided by the boot loader will be
2052 appended to the default kernel command string.
2054 config CMDLINE_FORCE
2055 bool "Always use the default kernel command string"
2057 Always use the default kernel command string, even if the boot
2058 loader passes other arguments to the kernel.
2059 This is useful if you cannot or don't want to change the
2060 command-line options your boot loader passes to the kernel.
2064 bool "Kernel Execute-In-Place from ROM"
2065 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2067 Execute-In-Place allows the kernel to run from non-volatile storage
2068 directly addressable by the CPU, such as NOR flash. This saves RAM
2069 space since the text section of the kernel is not loaded from flash
2070 to RAM. Read-write sections, such as the data section and stack,
2071 are still copied to RAM. The XIP kernel is not compressed since
2072 it has to run directly from flash, so it will take more space to
2073 store it. The flash address used to link the kernel object files,
2074 and for storing it, is configuration dependent. Therefore, if you
2075 say Y here, you must know the proper physical address where to
2076 store the kernel image depending on your own flash memory usage.
2078 Also note that the make target becomes "make xipImage" rather than
2079 "make zImage" or "make Image". The final kernel binary to put in
2080 ROM memory will be arch/arm/boot/xipImage.
2084 config XIP_PHYS_ADDR
2085 hex "XIP Kernel Physical Location"
2086 depends on XIP_KERNEL
2087 default "0x00080000"
2089 This is the physical address in your flash memory the kernel will
2090 be linked for and stored to. This address is dependent on your
2094 bool "Kexec system call (EXPERIMENTAL)"
2095 depends on (!SMP || PM_SLEEP_SMP)
2097 kexec is a system call that implements the ability to shutdown your
2098 current kernel, and to start another kernel. It is like a reboot
2099 but it is independent of the system firmware. And like a reboot
2100 you can start any kernel with it, not just Linux.
2102 It is an ongoing process to be certain the hardware in a machine
2103 is properly shutdown, so do not be surprised if this code does not
2104 initially work for you.
2107 bool "Export atags in procfs"
2108 depends on ATAGS && KEXEC
2111 Should the atags used to boot the kernel be exported in an "atags"
2112 file in procfs. Useful with kexec.
2115 bool "Build kdump crash kernel (EXPERIMENTAL)"
2117 Generate crash dump after being started by kexec. This should
2118 be normally only set in special crash dump kernels which are
2119 loaded in the main kernel with kexec-tools into a specially
2120 reserved region and then later executed after a crash by
2121 kdump/kexec. The crash dump kernel must be compiled to a
2122 memory address not used by the main kernel
2124 For more details see Documentation/kdump/kdump.txt
2126 config AUTO_ZRELADDR
2127 bool "Auto calculation of the decompressed kernel image address"
2128 depends on !ZBOOT_ROM
2130 ZRELADDR is the physical address where the decompressed kernel
2131 image will be placed. If AUTO_ZRELADDR is selected, the address
2132 will be determined at run-time by masking the current IP with
2133 0xf8000000. This assumes the zImage being placed in the first 128MB
2134 from start of memory.
2138 menu "CPU Power Management"
2141 source "drivers/cpufreq/Kconfig"
2144 source "drivers/cpuidle/Kconfig"
2148 menu "Floating point emulation"
2150 comment "At least one emulation must be selected"
2153 bool "NWFPE math emulation"
2154 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2156 Say Y to include the NWFPE floating point emulator in the kernel.
2157 This is necessary to run most binaries. Linux does not currently
2158 support floating point hardware so you need to say Y here even if
2159 your machine has an FPA or floating point co-processor podule.
2161 You may say N here if you are going to load the Acorn FPEmulator
2162 early in the bootup.
2165 bool "Support extended precision"
2166 depends on FPE_NWFPE
2168 Say Y to include 80-bit support in the kernel floating-point
2169 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2170 Note that gcc does not generate 80-bit operations by default,
2171 so in most cases this option only enlarges the size of the
2172 floating point emulator without any good reason.
2174 You almost surely want to say N here.
2177 bool "FastFPE math emulation (EXPERIMENTAL)"
2178 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2180 Say Y here to include the FAST floating point emulator in the kernel.
2181 This is an experimental much faster emulator which now also has full
2182 precision for the mantissa. It does not support any exceptions.
2183 It is very simple, and approximately 3-6 times faster than NWFPE.
2185 It should be sufficient for most programs. It may be not suitable
2186 for scientific calculations, but you have to check this for yourself.
2187 If you do not feel you need a faster FP emulation you should better
2191 bool "VFP-format floating point maths"
2192 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2194 Say Y to include VFP support code in the kernel. This is needed
2195 if your hardware includes a VFP unit.
2197 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2198 release notes and additional status information.
2200 Say N if your target does not have VFP hardware.
2208 bool "Advanced SIMD (NEON) Extension support"
2209 depends on VFPv3 && CPU_V7
2211 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2214 config KERNEL_MODE_NEON
2215 bool "Support for NEON in kernel mode"
2216 depends on NEON && AEABI
2218 Say Y to include support for NEON in kernel mode.
2222 menu "Userspace binary formats"
2224 source "fs/Kconfig.binfmt"
2227 tristate "RISC OS personality"
2230 Say Y here to include the kernel code necessary if you want to run
2231 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2232 experimental; if this sounds frightening, say N and sleep in peace.
2233 You can also say M here to compile this support as a module (which
2234 will be called arthur).
2238 menu "Power management options"
2240 source "kernel/power/Kconfig"
2242 config ARCH_SUSPEND_POSSIBLE
2243 depends on !ARCH_S5PC100
2244 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2245 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2248 config ARM_CPU_SUSPEND
2253 source "net/Kconfig"
2255 source "drivers/Kconfig"
2259 source "arch/arm/Kconfig.debug"
2261 source "security/Kconfig"
2263 source "crypto/Kconfig"
2265 source "lib/Kconfig"
2267 source "arch/arm/kvm/Kconfig"