5 select HAVE_DMA_API_DEBUG
6 select HAVE_IDE if PCI || ISA || PCMCIA
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
12 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
14 select HAVE_ARCH_TRACEHOOK
15 select HAVE_KPROBES if !XIP_KERNEL
16 select HAVE_KRETPROBES if (HAVE_KPROBES)
17 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
18 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
19 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
20 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
21 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
22 select HAVE_GENERIC_DMA_COHERENT
23 select HAVE_KERNEL_GZIP
24 select HAVE_KERNEL_LZO
25 select HAVE_KERNEL_LZMA
28 select HAVE_PERF_EVENTS
29 select PERF_USE_VMALLOC
30 select HAVE_REGS_AND_STACK_ACCESS_API
31 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
32 select HAVE_C_RECORDMCOUNT
33 select HAVE_GENERIC_HARDIRQS
34 select HARDIRQS_SW_RESEND
35 select GENERIC_IRQ_PROBE
36 select GENERIC_IRQ_SHOW
37 select GENERIC_IRQ_PROBE
38 select HARDIRQS_SW_RESEND
39 select CPU_PM if (SUSPEND || CPU_IDLE)
40 select GENERIC_PCI_IOMAP
42 select GENERIC_SMP_IDLE_THREAD
44 The ARM series is a line of low-power-consumption RISC chip designs
45 licensed by ARM Ltd and targeted at embedded applications and
46 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
47 manufactured, but legacy ARM-based PC hardware remains popular in
48 Europe. There is an ARM Linux project with a web page at
49 <http://www.arm.linux.org.uk/>.
51 config ARM_HAS_SG_CHAIN
60 config SYS_SUPPORTS_APM_EMULATION
66 config ARCH_USES_GETTIMEOFFSET
70 config GENERIC_CLOCKEVENTS
73 config GENERIC_CLOCKEVENTS_BROADCAST
75 depends on GENERIC_CLOCKEVENTS
84 select GENERIC_ALLOCATOR
95 The Extended Industry Standard Architecture (EISA) bus was
96 developed as an open alternative to the IBM MicroChannel bus.
98 The EISA bus provided some of the features of the IBM MicroChannel
99 bus while maintaining backward compatibility with cards made for
100 the older ISA bus. The EISA bus saw limited use between 1988 and
101 1995 when it was made obsolete by the PCI bus.
103 Say Y here if you are building a kernel for an EISA-based machine.
110 config STACKTRACE_SUPPORT
114 config HAVE_LATENCYTOP_SUPPORT
119 config LOCKDEP_SUPPORT
123 config TRACE_IRQFLAGS_SUPPORT
127 config GENERIC_LOCKBREAK
130 depends on SMP && PREEMPT
132 config RWSEM_GENERIC_SPINLOCK
136 config RWSEM_XCHGADD_ALGORITHM
139 config ARCH_HAS_ILOG2_U32
142 config ARCH_HAS_ILOG2_U64
145 config ARCH_HAS_CPUFREQ
148 Internal node to signify that the ARCH has CPUFREQ support
149 and that the relevant menu configurations are displayed for
152 config GENERIC_HWEIGHT
156 config GENERIC_CALIBRATE_DELAY
160 config ARCH_MAY_HAVE_PC_FDC
166 config NEED_DMA_MAP_STATE
169 config ARCH_HAS_DMA_SET_COHERENT_MASK
172 config GENERIC_ISA_DMA
178 config NEED_RET_TO_USER
186 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
187 default DRAM_BASE if REMAP_VECTORS_TO_RAM
190 The base address of exception vectors.
192 config ARM_PATCH_PHYS_VIRT
193 bool "Patch physical to virtual translations at runtime" if EMBEDDED
195 depends on !XIP_KERNEL && MMU
196 depends on !ARCH_REALVIEW || !SPARSEMEM
198 Patch phys-to-virt and virt-to-phys translation functions at
199 boot and module load time according to the position of the
200 kernel in system memory.
202 This can only be used with non-XIP MMU kernels where the base
203 of physical memory is at a 16MB boundary.
205 Only disable this option if you know that you do not require
206 this feature (eg, building a kernel for a single machine) and
207 you need to shrink the kernel to the minimal size.
209 config NEED_MACH_IO_H
212 Select this when mach/io.h is required to provide special
213 definitions for this platform. The need for mach/io.h should
214 be avoided when possible.
216 config NEED_MACH_MEMORY_H
219 Select this when mach/memory.h is required to provide special
220 definitions for this platform. The need for mach/memory.h should
221 be avoided when possible.
224 hex "Physical address of main memory" if MMU
225 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
226 default DRAM_BASE if !MMU
228 Please provide the physical address corresponding to the
229 location of main memory in your system.
235 source "init/Kconfig"
237 source "kernel/Kconfig.freezer"
242 bool "MMU-based Paged Memory Management Support"
245 Select if you want MMU-based virtualised addressing space
246 support by paged memory management. If unsure, say 'Y'.
249 # The "ARM system type" choice list is ordered alphabetically by option
250 # text. Please add new entries in the option alphabetic order.
253 prompt "ARM system type"
254 default ARCH_VERSATILE
256 config ARCH_INTEGRATOR
257 bool "ARM Ltd. Integrator family"
259 select ARCH_HAS_CPUFREQ
261 select HAVE_MACH_CLKDEV
264 select GENERIC_CLOCKEVENTS
265 select PLAT_VERSATILE
266 select PLAT_VERSATILE_FPGA_IRQ
267 select NEED_MACH_IO_H
268 select NEED_MACH_MEMORY_H
270 select MULTI_IRQ_HANDLER
272 Support for ARM's Integrator platform.
275 bool "ARM Ltd. RealView family"
278 select HAVE_MACH_CLKDEV
280 select GENERIC_CLOCKEVENTS
281 select ARCH_WANT_OPTIONAL_GPIOLIB
282 select PLAT_VERSATILE
283 select PLAT_VERSATILE_CLCD
284 select ARM_TIMER_SP804
285 select GPIO_PL061 if GPIOLIB
286 select NEED_MACH_MEMORY_H
288 This enables support for ARM Ltd RealView boards.
290 config ARCH_VERSATILE
291 bool "ARM Ltd. Versatile family"
295 select HAVE_MACH_CLKDEV
297 select GENERIC_CLOCKEVENTS
298 select ARCH_WANT_OPTIONAL_GPIOLIB
299 select PLAT_VERSATILE
300 select PLAT_VERSATILE_CLCD
301 select PLAT_VERSATILE_FPGA_IRQ
302 select ARM_TIMER_SP804
304 This enables support for ARM Ltd Versatile board.
307 bool "ARM Ltd. Versatile Express family"
308 select ARCH_WANT_OPTIONAL_GPIOLIB
310 select ARM_TIMER_SP804
312 select HAVE_MACH_CLKDEV
313 select GENERIC_CLOCKEVENTS
315 select HAVE_PATA_PLATFORM
318 select PLAT_VERSATILE
319 select PLAT_VERSATILE_CLCD
321 This enables support for the ARM Ltd Versatile Express boards.
325 select ARCH_REQUIRE_GPIOLIB
329 select NEED_MACH_IO_H if PCCARD
331 This enables support for systems based on Atmel
332 AT91RM9200 and AT91SAM9* processors.
335 bool "Broadcom BCMRING"
339 select ARM_TIMER_SP804
341 select GENERIC_CLOCKEVENTS
342 select ARCH_WANT_OPTIONAL_GPIOLIB
344 Support for Broadcom's BCMRing platform.
347 bool "Calxeda Highbank-based"
348 select ARCH_WANT_OPTIONAL_GPIOLIB
351 select ARM_TIMER_SP804
355 select GENERIC_CLOCKEVENTS
361 Support for the Calxeda Highbank SoC based boards.
364 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
366 select ARCH_USES_GETTIMEOFFSET
367 select NEED_MACH_MEMORY_H
369 Support for Cirrus Logic 711x/721x/731x based boards.
372 bool "Cavium Networks CNS3XXX family"
374 select GENERIC_CLOCKEVENTS
376 select MIGHT_HAVE_CACHE_L2X0
377 select MIGHT_HAVE_PCI
378 select PCI_DOMAINS if PCI
380 Support for Cavium Networks CNS3XXX platform.
383 bool "Cortina Systems Gemini"
385 select ARCH_REQUIRE_GPIOLIB
386 select ARCH_USES_GETTIMEOFFSET
388 Support for the Cortina Systems Gemini family SoCs
391 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
394 select GENERIC_CLOCKEVENTS
396 select GENERIC_IRQ_CHIP
397 select MIGHT_HAVE_CACHE_L2X0
403 Support for CSR SiRFSoC ARM Cortex A9 Platform
410 select ARCH_USES_GETTIMEOFFSET
411 select NEED_MACH_IO_H
412 select NEED_MACH_MEMORY_H
414 This is an evaluation board for the StrongARM processor available
415 from Digital. It has limited hardware on-board, including an
416 Ethernet interface, two PCMCIA sockets, two serial ports and a
425 select ARCH_REQUIRE_GPIOLIB
426 select ARCH_HAS_HOLES_MEMORYMODEL
427 select ARCH_USES_GETTIMEOFFSET
428 select NEED_MACH_MEMORY_H
430 This enables support for the Cirrus EP93xx series of CPUs.
432 config ARCH_FOOTBRIDGE
436 select GENERIC_CLOCKEVENTS
438 select NEED_MACH_IO_H
439 select NEED_MACH_MEMORY_H
441 Support for systems based on the DC21285 companion chip
442 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
445 bool "Freescale MXC/iMX-based"
446 select GENERIC_CLOCKEVENTS
447 select ARCH_REQUIRE_GPIOLIB
450 select GENERIC_IRQ_CHIP
451 select MULTI_IRQ_HANDLER
453 Support for Freescale MXC/iMX-based family of processors
456 bool "Freescale MXS-based"
457 select GENERIC_CLOCKEVENTS
458 select ARCH_REQUIRE_GPIOLIB
461 select HAVE_CLK_PREPARE
464 Support for Freescale MXS-based family of processors
467 bool "Hilscher NetX based"
471 select GENERIC_CLOCKEVENTS
473 This enables support for systems based on the Hilscher NetX Soc
476 bool "Hynix HMS720x-based"
479 select ARCH_USES_GETTIMEOFFSET
481 This enables support for systems based on the Hynix HMS720x
489 select ARCH_SUPPORTS_MSI
491 select NEED_MACH_IO_H
492 select NEED_MACH_MEMORY_H
493 select NEED_RET_TO_USER
495 Support for Intel's IOP13XX (XScale) family of processors.
501 select NEED_MACH_IO_H
502 select NEED_RET_TO_USER
505 select ARCH_REQUIRE_GPIOLIB
507 Support for Intel's 80219 and IOP32X (XScale) family of
514 select NEED_MACH_IO_H
515 select NEED_RET_TO_USER
518 select ARCH_REQUIRE_GPIOLIB
520 Support for Intel's IOP33X (XScale) family of processors.
525 select ARCH_HAS_DMA_SET_COHERENT_MASK
529 select GENERIC_CLOCKEVENTS
530 select MIGHT_HAVE_PCI
531 select NEED_MACH_IO_H
532 select DMABOUNCE if PCI
534 Support for Intel's IXP4XX (XScale) family of processors.
540 select ARCH_REQUIRE_GPIOLIB
541 select GENERIC_CLOCKEVENTS
542 select NEED_MACH_IO_H
545 Support for the Marvell Dove SoC 88AP510
548 bool "Marvell Kirkwood"
551 select ARCH_REQUIRE_GPIOLIB
552 select GENERIC_CLOCKEVENTS
553 select NEED_MACH_IO_H
556 Support for the following Marvell Kirkwood series SoCs:
557 88F6180, 88F6192 and 88F6281.
563 select ARCH_REQUIRE_GPIOLIB
566 select USB_ARCH_HAS_OHCI
568 select GENERIC_CLOCKEVENTS
571 Support for the NXP LPC32XX family of processors
574 bool "Marvell MV78xx0"
577 select ARCH_REQUIRE_GPIOLIB
578 select GENERIC_CLOCKEVENTS
579 select NEED_MACH_IO_H
582 Support for the following Marvell MV78xx0 series SoCs:
590 select ARCH_REQUIRE_GPIOLIB
591 select GENERIC_CLOCKEVENTS
594 Support for the following Marvell Orion 5x series SoCs:
595 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
596 Orion-2 (5281), Orion-1-90 (6183).
599 bool "Marvell PXA168/910/MMP2"
601 select ARCH_REQUIRE_GPIOLIB
603 select GENERIC_CLOCKEVENTS
608 select GENERIC_ALLOCATOR
610 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
613 bool "Micrel/Kendin KS8695"
615 select ARCH_REQUIRE_GPIOLIB
616 select ARCH_USES_GETTIMEOFFSET
617 select NEED_MACH_MEMORY_H
619 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
620 System-on-Chip devices.
623 bool "Nuvoton W90X900 CPU"
625 select ARCH_REQUIRE_GPIOLIB
628 select GENERIC_CLOCKEVENTS
630 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
631 At present, the w90x900 has been renamed nuc900, regarding
632 the ARM series product line, you can login the following
633 link address to know more.
635 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
636 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
642 select GENERIC_CLOCKEVENTS
646 select MIGHT_HAVE_CACHE_L2X0
647 select NEED_MACH_IO_H if PCI
648 select ARCH_HAS_CPUFREQ
650 This enables support for NVIDIA Tegra based systems (Tegra APX,
651 Tegra 6xx and Tegra 2 series).
653 config ARCH_PICOXCELL
654 bool "Picochip picoXcell"
655 select ARCH_REQUIRE_GPIOLIB
656 select ARM_PATCH_PHYS_VIRT
660 select GENERIC_CLOCKEVENTS
667 This enables support for systems based on the Picochip picoXcell
668 family of Femtocell devices. The picoxcell support requires device tree
672 bool "Philips Nexperia PNX4008 Mobile"
675 select ARCH_USES_GETTIMEOFFSET
677 This enables support for Philips PNX4008 mobile platform.
680 bool "PXA2xx/PXA3xx-based"
683 select ARCH_HAS_CPUFREQ
686 select ARCH_REQUIRE_GPIOLIB
687 select GENERIC_CLOCKEVENTS
692 select MULTI_IRQ_HANDLER
693 select ARM_CPU_SUSPEND if PM
696 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
701 select GENERIC_CLOCKEVENTS
702 select ARCH_REQUIRE_GPIOLIB
705 Support for Qualcomm MSM/QSD based systems. This runs on the
706 apps processor of the MSM/QSD and depends on a shared memory
707 interface to the modem processor which runs the baseband
708 stack and controls some vital subsystems
709 (clock and power control, etc).
712 bool "Renesas SH-Mobile / R-Mobile"
715 select HAVE_MACH_CLKDEV
717 select GENERIC_CLOCKEVENTS
718 select MIGHT_HAVE_CACHE_L2X0
721 select MULTI_IRQ_HANDLER
722 select PM_GENERIC_DOMAINS if PM
723 select NEED_MACH_MEMORY_H
725 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
731 select ARCH_MAY_HAVE_PC_FDC
732 select HAVE_PATA_PLATFORM
735 select ARCH_SPARSEMEM_ENABLE
736 select ARCH_USES_GETTIMEOFFSET
738 select NEED_MACH_IO_H
739 select NEED_MACH_MEMORY_H
741 On the Acorn Risc-PC, Linux can support the internal IDE disk and
742 CD-ROM interface, serial and parallel port, and the floppy drive.
749 select ARCH_SPARSEMEM_ENABLE
751 select ARCH_HAS_CPUFREQ
753 select GENERIC_CLOCKEVENTS
755 select ARCH_REQUIRE_GPIOLIB
757 select NEED_MACH_MEMORY_H
760 Support for StrongARM 11x0 based boards.
763 bool "Samsung S3C24XX SoCs"
765 select ARCH_HAS_CPUFREQ
768 select ARCH_USES_GETTIMEOFFSET
769 select HAVE_S3C2410_I2C if I2C
770 select HAVE_S3C_RTC if RTC_CLASS
771 select HAVE_S3C2410_WATCHDOG if WATCHDOG
772 select NEED_MACH_IO_H
774 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
775 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
776 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
777 Samsung SMDK2410 development board (and derivatives).
780 bool "Samsung S3C64XX"
788 select ARCH_USES_GETTIMEOFFSET
789 select ARCH_HAS_CPUFREQ
790 select ARCH_REQUIRE_GPIOLIB
791 select SAMSUNG_CLKSRC
792 select SAMSUNG_IRQ_VIC_TIMER
793 select S3C_GPIO_TRACK
795 select USB_ARCH_HAS_OHCI
796 select SAMSUNG_GPIOLIB_4BIT
797 select HAVE_S3C2410_I2C if I2C
798 select HAVE_S3C2410_WATCHDOG if WATCHDOG
800 Samsung S3C64XX series based systems
803 bool "Samsung S5P6440 S5P6450"
809 select HAVE_S3C2410_WATCHDOG if WATCHDOG
810 select GENERIC_CLOCKEVENTS
811 select HAVE_S3C2410_I2C if I2C
812 select HAVE_S3C_RTC if RTC_CLASS
814 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
818 bool "Samsung S5PC100"
823 select ARCH_USES_GETTIMEOFFSET
824 select HAVE_S3C2410_I2C if I2C
825 select HAVE_S3C_RTC if RTC_CLASS
826 select HAVE_S3C2410_WATCHDOG if WATCHDOG
828 Samsung S5PC100 series based systems
831 bool "Samsung S5PV210/S5PC110"
833 select ARCH_SPARSEMEM_ENABLE
834 select ARCH_HAS_HOLES_MEMORYMODEL
839 select ARCH_HAS_CPUFREQ
840 select GENERIC_CLOCKEVENTS
841 select HAVE_S3C2410_I2C if I2C
842 select HAVE_S3C_RTC if RTC_CLASS
843 select HAVE_S3C2410_WATCHDOG if WATCHDOG
844 select NEED_MACH_MEMORY_H
846 Samsung S5PV210/S5PC110 series based systems
849 bool "SAMSUNG EXYNOS"
851 select ARCH_SPARSEMEM_ENABLE
852 select ARCH_HAS_HOLES_MEMORYMODEL
856 select ARCH_HAS_CPUFREQ
857 select GENERIC_CLOCKEVENTS
858 select HAVE_S3C_RTC if RTC_CLASS
859 select HAVE_S3C2410_I2C if I2C
860 select HAVE_S3C2410_WATCHDOG if WATCHDOG
861 select NEED_MACH_MEMORY_H
863 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
872 select ARCH_USES_GETTIMEOFFSET
873 select NEED_MACH_MEMORY_H
874 select NEED_MACH_IO_H
876 Support for the StrongARM based Digital DNARD machine, also known
877 as "Shark" (<http://www.shark-linux.de/shark.html>).
880 bool "ST-Ericsson U300 Series"
886 select ARM_PATCH_PHYS_VIRT
888 select GENERIC_CLOCKEVENTS
890 select HAVE_MACH_CLKDEV
892 select ARCH_REQUIRE_GPIOLIB
894 Support for ST-Ericsson U300 series mobile platforms.
897 bool "ST-Ericsson U8500 Series"
901 select GENERIC_CLOCKEVENTS
903 select ARCH_REQUIRE_GPIOLIB
904 select ARCH_HAS_CPUFREQ
906 select MIGHT_HAVE_CACHE_L2X0
908 Support for ST-Ericsson's Ux500 architecture
911 bool "STMicroelectronics Nomadik"
916 select GENERIC_CLOCKEVENTS
918 select MIGHT_HAVE_CACHE_L2X0
919 select ARCH_REQUIRE_GPIOLIB
921 Support for the Nomadik platform by ST-Ericsson
925 select GENERIC_CLOCKEVENTS
926 select ARCH_REQUIRE_GPIOLIB
930 select GENERIC_ALLOCATOR
931 select GENERIC_IRQ_CHIP
932 select ARCH_HAS_HOLES_MEMORYMODEL
934 Support for TI's DaVinci platform.
939 select ARCH_REQUIRE_GPIOLIB
940 select ARCH_HAS_CPUFREQ
942 select GENERIC_CLOCKEVENTS
943 select ARCH_HAS_HOLES_MEMORYMODEL
945 Support for TI's OMAP platform (OMAP1/2/3/4).
950 select ARCH_REQUIRE_GPIOLIB
953 select GENERIC_CLOCKEVENTS
956 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
959 bool "VIA/WonderMedia 85xx"
962 select ARCH_HAS_CPUFREQ
963 select GENERIC_CLOCKEVENTS
964 select ARCH_REQUIRE_GPIOLIB
967 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
970 bool "Xilinx Zynq ARM Cortex A9 Platform"
972 select GENERIC_CLOCKEVENTS
977 select MIGHT_HAVE_CACHE_L2X0
980 Support for Xilinx Zynq ARM Cortex A9 Platform
984 # This is sorted alphabetically by mach-* pathname. However, plat-*
985 # Kconfigs may be included either alphabetically (according to the
986 # plat- suffix) or along side the corresponding mach-* source.
988 source "arch/arm/mach-at91/Kconfig"
990 source "arch/arm/mach-bcmring/Kconfig"
992 source "arch/arm/mach-clps711x/Kconfig"
994 source "arch/arm/mach-cns3xxx/Kconfig"
996 source "arch/arm/mach-davinci/Kconfig"
998 source "arch/arm/mach-dove/Kconfig"
1000 source "arch/arm/mach-ep93xx/Kconfig"
1002 source "arch/arm/mach-footbridge/Kconfig"
1004 source "arch/arm/mach-gemini/Kconfig"
1006 source "arch/arm/mach-h720x/Kconfig"
1008 source "arch/arm/mach-integrator/Kconfig"
1010 source "arch/arm/mach-iop32x/Kconfig"
1012 source "arch/arm/mach-iop33x/Kconfig"
1014 source "arch/arm/mach-iop13xx/Kconfig"
1016 source "arch/arm/mach-ixp4xx/Kconfig"
1018 source "arch/arm/mach-kirkwood/Kconfig"
1020 source "arch/arm/mach-ks8695/Kconfig"
1022 source "arch/arm/mach-lpc32xx/Kconfig"
1024 source "arch/arm/mach-msm/Kconfig"
1026 source "arch/arm/mach-mv78xx0/Kconfig"
1028 source "arch/arm/plat-mxc/Kconfig"
1030 source "arch/arm/mach-mxs/Kconfig"
1032 source "arch/arm/mach-netx/Kconfig"
1034 source "arch/arm/mach-nomadik/Kconfig"
1035 source "arch/arm/plat-nomadik/Kconfig"
1037 source "arch/arm/plat-omap/Kconfig"
1039 source "arch/arm/mach-omap1/Kconfig"
1041 source "arch/arm/mach-omap2/Kconfig"
1043 source "arch/arm/mach-orion5x/Kconfig"
1045 source "arch/arm/mach-pxa/Kconfig"
1046 source "arch/arm/plat-pxa/Kconfig"
1048 source "arch/arm/mach-mmp/Kconfig"
1050 source "arch/arm/mach-realview/Kconfig"
1052 source "arch/arm/mach-sa1100/Kconfig"
1054 source "arch/arm/plat-samsung/Kconfig"
1055 source "arch/arm/plat-s3c24xx/Kconfig"
1056 source "arch/arm/plat-s5p/Kconfig"
1058 source "arch/arm/plat-spear/Kconfig"
1060 source "arch/arm/mach-s3c24xx/Kconfig"
1062 source "arch/arm/mach-s3c2412/Kconfig"
1063 source "arch/arm/mach-s3c2440/Kconfig"
1067 source "arch/arm/mach-s3c64xx/Kconfig"
1070 source "arch/arm/mach-s5p64x0/Kconfig"
1072 source "arch/arm/mach-s5pc100/Kconfig"
1074 source "arch/arm/mach-s5pv210/Kconfig"
1076 source "arch/arm/mach-exynos/Kconfig"
1078 source "arch/arm/mach-shmobile/Kconfig"
1080 source "arch/arm/mach-tegra/Kconfig"
1082 source "arch/arm/mach-u300/Kconfig"
1084 source "arch/arm/mach-ux500/Kconfig"
1086 source "arch/arm/mach-versatile/Kconfig"
1088 source "arch/arm/mach-vexpress/Kconfig"
1089 source "arch/arm/plat-versatile/Kconfig"
1091 source "arch/arm/mach-vt8500/Kconfig"
1093 source "arch/arm/mach-w90x900/Kconfig"
1095 # Definitions to make life easier
1101 select GENERIC_CLOCKEVENTS
1106 select GENERIC_IRQ_CHIP
1111 config PLAT_VERSATILE
1114 config ARM_TIMER_SP804
1117 select HAVE_SCHED_CLOCK
1119 source arch/arm/mm/Kconfig
1123 default 16 if ARCH_EP93XX
1127 bool "Enable iWMMXt support"
1128 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1129 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1131 Enable support for iWMMXt context switching at run time if
1132 running on a CPU that supports it.
1136 depends on CPU_XSCALE
1140 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1141 (!ARCH_OMAP3 || OMAP3_EMU)
1145 config MULTI_IRQ_HANDLER
1148 Allow each machine to specify it's own IRQ handler at run time.
1151 source "arch/arm/Kconfig-nommu"
1154 config ARM_ERRATA_326103
1155 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1158 Executing a SWP instruction to read-only memory does not set bit 11
1159 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1160 treat the access as a read, preventing a COW from occurring and
1161 causing the faulting task to livelock.
1163 config ARM_ERRATA_411920
1164 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1165 depends on CPU_V6 || CPU_V6K
1167 Invalidation of the Instruction Cache operation can
1168 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1169 It does not affect the MPCore. This option enables the ARM Ltd.
1170 recommended workaround.
1172 config ARM_ERRATA_430973
1173 bool "ARM errata: Stale prediction on replaced interworking branch"
1176 This option enables the workaround for the 430973 Cortex-A8
1177 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1178 interworking branch is replaced with another code sequence at the
1179 same virtual address, whether due to self-modifying code or virtual
1180 to physical address re-mapping, Cortex-A8 does not recover from the
1181 stale interworking branch prediction. This results in Cortex-A8
1182 executing the new code sequence in the incorrect ARM or Thumb state.
1183 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1184 and also flushes the branch target cache at every context switch.
1185 Note that setting specific bits in the ACTLR register may not be
1186 available in non-secure mode.
1188 config ARM_ERRATA_458693
1189 bool "ARM errata: Processor deadlock when a false hazard is created"
1192 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1193 erratum. For very specific sequences of memory operations, it is
1194 possible for a hazard condition intended for a cache line to instead
1195 be incorrectly associated with a different cache line. This false
1196 hazard might then cause a processor deadlock. The workaround enables
1197 the L1 caching of the NEON accesses and disables the PLD instruction
1198 in the ACTLR register. Note that setting specific bits in the ACTLR
1199 register may not be available in non-secure mode.
1201 config ARM_ERRATA_460075
1202 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1205 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1206 erratum. Any asynchronous access to the L2 cache may encounter a
1207 situation in which recent store transactions to the L2 cache are lost
1208 and overwritten with stale memory contents from external memory. The
1209 workaround disables the write-allocate mode for the L2 cache via the
1210 ACTLR register. Note that setting specific bits in the ACTLR register
1211 may not be available in non-secure mode.
1213 config ARM_ERRATA_742230
1214 bool "ARM errata: DMB operation may be faulty"
1215 depends on CPU_V7 && SMP
1217 This option enables the workaround for the 742230 Cortex-A9
1218 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1219 between two write operations may not ensure the correct visibility
1220 ordering of the two writes. This workaround sets a specific bit in
1221 the diagnostic register of the Cortex-A9 which causes the DMB
1222 instruction to behave as a DSB, ensuring the correct behaviour of
1225 config ARM_ERRATA_742231
1226 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1227 depends on CPU_V7 && SMP
1229 This option enables the workaround for the 742231 Cortex-A9
1230 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1231 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1232 accessing some data located in the same cache line, may get corrupted
1233 data due to bad handling of the address hazard when the line gets
1234 replaced from one of the CPUs at the same time as another CPU is
1235 accessing it. This workaround sets specific bits in the diagnostic
1236 register of the Cortex-A9 which reduces the linefill issuing
1237 capabilities of the processor.
1239 config PL310_ERRATA_588369
1240 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1241 depends on CACHE_L2X0
1243 The PL310 L2 cache controller implements three types of Clean &
1244 Invalidate maintenance operations: by Physical Address
1245 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1246 They are architecturally defined to behave as the execution of a
1247 clean operation followed immediately by an invalidate operation,
1248 both performing to the same memory location. This functionality
1249 is not correctly implemented in PL310 as clean lines are not
1250 invalidated as a result of these operations.
1252 config ARM_ERRATA_720789
1253 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1256 This option enables the workaround for the 720789 Cortex-A9 (prior to
1257 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1258 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1259 As a consequence of this erratum, some TLB entries which should be
1260 invalidated are not, resulting in an incoherency in the system page
1261 tables. The workaround changes the TLB flushing routines to invalidate
1262 entries regardless of the ASID.
1264 config PL310_ERRATA_727915
1265 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1266 depends on CACHE_L2X0
1268 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1269 operation (offset 0x7FC). This operation runs in background so that
1270 PL310 can handle normal accesses while it is in progress. Under very
1271 rare circumstances, due to this erratum, write data can be lost when
1272 PL310 treats a cacheable write transaction during a Clean &
1273 Invalidate by Way operation.
1275 config ARM_ERRATA_743622
1276 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1279 This option enables the workaround for the 743622 Cortex-A9
1280 (r2p*) erratum. Under very rare conditions, a faulty
1281 optimisation in the Cortex-A9 Store Buffer may lead to data
1282 corruption. This workaround sets a specific bit in the diagnostic
1283 register of the Cortex-A9 which disables the Store Buffer
1284 optimisation, preventing the defect from occurring. This has no
1285 visible impact on the overall performance or power consumption of the
1288 config ARM_ERRATA_751472
1289 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1292 This option enables the workaround for the 751472 Cortex-A9 (prior
1293 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1294 completion of a following broadcasted operation if the second
1295 operation is received by a CPU before the ICIALLUIS has completed,
1296 potentially leading to corrupted entries in the cache or TLB.
1298 config PL310_ERRATA_753970
1299 bool "PL310 errata: cache sync operation may be faulty"
1300 depends on CACHE_PL310
1302 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1304 Under some condition the effect of cache sync operation on
1305 the store buffer still remains when the operation completes.
1306 This means that the store buffer is always asked to drain and
1307 this prevents it from merging any further writes. The workaround
1308 is to replace the normal offset of cache sync operation (0x730)
1309 by another offset targeting an unmapped PL310 register 0x740.
1310 This has the same effect as the cache sync operation: store buffer
1311 drain and waiting for all buffers empty.
1313 config ARM_ERRATA_754322
1314 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1317 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1318 r3p*) erratum. A speculative memory access may cause a page table walk
1319 which starts prior to an ASID switch but completes afterwards. This
1320 can populate the micro-TLB with a stale entry which may be hit with
1321 the new ASID. This workaround places two dsb instructions in the mm
1322 switching code so that no page table walks can cross the ASID switch.
1324 config ARM_ERRATA_754327
1325 bool "ARM errata: no automatic Store Buffer drain"
1326 depends on CPU_V7 && SMP
1328 This option enables the workaround for the 754327 Cortex-A9 (prior to
1329 r2p0) erratum. The Store Buffer does not have any automatic draining
1330 mechanism and therefore a livelock may occur if an external agent
1331 continuously polls a memory location waiting to observe an update.
1332 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1333 written polling loops from denying visibility of updates to memory.
1335 config ARM_ERRATA_364296
1336 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1337 depends on CPU_V6 && !SMP
1339 This options enables the workaround for the 364296 ARM1136
1340 r0p2 erratum (possible cache data corruption with
1341 hit-under-miss enabled). It sets the undocumented bit 31 in
1342 the auxiliary control register and the FI bit in the control
1343 register, thus disabling hit-under-miss without putting the
1344 processor into full low interrupt latency mode. ARM11MPCore
1347 config ARM_ERRATA_764369
1348 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1349 depends on CPU_V7 && SMP
1351 This option enables the workaround for erratum 764369
1352 affecting Cortex-A9 MPCore with two or more processors (all
1353 current revisions). Under certain timing circumstances, a data
1354 cache line maintenance operation by MVA targeting an Inner
1355 Shareable memory region may fail to proceed up to either the
1356 Point of Coherency or to the Point of Unification of the
1357 system. This workaround adds a DSB instruction before the
1358 relevant cache maintenance functions and sets a specific bit
1359 in the diagnostic control register of the SCU.
1361 config PL310_ERRATA_769419
1362 bool "PL310 errata: no automatic Store Buffer drain"
1363 depends on CACHE_L2X0
1365 On revisions of the PL310 prior to r3p2, the Store Buffer does
1366 not automatically drain. This can cause normal, non-cacheable
1367 writes to be retained when the memory system is idle, leading
1368 to suboptimal I/O performance for drivers using coherent DMA.
1369 This option adds a write barrier to the cpu_idle loop so that,
1370 on systems with an outer cache, the store buffer is drained
1375 source "arch/arm/common/Kconfig"
1385 Find out whether you have ISA slots on your motherboard. ISA is the
1386 name of a bus system, i.e. the way the CPU talks to the other stuff
1387 inside your box. Other bus systems are PCI, EISA, MicroChannel
1388 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1389 newer boards don't support it. If you have ISA, say Y, otherwise N.
1391 # Select ISA DMA controller support
1396 # Select ISA DMA interface
1401 bool "PCI support" if MIGHT_HAVE_PCI
1403 Find out whether you have a PCI motherboard. PCI is the name of a
1404 bus system, i.e. the way the CPU talks to the other stuff inside
1405 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1406 VESA. If you have PCI, say Y, otherwise N.
1412 config PCI_NANOENGINE
1413 bool "BSE nanoEngine PCI support"
1414 depends on SA1100_NANOENGINE
1416 Enable PCI on the BSE nanoEngine board.
1421 # Select the host bridge type
1422 config PCI_HOST_VIA82C505
1424 depends on PCI && ARCH_SHARK
1427 config PCI_HOST_ITE8152
1429 depends on PCI && MACH_ARMCORE
1433 source "drivers/pci/Kconfig"
1435 source "drivers/pcmcia/Kconfig"
1439 menu "Kernel Features"
1441 source "kernel/time/Kconfig"
1446 This option should be selected by machines which have an SMP-
1449 The only effect of this option is to make the SMP-related
1450 options available to the user for configuration.
1453 bool "Symmetric Multi-Processing"
1454 depends on CPU_V6K || CPU_V7
1455 depends on GENERIC_CLOCKEVENTS
1458 select USE_GENERIC_SMP_HELPERS
1459 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1461 This enables support for systems with more than one CPU. If you have
1462 a system with only one CPU, like most personal computers, say N. If
1463 you have a system with more than one CPU, say Y.
1465 If you say N here, the kernel will run on single and multiprocessor
1466 machines, but will use only one CPU of a multiprocessor machine. If
1467 you say Y here, the kernel will run on many, but not all, single
1468 processor machines. On a single processor machine, the kernel will
1469 run faster if you say N here.
1471 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1472 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1473 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1475 If you don't know what to do here, say N.
1478 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1479 depends on EXPERIMENTAL
1480 depends on SMP && !XIP_KERNEL
1483 SMP kernels contain instructions which fail on non-SMP processors.
1484 Enabling this option allows the kernel to modify itself to make
1485 these instructions safe. Disabling it allows about 1K of space
1488 If you don't know what to do here, say Y.
1490 config ARM_CPU_TOPOLOGY
1491 bool "Support cpu topology definition"
1492 depends on SMP && CPU_V7
1495 Support ARM cpu topology definition. The MPIDR register defines
1496 affinity between processors which is then used to describe the cpu
1497 topology of an ARM System.
1500 bool "Multi-core scheduler support"
1501 depends on ARM_CPU_TOPOLOGY
1503 Multi-core scheduler support improves the CPU scheduler's decision
1504 making when dealing with multi-core CPU chips at a cost of slightly
1505 increased overhead in some places. If unsure say N here.
1508 bool "SMT scheduler support"
1509 depends on ARM_CPU_TOPOLOGY
1511 Improves the CPU scheduler's decision making when dealing with
1512 MultiThreading at a cost of slightly increased overhead in some
1513 places. If unsure say N here.
1518 This option enables support for the ARM system coherency unit
1520 config ARM_ARCH_TIMER
1521 bool "Architected timer support"
1524 This option enables support for the ARM architected timer
1530 This options enables support for the ARM timer and watchdog unit
1533 prompt "Memory split"
1536 Select the desired split between kernel and user memory.
1538 If you are not absolutely sure what you are doing, leave this
1542 bool "3G/1G user/kernel split"
1544 bool "2G/2G user/kernel split"
1546 bool "1G/3G user/kernel split"
1551 default 0x40000000 if VMSPLIT_1G
1552 default 0x80000000 if VMSPLIT_2G
1556 int "Maximum number of CPUs (2-32)"
1562 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1563 depends on SMP && HOTPLUG && EXPERIMENTAL
1565 Say Y here to experiment with turning CPUs off and on. CPUs
1566 can be controlled through /sys/devices/system/cpu.
1569 bool "Use local timer interrupts"
1572 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1574 Enable support for local timers on SMP platforms, rather then the
1575 legacy IPI broadcast method. Local timers allows the system
1576 accounting to be spread across the timer interval, preventing a
1577 "thundering herd" at every timer tick.
1581 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1582 default 355 if ARCH_U8500
1583 default 264 if MACH_H4700
1586 Maximum number of GPIOs in the system.
1588 If unsure, leave the default value.
1590 source kernel/Kconfig.preempt
1594 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1595 ARCH_S5PV210 || ARCH_EXYNOS4
1596 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1597 default AT91_TIMER_HZ if ARCH_AT91
1598 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1601 config THUMB2_KERNEL
1602 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1603 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1605 select ARM_ASM_UNIFIED
1608 By enabling this option, the kernel will be compiled in
1609 Thumb-2 mode. A compiler/assembler that understand the unified
1610 ARM-Thumb syntax is needed.
1614 config THUMB2_AVOID_R_ARM_THM_JUMP11
1615 bool "Work around buggy Thumb-2 short branch relocations in gas"
1616 depends on THUMB2_KERNEL && MODULES
1619 Various binutils versions can resolve Thumb-2 branches to
1620 locally-defined, preemptible global symbols as short-range "b.n"
1621 branch instructions.
1623 This is a problem, because there's no guarantee the final
1624 destination of the symbol, or any candidate locations for a
1625 trampoline, are within range of the branch. For this reason, the
1626 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1627 relocation in modules at all, and it makes little sense to add
1630 The symptom is that the kernel fails with an "unsupported
1631 relocation" error when loading some modules.
1633 Until fixed tools are available, passing
1634 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1635 code which hits this problem, at the cost of a bit of extra runtime
1636 stack usage in some cases.
1638 The problem is described in more detail at:
1639 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1641 Only Thumb-2 kernels are affected.
1643 Unless you are sure your tools don't have this problem, say Y.
1645 config ARM_ASM_UNIFIED
1649 bool "Use the ARM EABI to compile the kernel"
1651 This option allows for the kernel to be compiled using the latest
1652 ARM ABI (aka EABI). This is only useful if you are using a user
1653 space environment that is also compiled with EABI.
1655 Since there are major incompatibilities between the legacy ABI and
1656 EABI, especially with regard to structure member alignment, this
1657 option also changes the kernel syscall calling convention to
1658 disambiguate both ABIs and allow for backward compatibility support
1659 (selected with CONFIG_OABI_COMPAT).
1661 To use this you need GCC version 4.0.0 or later.
1664 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1665 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1668 This option preserves the old syscall interface along with the
1669 new (ARM EABI) one. It also provides a compatibility layer to
1670 intercept syscalls that have structure arguments which layout
1671 in memory differs between the legacy ABI and the new ARM EABI
1672 (only for non "thumb" binaries). This option adds a tiny
1673 overhead to all syscalls and produces a slightly larger kernel.
1674 If you know you'll be using only pure EABI user space then you
1675 can say N here. If this option is not selected and you attempt
1676 to execute a legacy ABI binary then the result will be
1677 UNPREDICTABLE (in fact it can be predicted that it won't work
1678 at all). If in doubt say Y.
1680 config ARCH_HAS_HOLES_MEMORYMODEL
1683 config ARCH_SPARSEMEM_ENABLE
1686 config ARCH_SPARSEMEM_DEFAULT
1687 def_bool ARCH_SPARSEMEM_ENABLE
1689 config ARCH_SELECT_MEMORY_MODEL
1690 def_bool ARCH_SPARSEMEM_ENABLE
1692 config HAVE_ARCH_PFN_VALID
1693 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1696 bool "High Memory Support"
1699 The address space of ARM processors is only 4 Gigabytes large
1700 and it has to accommodate user address space, kernel address
1701 space as well as some memory mapped IO. That means that, if you
1702 have a large amount of physical memory and/or IO, not all of the
1703 memory can be "permanently mapped" by the kernel. The physical
1704 memory that is not permanently mapped is called "high memory".
1706 Depending on the selected kernel/user memory split, minimum
1707 vmalloc space and actual amount of RAM, you may not need this
1708 option which should result in a slightly faster kernel.
1713 bool "Allocate 2nd-level pagetables from highmem"
1716 config HW_PERF_EVENTS
1717 bool "Enable hardware performance counter support for perf events"
1718 depends on PERF_EVENTS && CPU_HAS_PMU
1721 Enable hardware performance counter support for perf events. If
1722 disabled, perf events will use software events only.
1726 config FORCE_MAX_ZONEORDER
1727 int "Maximum zone order" if ARCH_SHMOBILE
1728 range 11 64 if ARCH_SHMOBILE
1729 default "9" if SA1111
1732 The kernel memory allocator divides physically contiguous memory
1733 blocks into "zones", where each zone is a power of two number of
1734 pages. This option selects the largest power of two that the kernel
1735 keeps in the memory allocator. If you need to allocate very large
1736 blocks of physically contiguous memory, then you may need to
1737 increase this value.
1739 This config option is actually maximum order plus one. For example,
1740 a value of 11 means that the largest free memory block is 2^10 pages.
1743 bool "Timer and CPU usage LEDs"
1744 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1745 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1746 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1747 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1748 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1749 ARCH_AT91 || ARCH_DAVINCI || \
1750 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1752 If you say Y here, the LEDs on your machine will be used
1753 to provide useful information about your current system status.
1755 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1756 be able to select which LEDs are active using the options below. If
1757 you are compiling a kernel for the EBSA-110 or the LART however, the
1758 red LED will simply flash regularly to indicate that the system is
1759 still functional. It is safe to say Y here if you have a CATS
1760 system, but the driver will do nothing.
1763 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1764 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1765 || MACH_OMAP_PERSEUS2
1767 depends on !GENERIC_CLOCKEVENTS
1768 default y if ARCH_EBSA110
1770 If you say Y here, one of the system LEDs (the green one on the
1771 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1772 will flash regularly to indicate that the system is still
1773 operational. This is mainly useful to kernel hackers who are
1774 debugging unstable kernels.
1776 The LART uses the same LED for both Timer LED and CPU usage LED
1777 functions. You may choose to use both, but the Timer LED function
1778 will overrule the CPU usage LED.
1781 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1783 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1784 || MACH_OMAP_PERSEUS2
1787 If you say Y here, the red LED will be used to give a good real
1788 time indication of CPU usage, by lighting whenever the idle task
1789 is not currently executing.
1791 The LART uses the same LED for both Timer LED and CPU usage LED
1792 functions. You may choose to use both, but the Timer LED function
1793 will overrule the CPU usage LED.
1795 config ALIGNMENT_TRAP
1797 depends on CPU_CP15_MMU
1798 default y if !ARCH_EBSA110
1799 select HAVE_PROC_CPU if PROC_FS
1801 ARM processors cannot fetch/store information which is not
1802 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1803 address divisible by 4. On 32-bit ARM processors, these non-aligned
1804 fetch/store instructions will be emulated in software if you say
1805 here, which has a severe performance impact. This is necessary for
1806 correct operation of some network protocols. With an IP-only
1807 configuration it is safe to say N, otherwise say Y.
1809 config UACCESS_WITH_MEMCPY
1810 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1811 depends on MMU && EXPERIMENTAL
1812 default y if CPU_FEROCEON
1814 Implement faster copy_to_user and clear_user methods for CPU
1815 cores where a 8-word STM instruction give significantly higher
1816 memory write throughput than a sequence of individual 32bit stores.
1818 A possible side effect is a slight increase in scheduling latency
1819 between threads sharing the same address space if they invoke
1820 such copy operations with large buffers.
1822 However, if the CPU data cache is using a write-allocate mode,
1823 this option is unlikely to provide any performance gain.
1827 prompt "Enable seccomp to safely compute untrusted bytecode"
1829 This kernel feature is useful for number crunching applications
1830 that may need to compute untrusted bytecode during their
1831 execution. By using pipes or other transports made available to
1832 the process as file descriptors supporting the read/write
1833 syscalls, it's possible to isolate those applications in
1834 their own address space using seccomp. Once seccomp is
1835 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1836 and the task is only allowed to execute a few safe syscalls
1837 defined by each seccomp mode.
1839 config CC_STACKPROTECTOR
1840 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1841 depends on EXPERIMENTAL
1843 This option turns on the -fstack-protector GCC feature. This
1844 feature puts, at the beginning of functions, a canary value on
1845 the stack just before the return address, and validates
1846 the value just before actually returning. Stack based buffer
1847 overflows (that need to overwrite this return address) now also
1848 overwrite the canary, which gets detected and the attack is then
1849 neutralized via a kernel panic.
1850 This feature requires gcc version 4.2 or above.
1852 config DEPRECATED_PARAM_STRUCT
1853 bool "Provide old way to pass kernel parameters"
1855 This was deprecated in 2001 and announced to live on for 5 years.
1856 Some old boot loaders still use this way.
1863 bool "Flattened Device Tree support"
1865 select OF_EARLY_FLATTREE
1868 Include support for flattened device tree machine descriptions.
1870 # Compressed boot loader in ROM. Yes, we really want to ask about
1871 # TEXT and BSS so we preserve their values in the config files.
1872 config ZBOOT_ROM_TEXT
1873 hex "Compressed ROM boot loader base address"
1876 The physical address at which the ROM-able zImage is to be
1877 placed in the target. Platforms which normally make use of
1878 ROM-able zImage formats normally set this to a suitable
1879 value in their defconfig file.
1881 If ZBOOT_ROM is not enabled, this has no effect.
1883 config ZBOOT_ROM_BSS
1884 hex "Compressed ROM boot loader BSS address"
1887 The base address of an area of read/write memory in the target
1888 for the ROM-able zImage which must be available while the
1889 decompressor is running. It must be large enough to hold the
1890 entire decompressed kernel plus an additional 128 KiB.
1891 Platforms which normally make use of ROM-able zImage formats
1892 normally set this to a suitable value in their defconfig file.
1894 If ZBOOT_ROM is not enabled, this has no effect.
1897 bool "Compressed boot loader in ROM/flash"
1898 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1900 Say Y here if you intend to execute your compressed kernel image
1901 (zImage) directly from ROM or flash. If unsure, say N.
1904 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1905 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1906 default ZBOOT_ROM_NONE
1908 Include experimental SD/MMC loading code in the ROM-able zImage.
1909 With this enabled it is possible to write the ROM-able zImage
1910 kernel image to an MMC or SD card and boot the kernel straight
1911 from the reset vector. At reset the processor Mask ROM will load
1912 the first part of the ROM-able zImage which in turn loads the
1913 rest the kernel image to RAM.
1915 config ZBOOT_ROM_NONE
1916 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1918 Do not load image from SD or MMC
1920 config ZBOOT_ROM_MMCIF
1921 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1923 Load image from MMCIF hardware block.
1925 config ZBOOT_ROM_SH_MOBILE_SDHI
1926 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1928 Load image from SDHI hardware block
1932 config ARM_APPENDED_DTB
1933 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1934 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1936 With this option, the boot code will look for a device tree binary
1937 (DTB) appended to zImage
1938 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1940 This is meant as a backward compatibility convenience for those
1941 systems with a bootloader that can't be upgraded to accommodate
1942 the documented boot protocol using a device tree.
1944 Beware that there is very little in terms of protection against
1945 this option being confused by leftover garbage in memory that might
1946 look like a DTB header after a reboot if no actual DTB is appended
1947 to zImage. Do not leave this option active in a production kernel
1948 if you don't intend to always append a DTB. Proper passing of the
1949 location into r2 of a bootloader provided DTB is always preferable
1952 config ARM_ATAG_DTB_COMPAT
1953 bool "Supplement the appended DTB with traditional ATAG information"
1954 depends on ARM_APPENDED_DTB
1956 Some old bootloaders can't be updated to a DTB capable one, yet
1957 they provide ATAGs with memory configuration, the ramdisk address,
1958 the kernel cmdline string, etc. Such information is dynamically
1959 provided by the bootloader and can't always be stored in a static
1960 DTB. To allow a device tree enabled kernel to be used with such
1961 bootloaders, this option allows zImage to extract the information
1962 from the ATAG list and store it at run time into the appended DTB.
1965 string "Default kernel command string"
1968 On some architectures (EBSA110 and CATS), there is currently no way
1969 for the boot loader to pass arguments to the kernel. For these
1970 architectures, you should supply some command-line options at build
1971 time by entering them here. As a minimum, you should specify the
1972 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1975 prompt "Kernel command line type" if CMDLINE != ""
1976 default CMDLINE_FROM_BOOTLOADER
1978 config CMDLINE_FROM_BOOTLOADER
1979 bool "Use bootloader kernel arguments if available"
1981 Uses the command-line options passed by the boot loader. If
1982 the boot loader doesn't provide any, the default kernel command
1983 string provided in CMDLINE will be used.
1985 config CMDLINE_EXTEND
1986 bool "Extend bootloader kernel arguments"
1988 The command-line arguments provided by the boot loader will be
1989 appended to the default kernel command string.
1991 config CMDLINE_FORCE
1992 bool "Always use the default kernel command string"
1994 Always use the default kernel command string, even if the boot
1995 loader passes other arguments to the kernel.
1996 This is useful if you cannot or don't want to change the
1997 command-line options your boot loader passes to the kernel.
2001 bool "Kernel Execute-In-Place from ROM"
2002 depends on !ZBOOT_ROM && !ARM_LPAE
2004 Execute-In-Place allows the kernel to run from non-volatile storage
2005 directly addressable by the CPU, such as NOR flash. This saves RAM
2006 space since the text section of the kernel is not loaded from flash
2007 to RAM. Read-write sections, such as the data section and stack,
2008 are still copied to RAM. The XIP kernel is not compressed since
2009 it has to run directly from flash, so it will take more space to
2010 store it. The flash address used to link the kernel object files,
2011 and for storing it, is configuration dependent. Therefore, if you
2012 say Y here, you must know the proper physical address where to
2013 store the kernel image depending on your own flash memory usage.
2015 Also note that the make target becomes "make xipImage" rather than
2016 "make zImage" or "make Image". The final kernel binary to put in
2017 ROM memory will be arch/arm/boot/xipImage.
2021 config XIP_PHYS_ADDR
2022 hex "XIP Kernel Physical Location"
2023 depends on XIP_KERNEL
2024 default "0x00080000"
2026 This is the physical address in your flash memory the kernel will
2027 be linked for and stored to. This address is dependent on your
2031 bool "Kexec system call (EXPERIMENTAL)"
2032 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2034 kexec is a system call that implements the ability to shutdown your
2035 current kernel, and to start another kernel. It is like a reboot
2036 but it is independent of the system firmware. And like a reboot
2037 you can start any kernel with it, not just Linux.
2039 It is an ongoing process to be certain the hardware in a machine
2040 is properly shutdown, so do not be surprised if this code does not
2041 initially work for you. It may help to enable device hotplugging
2045 bool "Export atags in procfs"
2049 Should the atags used to boot the kernel be exported in an "atags"
2050 file in procfs. Useful with kexec.
2053 bool "Build kdump crash kernel (EXPERIMENTAL)"
2054 depends on EXPERIMENTAL
2056 Generate crash dump after being started by kexec. This should
2057 be normally only set in special crash dump kernels which are
2058 loaded in the main kernel with kexec-tools into a specially
2059 reserved region and then later executed after a crash by
2060 kdump/kexec. The crash dump kernel must be compiled to a
2061 memory address not used by the main kernel
2063 For more details see Documentation/kdump/kdump.txt
2065 config AUTO_ZRELADDR
2066 bool "Auto calculation of the decompressed kernel image address"
2067 depends on !ZBOOT_ROM && !ARCH_U300
2069 ZRELADDR is the physical address where the decompressed kernel
2070 image will be placed. If AUTO_ZRELADDR is selected, the address
2071 will be determined at run-time by masking the current IP with
2072 0xf8000000. This assumes the zImage being placed in the first 128MB
2073 from start of memory.
2077 menu "CPU Power Management"
2081 source "drivers/cpufreq/Kconfig"
2084 tristate "CPUfreq driver for i.MX CPUs"
2085 depends on ARCH_MXC && CPU_FREQ
2087 This enables the CPUfreq driver for i.MX CPUs.
2089 config CPU_FREQ_SA1100
2092 config CPU_FREQ_SA1110
2095 config CPU_FREQ_INTEGRATOR
2096 tristate "CPUfreq driver for ARM Integrator CPUs"
2097 depends on ARCH_INTEGRATOR && CPU_FREQ
2100 This enables the CPUfreq driver for ARM Integrator CPUs.
2102 For details, take a look at <file:Documentation/cpu-freq>.
2108 depends on CPU_FREQ && ARCH_PXA && PXA25x
2110 select CPU_FREQ_TABLE
2111 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2116 Internal configuration node for common cpufreq on Samsung SoC
2118 config CPU_FREQ_S3C24XX
2119 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2120 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2123 This enables the CPUfreq driver for the Samsung S3C24XX family
2126 For details, take a look at <file:Documentation/cpu-freq>.
2130 config CPU_FREQ_S3C24XX_PLL
2131 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2132 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2134 Compile in support for changing the PLL frequency from the
2135 S3C24XX series CPUfreq driver. The PLL takes time to settle
2136 after a frequency change, so by default it is not enabled.
2138 This also means that the PLL tables for the selected CPU(s) will
2139 be built which may increase the size of the kernel image.
2141 config CPU_FREQ_S3C24XX_DEBUG
2142 bool "Debug CPUfreq Samsung driver core"
2143 depends on CPU_FREQ_S3C24XX
2145 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2147 config CPU_FREQ_S3C24XX_IODEBUG
2148 bool "Debug CPUfreq Samsung driver IO timing"
2149 depends on CPU_FREQ_S3C24XX
2151 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2153 config CPU_FREQ_S3C24XX_DEBUGFS
2154 bool "Export debugfs for CPUFreq"
2155 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2157 Export status information via debugfs.
2161 source "drivers/cpuidle/Kconfig"
2165 menu "Floating point emulation"
2167 comment "At least one emulation must be selected"
2170 bool "NWFPE math emulation"
2171 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2173 Say Y to include the NWFPE floating point emulator in the kernel.
2174 This is necessary to run most binaries. Linux does not currently
2175 support floating point hardware so you need to say Y here even if
2176 your machine has an FPA or floating point co-processor podule.
2178 You may say N here if you are going to load the Acorn FPEmulator
2179 early in the bootup.
2182 bool "Support extended precision"
2183 depends on FPE_NWFPE
2185 Say Y to include 80-bit support in the kernel floating-point
2186 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2187 Note that gcc does not generate 80-bit operations by default,
2188 so in most cases this option only enlarges the size of the
2189 floating point emulator without any good reason.
2191 You almost surely want to say N here.
2194 bool "FastFPE math emulation (EXPERIMENTAL)"
2195 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2197 Say Y here to include the FAST floating point emulator in the kernel.
2198 This is an experimental much faster emulator which now also has full
2199 precision for the mantissa. It does not support any exceptions.
2200 It is very simple, and approximately 3-6 times faster than NWFPE.
2202 It should be sufficient for most programs. It may be not suitable
2203 for scientific calculations, but you have to check this for yourself.
2204 If you do not feel you need a faster FP emulation you should better
2208 bool "VFP-format floating point maths"
2209 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2211 Say Y to include VFP support code in the kernel. This is needed
2212 if your hardware includes a VFP unit.
2214 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2215 release notes and additional status information.
2217 Say N if your target does not have VFP hardware.
2225 bool "Advanced SIMD (NEON) Extension support"
2226 depends on VFPv3 && CPU_V7
2228 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2233 menu "Userspace binary formats"
2235 source "fs/Kconfig.binfmt"
2238 tristate "RISC OS personality"
2241 Say Y here to include the kernel code necessary if you want to run
2242 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2243 experimental; if this sounds frightening, say N and sleep in peace.
2244 You can also say M here to compile this support as a module (which
2245 will be called arthur).
2249 menu "Power management options"
2251 source "kernel/power/Kconfig"
2253 config ARCH_SUSPEND_POSSIBLE
2254 depends on !ARCH_S5PC100 && !ARCH_TEGRA
2255 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2256 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2259 config ARM_CPU_SUSPEND
2264 source "net/Kconfig"
2266 source "drivers/Kconfig"
2270 source "arch/arm/Kconfig.debug"
2272 source "security/Kconfig"
2274 source "crypto/Kconfig"
2276 source "lib/Kconfig"