2 * linux/arch/arm/boot/compressed/head.S
4 * Copyright (C) 1996-2002 Russell King
5 * Copyright (C) 2004 Hyok S. Choi (MPU support)
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/linkage.h>
16 * Note that these macros must not contain any code which is not
17 * 100% relocatable. Any attempt to do so will result in a crash.
18 * Please select one of the following when turning on debugging.
22 #if defined(CONFIG_DEBUG_ICEDCC)
24 #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
25 .macro loadsp, rb, tmp
28 mcr p14, 0, \ch, c0, c5, 0
30 #elif defined(CONFIG_CPU_XSCALE)
31 .macro loadsp, rb, tmp
34 mcr p14, 0, \ch, c8, c0, 0
37 .macro loadsp, rb, tmp
40 mcr p14, 0, \ch, c1, c0, 0
46 #include <mach/debug-macro.S>
52 #if defined(CONFIG_ARCH_SA1100)
53 .macro loadsp, rb, tmp
54 mov \rb, #0x80000000 @ physical base address
55 #ifdef CONFIG_DEBUG_LL_SER3
56 add \rb, \rb, #0x00050000 @ Ser3
58 add \rb, \rb, #0x00010000 @ Ser1
61 #elif defined(CONFIG_ARCH_S3C2410)
62 .macro loadsp, rb, tmp
64 add \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT
67 .macro loadsp, rb, tmp
85 .macro debug_reloc_start
88 kphex r6, 8 /* processor id */
90 kphex r7, 8 /* architecture id */
91 #ifdef CONFIG_CPU_CP15
93 mrc p15, 0, r0, c1, c0
94 kphex r0, 8 /* control reg */
97 kphex r5, 8 /* decompressed kernel start */
99 kphex r9, 8 /* decompressed kernel end */
101 kphex r4, 8 /* kernel execution address */
106 .macro debug_reloc_end
108 kphex r5, 8 /* end of kernel */
111 bl memdump /* dump 256 bytes at start of kernel */
115 .section ".start", #alloc, #execinstr
117 * sort out different calling conventions
120 .arm @ Always enter in ARM state
122 .type start,#function
128 THUMB( adr r12, BSYM(1f) )
131 .word 0x016f2818 @ Magic numbers to help the loader
132 .word start @ absolute load/run zImage address
133 .word _edata @ zImage end address
135 1: mov r7, r1 @ save architecture ID
136 mov r8, r2 @ save atags pointer
138 #ifndef __ARM_ARCH_2__
140 * Booting from Angel - need to enter SVC mode and disable
141 * FIQs/IRQs (numeric definitions from angel arm.h source).
142 * We only do this if we were in user mode on entry.
144 mrs r2, cpsr @ get current mode
145 tst r2, #3 @ not user?
147 mov r0, #0x17 @ angel_SWIreason_EnterSVC
148 ARM( swi 0x123456 ) @ angel_SWI_ARM
149 THUMB( svc 0xab ) @ angel_SWI_THUMB
151 mrs r2, cpsr @ turn off interrupts to
152 orr r2, r2, #0xc0 @ prevent angel from running
155 teqp pc, #0x0c000003 @ turn off interrupts
159 * Note that some cache flushing and other stuff may
160 * be needed here - is there an Angel SWI call for this?
164 * some architecture specific code can be inserted
165 * by the linker here, but it should preserve r7, r8, and r9.
170 #ifdef CONFIG_AUTO_ZRELADDR
171 @ determine final kernel image address
173 and r4, r4, #0xf8000000
174 add r4, r4, #TEXT_OFFSET
182 ldmia r0, {r1, r2, r3, r5, r6, r9, r11, r12}
186 * We might be running at a different address. We need
187 * to fix up various pointers.
189 sub r0, r0, r1 @ calculate the delta offset
190 add r5, r5, r0 @ _start
191 add r6, r6, r0 @ _edata
193 #ifndef CONFIG_ZBOOT_ROM
194 /* malloc space is above the relocated stack (64k max) */
196 add r10, sp, #0x10000
199 * With ZBOOT_ROM the bss/stack is non relocatable,
200 * but someone could still run this code from RAM,
201 * in which case our reference is _edata.
207 * Check to see if we will overwrite ourselves.
208 * r4 = final kernel address
209 * r5 = start of this image
210 * r9 = size of decompressed image
211 * r10 = end of this image, including bss/stack/malloc space if non XIP
214 * r4 + image length <= r5 -> OK
223 * Relocate ourselves past the end of the decompressed kernel.
224 * r5 = start of this image
226 * r10 = end of the decompressed kernel
227 * Because we always copy ahead, we need to do it from the end and go
228 * backward in case the source and destination overlap.
230 /* Round up to next 256-byte boundary. */
234 sub r9, r6, r5 @ size to copy
235 add r9, r9, #31 @ rounded up to a multiple
236 bic r9, r9, #31 @ ... of 32 bytes
240 1: ldmdb r6!, {r0 - r3, r10 - r12, lr}
242 stmdb r9!, {r0 - r3, r10 - r12, lr}
245 /* Preserve offset to relocated code. */
250 adr r0, BSYM(restart)
256 * If delta is zero, we are running at the address we were linked at.
260 * r4 = kernel execution address
261 * r7 = architecture ID
272 #ifndef CONFIG_ZBOOT_ROM
274 * If we're running fully PIC === CONFIG_ZBOOT_ROM = n,
275 * we need to fix up pointers into the BSS region.
276 * Note that the stack pointer has already been fixed up.
282 * Relocate all entries in the GOT table.
284 1: ldr r1, [r11, #0] @ relocate entries in the GOT
285 add r1, r1, r0 @ table. This fixes up the
286 str r1, [r11], #4 @ C references.
292 * Relocate entries in the GOT table. We only relocate
293 * the entries that are outside the (relocated) BSS region.
295 1: ldr r1, [r11, #0] @ relocate entries in the GOT
296 cmp r1, r2 @ entry < bss_start ||
297 cmphs r3, r1 @ _end < entry
298 addlo r1, r1, r0 @ table. This fixes up the
299 str r1, [r11], #4 @ C references.
304 not_relocated: mov r0, #0
305 1: str r0, [r2], #4 @ clear bss
313 * The C runtime environment should now be setup sufficiently.
314 * Set up some pointers, and start decompressing.
315 * r4 = kernel execution address
316 * r7 = architecture ID
320 mov r1, sp @ malloc space above stack
321 add r2, sp, #0x10000 @ 64k max
326 mov r0, #0 @ must be zero
327 mov r1, r7 @ restore architecture number
328 mov r2, r8 @ restore atags pointer
329 mov pc, r4 @ call kernel
334 .word __bss_start @ r2
338 .word _image_size @ r9
339 .word _got_start @ r11
341 .word user_stack_end @ sp
344 #ifdef CONFIG_ARCH_RPC
346 params: ldr r0, =0x10000100 @ params_phys for RPC
353 * Turn on the cache. We need to setup some page tables so that we
354 * can have both the I and D caches on.
356 * We place the page tables 16k down from the kernel execution address,
357 * and we hope that nothing else is using it. If we're using it, we
361 * r4 = kernel execution address
362 * r7 = architecture number
365 * r0, r1, r2, r3, r9, r10, r12 corrupted
366 * This routine must preserve:
370 cache_on: mov r3, #8 @ cache_on function
374 * Initialize the highest priority protection region, PR7
375 * to cover all 32bit address and cacheable and bufferable.
377 __armv4_mpu_cache_on:
378 mov r0, #0x3f @ 4G, the whole
379 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
380 mcr p15, 0, r0, c6, c7, 1
383 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
384 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
385 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
388 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
389 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
392 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
393 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
394 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
395 mrc p15, 0, r0, c1, c0, 0 @ read control reg
396 @ ...I .... ..D. WC.M
397 orr r0, r0, #0x002d @ .... .... ..1. 11.1
398 orr r0, r0, #0x1000 @ ...1 .... .... ....
400 mcr p15, 0, r0, c1, c0, 0 @ write control reg
403 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
404 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
407 __armv3_mpu_cache_on:
408 mov r0, #0x3f @ 4G, the whole
409 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
412 mcr p15, 0, r0, c2, c0, 0 @ cache on
413 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
416 mcr p15, 0, r0, c5, c0, 0 @ access permission
419 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
421 * ?? ARMv3 MMU does not allow reading the control register,
422 * does this really work on ARMv3 MPU?
424 mrc p15, 0, r0, c1, c0, 0 @ read control reg
425 @ .... .... .... WC.M
426 orr r0, r0, #0x000d @ .... .... .... 11.1
427 /* ?? this overwrites the value constructed above? */
429 mcr p15, 0, r0, c1, c0, 0 @ write control reg
431 /* ?? invalidate for the second time? */
432 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
435 __setup_mmu: sub r3, r4, #16384 @ Page directory size
436 bic r3, r3, #0xff @ Align the pointer
439 * Initialise the page tables, turning on the cacheable and bufferable
440 * bits for the RAM area only.
444 mov r9, r9, lsl #18 @ start of RAM
445 add r10, r9, #0x10000000 @ a reasonable RAM size
449 1: cmp r1, r9 @ if virt > start of RAM
450 orrhs r1, r1, #0x0c @ set cacheable, bufferable
451 cmp r1, r10 @ if virt > end of RAM
452 bichs r1, r1, #0x0c @ clear cacheable, bufferable
453 str r1, [r0], #4 @ 1:1 mapping
458 * If ever we are running from Flash, then we surely want the cache
459 * to be enabled also for our execution instance... We map 2MB of it
460 * so there is no map overlap problem for up to 1 MB compressed kernel.
461 * If the execution is in RAM then we would only be duplicating the above.
467 orr r1, r1, r2, lsl #20
468 add r0, r3, r2, lsl #2
475 __armv4_mmu_cache_on:
480 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
481 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
482 mrc p15, 0, r0, c1, c0, 0 @ read control reg
483 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
485 #ifdef CONFIG_CPU_ENDIAN_BE8
486 orr r0, r0, #1 << 25 @ big-endian page tables
488 bl __common_mmu_cache_on
490 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
494 __armv7_mmu_cache_on:
497 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
501 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
503 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
505 mrc p15, 0, r0, c1, c0, 0 @ read control reg
506 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
507 orr r0, r0, #0x003c @ write buffer
509 #ifdef CONFIG_CPU_ENDIAN_BE8
510 orr r0, r0, #1 << 25 @ big-endian page tables
512 orrne r0, r0, #1 @ MMU enabled
514 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
515 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
517 mcr p15, 0, r0, c1, c0, 0 @ load control register
518 mrc p15, 0, r0, c1, c0, 0 @ and read it back
520 mcr p15, 0, r0, c7, c5, 4 @ ISB
527 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
528 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
529 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
530 mrc p15, 0, r0, c1, c0, 0 @ read control reg
531 orr r0, r0, #0x1000 @ I-cache enable
532 bl __common_mmu_cache_on
534 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
541 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
542 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
544 bl __common_mmu_cache_on
546 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
549 __common_mmu_cache_on:
550 #ifndef CONFIG_THUMB2_KERNEL
552 orr r0, r0, #0x000d @ Write buffer, mmu
555 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
556 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
558 .align 5 @ cache line aligned
559 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
560 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
561 sub pc, lr, r0, lsr #32 @ properly flush pipeline
565 * Here follow the relocatable cache support functions for the
566 * various processors. This is a generic hook for locating an
567 * entry and jumping to an instruction at the specified offset
568 * from the start of the block. Please note this is all position
578 call_cache_fn: adr r12, proc_types
579 #ifdef CONFIG_CPU_CP15
580 mrc p15, 0, r9, c0, c0 @ get processor ID
582 ldr r9, =CONFIG_PROCESSOR_ID
584 1: ldr r1, [r12, #0] @ get value
585 ldr r2, [r12, #4] @ get mask
586 eor r1, r1, r9 @ (real ^ match)
588 ARM( addeq pc, r12, r3 ) @ call cache function
589 THUMB( addeq r12, r3 )
590 THUMB( moveq pc, r12 ) @ call cache function
595 * Table for cache operations. This is basically:
598 * - 'cache on' method instruction
599 * - 'cache off' method instruction
600 * - 'cache flush' method instruction
602 * We match an entry using: ((real_id ^ match) & mask) == 0
604 * Writethrough caches generally only need 'on' and 'off'
605 * methods. Writeback caches _must_ have the flush method
609 .type proc_types,#object
611 .word 0x41560600 @ ARM6/610
613 W(b) __arm6_mmu_cache_off @ works, but slow
614 W(b) __arm6_mmu_cache_off
617 @ b __arm6_mmu_cache_on @ untested
618 @ b __arm6_mmu_cache_off
619 @ b __armv3_mmu_cache_flush
621 .word 0x00000000 @ old ARM ID
630 .word 0x41007000 @ ARM7/710
632 W(b) __arm7_mmu_cache_off
633 W(b) __arm7_mmu_cache_off
637 .word 0x41807200 @ ARM720T (writethrough)
639 W(b) __armv4_mmu_cache_on
640 W(b) __armv4_mmu_cache_off
644 .word 0x41007400 @ ARM74x
646 W(b) __armv3_mpu_cache_on
647 W(b) __armv3_mpu_cache_off
648 W(b) __armv3_mpu_cache_flush
650 .word 0x41009400 @ ARM94x
652 W(b) __armv4_mpu_cache_on
653 W(b) __armv4_mpu_cache_off
654 W(b) __armv4_mpu_cache_flush
656 .word 0x00007000 @ ARM7 IDs
665 @ Everything from here on will be the new ID system.
667 .word 0x4401a100 @ sa110 / sa1100
669 W(b) __armv4_mmu_cache_on
670 W(b) __armv4_mmu_cache_off
671 W(b) __armv4_mmu_cache_flush
673 .word 0x6901b110 @ sa1110
675 W(b) __armv4_mmu_cache_on
676 W(b) __armv4_mmu_cache_off
677 W(b) __armv4_mmu_cache_flush
680 .word 0xffffff00 @ PXA9xx
681 W(b) __armv4_mmu_cache_on
682 W(b) __armv4_mmu_cache_off
683 W(b) __armv4_mmu_cache_flush
685 .word 0x56158000 @ PXA168
687 W(b) __armv4_mmu_cache_on
688 W(b) __armv4_mmu_cache_off
689 W(b) __armv5tej_mmu_cache_flush
691 .word 0x56050000 @ Feroceon
693 W(b) __armv4_mmu_cache_on
694 W(b) __armv4_mmu_cache_off
695 W(b) __armv5tej_mmu_cache_flush
697 #ifdef CONFIG_CPU_FEROCEON_OLD_ID
698 /* this conflicts with the standard ARMv5TE entry */
699 .long 0x41009260 @ Old Feroceon
701 b __armv4_mmu_cache_on
702 b __armv4_mmu_cache_off
703 b __armv5tej_mmu_cache_flush
706 .word 0x66015261 @ FA526
708 W(b) __fa526_cache_on
709 W(b) __armv4_mmu_cache_off
710 W(b) __fa526_cache_flush
712 @ These match on the architecture ID
714 .word 0x00020000 @ ARMv4T
716 W(b) __armv4_mmu_cache_on
717 W(b) __armv4_mmu_cache_off
718 W(b) __armv4_mmu_cache_flush
720 .word 0x00050000 @ ARMv5TE
722 W(b) __armv4_mmu_cache_on
723 W(b) __armv4_mmu_cache_off
724 W(b) __armv4_mmu_cache_flush
726 .word 0x00060000 @ ARMv5TEJ
728 W(b) __armv4_mmu_cache_on
729 W(b) __armv4_mmu_cache_off
730 W(b) __armv5tej_mmu_cache_flush
732 .word 0x0007b000 @ ARMv6
734 W(b) __armv4_mmu_cache_on
735 W(b) __armv4_mmu_cache_off
736 W(b) __armv6_mmu_cache_flush
738 .word 0x560f5810 @ Marvell PJ4 ARMv6
740 W(b) __armv4_mmu_cache_on
741 W(b) __armv4_mmu_cache_off
742 W(b) __armv6_mmu_cache_flush
744 .word 0x000f0000 @ new CPU Id
746 W(b) __armv7_mmu_cache_on
747 W(b) __armv7_mmu_cache_off
748 W(b) __armv7_mmu_cache_flush
750 .word 0 @ unrecognised type
759 .size proc_types, . - proc_types
762 * Turn off the Cache and MMU. ARMv3 does not support
763 * reading the control register, but ARMv4 does.
766 * r0, r1, r2, r3, r9, r12 corrupted
767 * This routine must preserve:
771 cache_off: mov r3, #12 @ cache_off function
774 __armv4_mpu_cache_off:
775 mrc p15, 0, r0, c1, c0
777 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
779 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
780 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
781 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
784 __armv3_mpu_cache_off:
785 mrc p15, 0, r0, c1, c0
787 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
789 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
792 __armv4_mmu_cache_off:
794 mrc p15, 0, r0, c1, c0
796 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
798 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
799 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
803 __armv7_mmu_cache_off:
804 mrc p15, 0, r0, c1, c0
810 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
812 bl __armv7_mmu_cache_flush
815 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
817 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
818 mcr p15, 0, r0, c7, c10, 4 @ DSB
819 mcr p15, 0, r0, c7, c5, 4 @ ISB
822 __arm6_mmu_cache_off:
823 mov r0, #0x00000030 @ ARM6 control reg.
824 b __armv3_mmu_cache_off
826 __arm7_mmu_cache_off:
827 mov r0, #0x00000070 @ ARM7 control reg.
828 b __armv3_mmu_cache_off
830 __armv3_mmu_cache_off:
831 mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off
833 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
834 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
838 * Clean and flush the cache to maintain consistency.
841 * r1, r2, r3, r9, r10, r11, r12 corrupted
842 * This routine must preserve:
850 __armv4_mpu_cache_flush:
853 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
854 mov r1, #7 << 5 @ 8 segments
855 1: orr r3, r1, #63 << 26 @ 64 entries
856 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
857 subs r3, r3, #1 << 26
858 bcs 2b @ entries 63 to 0
860 bcs 1b @ segments 7 to 0
863 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
864 mcr p15, 0, ip, c7, c10, 4 @ drain WB
869 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
870 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
871 mcr p15, 0, r1, c7, c10, 4 @ drain WB
874 __armv6_mmu_cache_flush:
876 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
877 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
878 mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
879 mcr p15, 0, r1, c7, c10, 4 @ drain WB
882 __armv7_mmu_cache_flush:
883 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
884 tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
887 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
890 mcr p15, 0, r10, c7, c10, 5 @ DMB
891 stmfd sp!, {r0-r7, r9-r11}
892 mrc p15, 1, r0, c0, c0, 1 @ read clidr
893 ands r3, r0, #0x7000000 @ extract loc from clidr
894 mov r3, r3, lsr #23 @ left align loc bit field
895 beq finished @ if loc is 0, then no need to clean
896 mov r10, #0 @ start clean at cache level 0
898 add r2, r10, r10, lsr #1 @ work out 3x current cache level
899 mov r1, r0, lsr r2 @ extract cache type bits from clidr
900 and r1, r1, #7 @ mask of the bits for current cache only
901 cmp r1, #2 @ see what cache we have at this level
902 blt skip @ skip if no cache, or just i-cache
903 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
904 mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr
905 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
906 and r2, r1, #7 @ extract the length of the cache lines
907 add r2, r2, #4 @ add 4 (line length offset)
909 ands r4, r4, r1, lsr #3 @ find maximum number on the way size
910 clz r5, r4 @ find bit position of way size increment
912 ands r7, r7, r1, lsr #13 @ extract max number of the index size
914 mov r9, r4 @ create working copy of max way size
916 ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11
917 ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11
918 THUMB( lsl r6, r9, r5 )
919 THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
920 THUMB( lsl r6, r7, r2 )
921 THUMB( orr r11, r11, r6 ) @ factor index number into r11
922 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
923 subs r9, r9, #1 @ decrement the way
925 subs r7, r7, #1 @ decrement the index
928 add r10, r10, #2 @ increment cache number
932 ldmfd sp!, {r0-r7, r9-r11}
933 mov r10, #0 @ swith back to cache level 0
934 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
936 mcr p15, 0, r10, c7, c10, 4 @ DSB
937 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
938 mcr p15, 0, r10, c7, c10, 4 @ DSB
939 mcr p15, 0, r10, c7, c5, 4 @ ISB
942 __armv5tej_mmu_cache_flush:
943 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
945 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
946 mcr p15, 0, r0, c7, c10, 4 @ drain WB
949 __armv4_mmu_cache_flush:
950 mov r2, #64*1024 @ default: 32K dcache size (*2)
951 mov r11, #32 @ default: 32 byte line size
952 mrc p15, 0, r3, c0, c0, 1 @ read cache type
953 teq r3, r9 @ cache ID register present?
958 mov r2, r2, lsl r1 @ base dcache size *2
959 tst r3, #1 << 14 @ test M bit
960 addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1
964 mov r11, r11, lsl r3 @ cache line size in bytes
967 bic r1, r1, #63 @ align to longest cache line
970 ARM( ldr r3, [r1], r11 ) @ s/w flush D cache
971 THUMB( ldr r3, [r1] ) @ s/w flush D cache
972 THUMB( add r1, r1, r11 )
976 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
977 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
978 mcr p15, 0, r1, c7, c10, 4 @ drain WB
981 __armv3_mmu_cache_flush:
982 __armv3_mpu_cache_flush:
984 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
988 * Various debugging routines for printing hex characters and
989 * memory, which again must be relocatable.
993 .type phexbuf,#object
995 .size phexbuf, . - phexbuf
997 @ phex corrupts {r0, r1, r2, r3}
998 phex: adr r3, phexbuf
1012 @ puts corrupts {r0, r1, r2, r3}
1014 1: ldrb r2, [r0], #1
1027 @ putc corrupts {r0, r1, r2, r3}
1034 @ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr}
1035 memdump: mov r12, r0
1038 2: mov r0, r11, lsl #2
1046 ldr r0, [r12, r11, lsl #2]
1067 .section ".stack", "aw", %nobits
1068 user_stack: .space 4096