2 * linux/arch/arm/boot/compressed/head.S
4 * Copyright (C) 1996-2002 Russell King
5 * Copyright (C) 2004 Hyok S. Choi (MPU support)
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/linkage.h>
16 * Note that these macros must not contain any code which is not
17 * 100% relocatable. Any attempt to do so will result in a crash.
18 * Please select one of the following when turning on debugging.
22 #if defined(CONFIG_DEBUG_ICEDCC)
25 .macro loadsp, rb, tmp
28 mcr p14, 0, \ch, c0, c5, 0
30 #elif defined(CONFIG_CPU_V7)
31 .macro loadsp, rb, tmp
34 wait: mrc p14, 0, pc, c0, c1, 0
36 mcr p14, 0, \ch, c0, c5, 0
38 #elif defined(CONFIG_CPU_XSCALE)
39 .macro loadsp, rb, tmp
42 mcr p14, 0, \ch, c8, c0, 0
45 .macro loadsp, rb, tmp
48 mcr p14, 0, \ch, c1, c0, 0
54 #include <mach/debug-macro.S>
60 #if defined(CONFIG_ARCH_SA1100)
61 .macro loadsp, rb, tmp
62 mov \rb, #0x80000000 @ physical base address
63 #ifdef CONFIG_DEBUG_LL_SER3
64 add \rb, \rb, #0x00050000 @ Ser3
66 add \rb, \rb, #0x00010000 @ Ser1
69 #elif defined(CONFIG_ARCH_S3C2410)
70 .macro loadsp, rb, tmp
72 add \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT
75 .macro loadsp, rb, tmp
93 .macro debug_reloc_start
96 kphex r6, 8 /* processor id */
98 kphex r7, 8 /* architecture id */
99 #ifdef CONFIG_CPU_CP15
101 mrc p15, 0, r0, c1, c0
102 kphex r0, 8 /* control reg */
105 kphex r5, 8 /* decompressed kernel start */
107 kphex r9, 8 /* decompressed kernel end */
109 kphex r4, 8 /* kernel execution address */
114 .macro debug_reloc_end
116 kphex r5, 8 /* end of kernel */
119 bl memdump /* dump 256 bytes at start of kernel */
123 .section ".start", #alloc, #execinstr
125 * sort out different calling conventions
128 .arm @ Always enter in ARM state
130 .type start,#function
131 THUMB( adr r12, BSYM(1f) )
139 .word 0x016f2818 @ Magic numbers to help the loader
140 .word start @ absolute load/run zImage address
141 .word _edata @ zImage end address
143 1: mov r7, r1 @ save architecture ID
144 mov r8, r2 @ save atags pointer
146 #ifndef __ARM_ARCH_2__
148 * Booting from Angel - need to enter SVC mode and disable
149 * FIQs/IRQs (numeric definitions from angel arm.h source).
150 * We only do this if we were in user mode on entry.
152 mrs r2, cpsr @ get current mode
153 tst r2, #3 @ not user?
155 mov r0, #0x17 @ angel_SWIreason_EnterSVC
156 ARM( swi 0x123456 ) @ angel_SWI_ARM
157 THUMB( svc 0xab ) @ angel_SWI_THUMB
159 mrs r2, cpsr @ turn off interrupts to
160 orr r2, r2, #0xc0 @ prevent angel from running
163 teqp pc, #0x0c000003 @ turn off interrupts
167 * Note that some cache flushing and other stuff may
168 * be needed here - is there an Angel SWI call for this?
172 * some architecture specific code can be inserted
173 * by the linker here, but it should preserve r7, r8, and r9.
178 ldmia r0, {r1, r2, r3, r5, r6, r11, ip}
180 #ifdef CONFIG_AUTO_ZRELADDR
181 @ determine final kernel image address
183 and r4, r4, #0xf8000000
184 add r4, r4, #TEXT_OFFSET
188 subs r0, r0, r1 @ calculate the delta offset
190 @ if delta is zero, we are
191 beq not_relocated @ running at the address we
195 * We're running at a different address. We need to fix
196 * up various pointers:
197 * r5 - zImage base address (_start)
198 * r6 - size of decompressed image
206 #ifndef CONFIG_ZBOOT_ROM
208 * If we're running fully PIC === CONFIG_ZBOOT_ROM = n,
209 * we need to fix up pointers into the BSS region.
219 * Relocate all entries in the GOT table.
221 1: ldr r1, [r11, #0] @ relocate entries in the GOT
222 add r1, r1, r0 @ table. This fixes up the
223 str r1, [r11], #4 @ C references.
229 * Relocate entries in the GOT table. We only relocate
230 * the entries that are outside the (relocated) BSS region.
232 1: ldr r1, [r11, #0] @ relocate entries in the GOT
233 cmp r1, r2 @ entry < bss_start ||
234 cmphs r3, r1 @ _end < entry
235 addlo r1, r1, r0 @ table. This fixes up the
236 str r1, [r11], #4 @ C references.
241 not_relocated: mov r0, #0
242 1: str r0, [r2], #4 @ clear bss
250 * The C runtime environment should now be setup
251 * sufficiently. Turn the cache on, set up some
252 * pointers, and start decompressing.
256 mov r1, sp @ malloc space above stack
257 add r2, sp, #0x10000 @ 64k max
260 * Check to see if we will overwrite ourselves.
261 * r4 = final kernel address
262 * r5 = start of this image
263 * r6 = size of decompressed image
264 * r2 = end of malloc space (and therefore this image)
267 * r4 + image length <= r5 -> OK
275 mov r5, r2 @ decompress after malloc space
280 add r0, r0, #127 + 128 @ alignment + stack
281 bic r0, r0, #127 @ align the kernel length
283 * r0 = decompressed kernel length
285 * r4 = kernel execution address
286 * r5 = decompressed kernel start
287 * r7 = architecture ID
289 * r9-r12,r14 = corrupted
291 add r1, r5, r0 @ end of decompressed kernel
295 1: ldmia r2!, {r9 - r12, r14} @ copy relocation code
296 stmia r1!, {r9 - r12, r14}
297 ldmia r2!, {r9 - r12, r14}
298 stmia r1!, {r9 - r12, r14}
302 add sp, sp, #128 @ relocate the stack
305 ARM( add pc, r5, r0 ) @ call relocation code
306 THUMB( add r12, r5, r0 )
307 THUMB( mov pc, r12 ) @ call relocation code
310 * We're not in danger of overwriting ourselves. Do this the simple way.
312 * r4 = kernel execution address
313 * r7 = architecture ID
315 wont_overwrite: mov r0, r4
323 .word __bss_start @ r2
326 .word _image_size @ r6
327 .word _got_start @ r11
329 .word user_stack_end @ sp
330 LC1: .word reloc_end - reloc_start
333 #ifdef CONFIG_ARCH_RPC
335 params: ldr r0, =0x10000100 @ params_phys for RPC
342 * Turn on the cache. We need to setup some page tables so that we
343 * can have both the I and D caches on.
345 * We place the page tables 16k down from the kernel execution address,
346 * and we hope that nothing else is using it. If we're using it, we
350 * r4 = kernel execution address
351 * r7 = architecture number
354 * r0, r1, r2, r3, r9, r10, r12 corrupted
355 * This routine must preserve:
359 cache_on: mov r3, #8 @ cache_on function
363 * Initialize the highest priority protection region, PR7
364 * to cover all 32bit address and cacheable and bufferable.
366 __armv4_mpu_cache_on:
367 mov r0, #0x3f @ 4G, the whole
368 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
369 mcr p15, 0, r0, c6, c7, 1
372 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
373 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
374 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
377 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
378 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
381 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
382 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
383 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
384 mrc p15, 0, r0, c1, c0, 0 @ read control reg
385 @ ...I .... ..D. WC.M
386 orr r0, r0, #0x002d @ .... .... ..1. 11.1
387 orr r0, r0, #0x1000 @ ...1 .... .... ....
389 mcr p15, 0, r0, c1, c0, 0 @ write control reg
392 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
393 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
396 __armv3_mpu_cache_on:
397 mov r0, #0x3f @ 4G, the whole
398 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
401 mcr p15, 0, r0, c2, c0, 0 @ cache on
402 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
405 mcr p15, 0, r0, c5, c0, 0 @ access permission
408 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
410 * ?? ARMv3 MMU does not allow reading the control register,
411 * does this really work on ARMv3 MPU?
413 mrc p15, 0, r0, c1, c0, 0 @ read control reg
414 @ .... .... .... WC.M
415 orr r0, r0, #0x000d @ .... .... .... 11.1
416 /* ?? this overwrites the value constructed above? */
418 mcr p15, 0, r0, c1, c0, 0 @ write control reg
420 /* ?? invalidate for the second time? */
421 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
424 __setup_mmu: sub r3, r4, #16384 @ Page directory size
425 bic r3, r3, #0xff @ Align the pointer
428 * Initialise the page tables, turning on the cacheable and bufferable
429 * bits for the RAM area only.
433 mov r9, r9, lsl #18 @ start of RAM
434 add r10, r9, #0x10000000 @ a reasonable RAM size
438 1: cmp r1, r9 @ if virt > start of RAM
439 orrhs r1, r1, #0x0c @ set cacheable, bufferable
440 cmp r1, r10 @ if virt > end of RAM
441 bichs r1, r1, #0x0c @ clear cacheable, bufferable
442 str r1, [r0], #4 @ 1:1 mapping
447 * If ever we are running from Flash, then we surely want the cache
448 * to be enabled also for our execution instance... We map 2MB of it
449 * so there is no map overlap problem for up to 1 MB compressed kernel.
450 * If the execution is in RAM then we would only be duplicating the above.
456 orr r1, r1, r2, lsl #20
457 add r0, r3, r2, lsl #2
464 __armv4_mmu_cache_on:
469 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
470 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
471 mrc p15, 0, r0, c1, c0, 0 @ read control reg
472 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
474 #ifdef CONFIG_CPU_ENDIAN_BE8
475 orr r0, r0, #1 << 25 @ big-endian page tables
477 bl __common_mmu_cache_on
479 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
483 __armv7_mmu_cache_on:
486 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
490 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
492 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
494 mrc p15, 0, r0, c1, c0, 0 @ read control reg
495 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
496 orr r0, r0, #0x003c @ write buffer
498 #ifdef CONFIG_CPU_ENDIAN_BE8
499 orr r0, r0, #1 << 25 @ big-endian page tables
501 orrne r0, r0, #1 @ MMU enabled
503 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
504 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
506 mcr p15, 0, r0, c1, c0, 0 @ load control register
507 mrc p15, 0, r0, c1, c0, 0 @ and read it back
509 mcr p15, 0, r0, c7, c5, 4 @ ISB
516 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
517 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
518 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
519 mrc p15, 0, r0, c1, c0, 0 @ read control reg
520 orr r0, r0, #0x1000 @ I-cache enable
521 bl __common_mmu_cache_on
523 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
530 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
531 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
533 bl __common_mmu_cache_on
535 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
538 __common_mmu_cache_on:
539 #ifndef CONFIG_THUMB2_KERNEL
541 orr r0, r0, #0x000d @ Write buffer, mmu
544 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
545 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
547 .align 5 @ cache line aligned
548 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
549 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
550 sub pc, lr, r0, lsr #32 @ properly flush pipeline
554 * All code following this line is relocatable. It is relocated by
555 * the above code to the end of the decompressed kernel image and
556 * executed there. During this time, we have no stacks.
558 * r0 = decompressed kernel length
560 * r4 = kernel execution address
561 * r5 = decompressed kernel start
562 * r7 = architecture ID
564 * r9-r12,r14 = corrupted
567 reloc_start: add r9, r5, r0
568 sub r9, r9, #128 @ do not copy the stack
573 ldmia r5!, {r0, r2, r3, r10 - r12, r14} @ relocate kernel
574 stmia r1!, {r0, r2, r3, r10 - r12, r14}
580 add sp, sp, #128 @ relocate the stack
583 call_kernel: bl cache_clean_flush
585 mov r0, #0 @ must be zero
586 mov r1, r7 @ restore architecture number
587 mov r2, r8 @ restore atags pointer
588 mov pc, r4 @ call kernel
591 * Here follow the relocatable cache support functions for the
592 * various processors. This is a generic hook for locating an
593 * entry and jumping to an instruction at the specified offset
594 * from the start of the block. Please note this is all position
604 call_cache_fn: adr r12, proc_types
605 #ifdef CONFIG_CPU_CP15
606 mrc p15, 0, r9, c0, c0 @ get processor ID
608 ldr r9, =CONFIG_PROCESSOR_ID
610 1: ldr r1, [r12, #0] @ get value
611 ldr r2, [r12, #4] @ get mask
612 eor r1, r1, r9 @ (real ^ match)
614 ARM( addeq pc, r12, r3 ) @ call cache function
615 THUMB( addeq r12, r3 )
616 THUMB( moveq pc, r12 ) @ call cache function
621 * Table for cache operations. This is basically:
624 * - 'cache on' method instruction
625 * - 'cache off' method instruction
626 * - 'cache flush' method instruction
628 * We match an entry using: ((real_id ^ match) & mask) == 0
630 * Writethrough caches generally only need 'on' and 'off'
631 * methods. Writeback caches _must_ have the flush method
635 .type proc_types,#object
637 .word 0x41560600 @ ARM6/610
639 W(b) __arm6_mmu_cache_off @ works, but slow
640 W(b) __arm6_mmu_cache_off
643 @ b __arm6_mmu_cache_on @ untested
644 @ b __arm6_mmu_cache_off
645 @ b __armv3_mmu_cache_flush
647 .word 0x00000000 @ old ARM ID
656 .word 0x41007000 @ ARM7/710
658 W(b) __arm7_mmu_cache_off
659 W(b) __arm7_mmu_cache_off
663 .word 0x41807200 @ ARM720T (writethrough)
665 W(b) __armv4_mmu_cache_on
666 W(b) __armv4_mmu_cache_off
670 .word 0x41007400 @ ARM74x
672 W(b) __armv3_mpu_cache_on
673 W(b) __armv3_mpu_cache_off
674 W(b) __armv3_mpu_cache_flush
676 .word 0x41009400 @ ARM94x
678 W(b) __armv4_mpu_cache_on
679 W(b) __armv4_mpu_cache_off
680 W(b) __armv4_mpu_cache_flush
682 .word 0x00007000 @ ARM7 IDs
691 @ Everything from here on will be the new ID system.
693 .word 0x4401a100 @ sa110 / sa1100
695 W(b) __armv4_mmu_cache_on
696 W(b) __armv4_mmu_cache_off
697 W(b) __armv4_mmu_cache_flush
699 .word 0x6901b110 @ sa1110
701 W(b) __armv4_mmu_cache_on
702 W(b) __armv4_mmu_cache_off
703 W(b) __armv4_mmu_cache_flush
706 .word 0xffffff00 @ PXA9xx
707 W(b) __armv4_mmu_cache_on
708 W(b) __armv4_mmu_cache_off
709 W(b) __armv4_mmu_cache_flush
711 .word 0x56158000 @ PXA168
713 W(b) __armv4_mmu_cache_on
714 W(b) __armv4_mmu_cache_off
715 W(b) __armv5tej_mmu_cache_flush
717 .word 0x56050000 @ Feroceon
719 W(b) __armv4_mmu_cache_on
720 W(b) __armv4_mmu_cache_off
721 W(b) __armv5tej_mmu_cache_flush
723 #ifdef CONFIG_CPU_FEROCEON_OLD_ID
724 /* this conflicts with the standard ARMv5TE entry */
725 .long 0x41009260 @ Old Feroceon
727 b __armv4_mmu_cache_on
728 b __armv4_mmu_cache_off
729 b __armv5tej_mmu_cache_flush
732 .word 0x66015261 @ FA526
734 W(b) __fa526_cache_on
735 W(b) __armv4_mmu_cache_off
736 W(b) __fa526_cache_flush
738 @ These match on the architecture ID
740 .word 0x00020000 @ ARMv4T
742 W(b) __armv4_mmu_cache_on
743 W(b) __armv4_mmu_cache_off
744 W(b) __armv4_mmu_cache_flush
746 .word 0x00050000 @ ARMv5TE
748 W(b) __armv4_mmu_cache_on
749 W(b) __armv4_mmu_cache_off
750 W(b) __armv4_mmu_cache_flush
752 .word 0x00060000 @ ARMv5TEJ
754 W(b) __armv4_mmu_cache_on
755 W(b) __armv4_mmu_cache_off
756 W(b) __armv5tej_mmu_cache_flush
758 .word 0x0007b000 @ ARMv6
760 W(b) __armv4_mmu_cache_on
761 W(b) __armv4_mmu_cache_off
762 W(b) __armv6_mmu_cache_flush
764 .word 0x560f5810 @ Marvell PJ4 ARMv6
766 W(b) __armv4_mmu_cache_on
767 W(b) __armv4_mmu_cache_off
768 W(b) __armv6_mmu_cache_flush
770 .word 0x000f0000 @ new CPU Id
772 W(b) __armv7_mmu_cache_on
773 W(b) __armv7_mmu_cache_off
774 W(b) __armv7_mmu_cache_flush
776 .word 0 @ unrecognised type
785 .size proc_types, . - proc_types
788 * Turn off the Cache and MMU. ARMv3 does not support
789 * reading the control register, but ARMv4 does.
792 * r0, r1, r2, r3, r9, r12 corrupted
793 * This routine must preserve:
797 cache_off: mov r3, #12 @ cache_off function
800 __armv4_mpu_cache_off:
801 mrc p15, 0, r0, c1, c0
803 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
805 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
806 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
807 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
810 __armv3_mpu_cache_off:
811 mrc p15, 0, r0, c1, c0
813 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
815 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
818 __armv4_mmu_cache_off:
820 mrc p15, 0, r0, c1, c0
822 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
824 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
825 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
829 __armv7_mmu_cache_off:
830 mrc p15, 0, r0, c1, c0
836 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
838 bl __armv7_mmu_cache_flush
841 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
843 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
844 mcr p15, 0, r0, c7, c10, 4 @ DSB
845 mcr p15, 0, r0, c7, c5, 4 @ ISB
848 __arm6_mmu_cache_off:
849 mov r0, #0x00000030 @ ARM6 control reg.
850 b __armv3_mmu_cache_off
852 __arm7_mmu_cache_off:
853 mov r0, #0x00000070 @ ARM7 control reg.
854 b __armv3_mmu_cache_off
856 __armv3_mmu_cache_off:
857 mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off
859 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
860 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
864 * Clean and flush the cache to maintain consistency.
867 * r1, r2, r3, r9, r10, r11, r12 corrupted
868 * This routine must preserve:
876 __armv4_mpu_cache_flush:
879 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
880 mov r1, #7 << 5 @ 8 segments
881 1: orr r3, r1, #63 << 26 @ 64 entries
882 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
883 subs r3, r3, #1 << 26
884 bcs 2b @ entries 63 to 0
886 bcs 1b @ segments 7 to 0
889 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
890 mcr p15, 0, ip, c7, c10, 4 @ drain WB
895 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
896 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
897 mcr p15, 0, r1, c7, c10, 4 @ drain WB
900 __armv6_mmu_cache_flush:
902 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
903 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
904 mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
905 mcr p15, 0, r1, c7, c10, 4 @ drain WB
908 __armv7_mmu_cache_flush:
909 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
910 tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
913 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
916 mcr p15, 0, r10, c7, c10, 5 @ DMB
917 stmfd sp!, {r0-r7, r9-r11}
918 mrc p15, 1, r0, c0, c0, 1 @ read clidr
919 ands r3, r0, #0x7000000 @ extract loc from clidr
920 mov r3, r3, lsr #23 @ left align loc bit field
921 beq finished @ if loc is 0, then no need to clean
922 mov r10, #0 @ start clean at cache level 0
924 add r2, r10, r10, lsr #1 @ work out 3x current cache level
925 mov r1, r0, lsr r2 @ extract cache type bits from clidr
926 and r1, r1, #7 @ mask of the bits for current cache only
927 cmp r1, #2 @ see what cache we have at this level
928 blt skip @ skip if no cache, or just i-cache
929 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
930 mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr
931 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
932 and r2, r1, #7 @ extract the length of the cache lines
933 add r2, r2, #4 @ add 4 (line length offset)
935 ands r4, r4, r1, lsr #3 @ find maximum number on the way size
936 clz r5, r4 @ find bit position of way size increment
938 ands r7, r7, r1, lsr #13 @ extract max number of the index size
940 mov r9, r4 @ create working copy of max way size
942 ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11
943 ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11
944 THUMB( lsl r6, r9, r5 )
945 THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
946 THUMB( lsl r6, r7, r2 )
947 THUMB( orr r11, r11, r6 ) @ factor index number into r11
948 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
949 subs r9, r9, #1 @ decrement the way
951 subs r7, r7, #1 @ decrement the index
954 add r10, r10, #2 @ increment cache number
958 ldmfd sp!, {r0-r7, r9-r11}
959 mov r10, #0 @ swith back to cache level 0
960 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
962 mcr p15, 0, r10, c7, c10, 4 @ DSB
963 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
964 mcr p15, 0, r10, c7, c10, 4 @ DSB
965 mcr p15, 0, r10, c7, c5, 4 @ ISB
968 __armv5tej_mmu_cache_flush:
969 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
971 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
972 mcr p15, 0, r0, c7, c10, 4 @ drain WB
975 __armv4_mmu_cache_flush:
976 mov r2, #64*1024 @ default: 32K dcache size (*2)
977 mov r11, #32 @ default: 32 byte line size
978 mrc p15, 0, r3, c0, c0, 1 @ read cache type
979 teq r3, r9 @ cache ID register present?
984 mov r2, r2, lsl r1 @ base dcache size *2
985 tst r3, #1 << 14 @ test M bit
986 addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1
990 mov r11, r11, lsl r3 @ cache line size in bytes
993 bic r1, r1, #63 @ align to longest cache line
996 ARM( ldr r3, [r1], r11 ) @ s/w flush D cache
997 THUMB( ldr r3, [r1] ) @ s/w flush D cache
998 THUMB( add r1, r1, r11 )
1002 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1003 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
1004 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1007 __armv3_mmu_cache_flush:
1008 __armv3_mpu_cache_flush:
1010 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
1014 * Various debugging routines for printing hex characters and
1015 * memory, which again must be relocatable.
1019 .type phexbuf,#object
1021 .size phexbuf, . - phexbuf
1023 @ phex corrupts {r0, r1, r2, r3}
1024 phex: adr r3, phexbuf
1038 @ puts corrupts {r0, r1, r2, r3}
1040 1: ldrb r2, [r0], #1
1053 @ putc corrupts {r0, r1, r2, r3}
1060 @ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr}
1061 memdump: mov r12, r0
1064 2: mov r0, r11, lsl #2
1072 ldr r0, [r12, r11, lsl #2]
1094 .section ".stack", "aw", %nobits
1095 user_stack: .space 4096