2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
16 #include "am33xx.dtsi"
17 #include <dt-bindings/pwm/pwm.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
21 model = "OnRISC Baltos iR 5221";
22 compatible = "vscom,onrisc", "ti,am33xx";
26 cpu0-supply = <&vdd1_reg>;
31 device_type = "memory";
32 reg = <0x80000000 0x10000000>; /* 256 MB */
35 vbat: fixedregulator@0 {
36 compatible = "regulator-fixed";
37 regulator-name = "vbat";
38 regulator-min-microvolt = <5000000>;
39 regulator-max-microvolt = <5000000>;
43 wl12xx_vmmc: fixedregulator@2 {
44 pinctrl-names = "default";
45 pinctrl-0 = <&wl12xx_gpio>;
46 compatible = "regulator-fixed";
47 regulator-name = "vwl1271";
48 regulator-min-microvolt = <3300000>;
49 regulator-max-microvolt = <3300000>;
51 startup-delay-us = <70000>;
57 mmc2_pins: pinmux_mmc2_pins {
58 pinctrl-single,pins = <
59 0x020 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad8.mmc1_dat0_mux0 */
60 0x024 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad9.mmc1_dat1_mux0 */
61 0x028 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad10.mmc1_dat2_mux0 */
62 0x02c (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad11.mmc1_dat3_mux0 */
63 0x080 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk_mux0 */
64 0x084 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd_mux0 */
65 0x1e4 (PIN_INPUT_PULLUP | MUX_MODE7) /* emu0.gpio3[7] */
69 wl12xx_gpio: pinmux_wl12xx_gpio {
70 pinctrl-single,pins = <
71 0x1e8 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* emu1.gpio3[8] */
75 tps65910_pins: pinmux_tps65910_pins {
76 pinctrl-single,pins = <
77 0x078 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ben1.gpio1[28] */
81 tca6416_pins: pinmux_tca6416_pins {
82 pinctrl-single,pins = <
83 0x1b4 (PIN_INPUT_PULLUP | MUX_MODE7) /* xdma_event_intr1.gpio0[20] tca6416 stuff */
87 i2c1_pins: pinmux_i2c1_pins {
88 pinctrl-single,pins = <
89 0x158 0x2a /* spi0_d1.i2c1_sda_mux3, INPUT | MODE2 */
90 0x15c 0x2a /* spi0_cs0.i2c1_scl_mux3, INPUT | MODE2 */
94 dcan1_pins: pinmux_dcan1_pins {
95 pinctrl-single,pins = <
96 0x168 0x0a /* uart0_ctsn.dcan1_tx_mux0, OUTPUT | MODE2 */
97 0x16c 0x2a /* uart0_rtsn.dcan1_rx_mux0, INPUT | MODE2 */
101 uart0_pins: pinmux_uart0_pins {
102 pinctrl-single,pins = <
103 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
104 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
108 uart1_pins: pinmux_uart1_pins {
109 pinctrl-single,pins = <
110 0x180 0x28 /* uart1_rxd, INPUT | MODE0 */
111 0x184 0x28 /* uart1_txd, INPUT | MODE0 */
112 0x178 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_ctsn, INPUT | MODE0 */
113 0x17c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart1_rtsn, OUTPUT | MODE0 */
114 0x0e0 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.gpio2[22] DTR */
115 0x0e4 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.gpio2[23] DSR */
116 0x0e8 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.gpio2[24] DCD */
117 0x0ec (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.gpio2[25] RI */
121 uart2_pins: pinmux_uart2_pins {
122 pinctrl-single,pins = <
123 0x150 0x29 /* spi0_sclk.uart2_rxd_mux3, INPUT | MODE1 */
124 0x154 0x09 /* spi0_d0.uart2_txd_mux3, OUTPUT | MODE1 */
125 0x188 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* i2c0_sda.uart2_ctsn_mux0 */
126 0x18c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* i2c0_scl.uart2_rtsn_mux0 */
127 0x030 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad12.gpio1[12] DTR */
128 0x034 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad13.gpio1[13] DSR */
129 0x038 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad14.gpio1[14] DCD */
130 0x03c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad15.gpio1[15] RI */
132 0x1a0 (PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkr.gpio3[18], INPUT_PULLDOWN | MODE7 */
136 cpsw_default: cpsw_default {
137 pinctrl-single,pins = <
139 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */
140 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_tx_en.rmii1_txen */
141 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
142 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
143 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
144 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
145 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii1_refclk */
149 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
150 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */
151 0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */
152 0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */
153 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */
154 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */
155 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */
156 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */
157 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */
158 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */
159 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */
160 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */
164 cpsw_sleep: cpsw_sleep {
165 pinctrl-single,pins = <
166 /* Slave 1 reset value */
167 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
168 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
169 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
170 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
171 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
172 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
173 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
175 /* Slave 2 reset value*/
176 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7)
177 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7)
178 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7)
179 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7)
180 0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7)
181 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7)
182 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7)
183 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7)
184 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7)
185 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)
186 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)
187 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)
191 davinci_mdio_default: davinci_mdio_default {
192 pinctrl-single,pins = <
194 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
195 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
199 davinci_mdio_sleep: davinci_mdio_sleep {
200 pinctrl-single,pins = <
201 /* MDIO reset value */
202 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
203 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
207 nandflash_pins_s0: nandflash_pins_s0 {
208 pinctrl-single,pins = <
209 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
210 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
211 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
212 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
213 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
214 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
215 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
216 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
217 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
218 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
219 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
220 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
221 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
222 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
223 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
233 pinctrl-names = "default";
234 pinctrl-0 = <&nandflash_pins_s0>;
235 ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
239 reg = <0 0 0>; /* CS0, offset 0 */
240 nand-bus-width = <8>;
241 ti,nand-ecc-opt = "bch8";
242 ti,nand-xfer-type = "polled";
244 gpmc,device-nand = "true";
245 gpmc,device-width = <1>;
246 gpmc,sync-clk-ps = <0>;
248 gpmc,cs-rd-off-ns = <44>;
249 gpmc,cs-wr-off-ns = <44>;
250 gpmc,adv-on-ns = <6>;
251 gpmc,adv-rd-off-ns = <34>;
252 gpmc,adv-wr-off-ns = <44>;
254 gpmc,we-off-ns = <40>;
256 gpmc,oe-off-ns = <54>;
257 gpmc,access-ns = <64>;
258 gpmc,rd-cycle-ns = <82>;
259 gpmc,wr-cycle-ns = <82>;
260 gpmc,wait-on-read = "true";
261 gpmc,wait-on-write = "true";
262 gpmc,bus-turnaround-ns = <0>;
263 gpmc,cycle2cycle-delay-ns = <0>;
264 gpmc,clk-activation-ns = <0>;
265 gpmc,wait-monitoring-ns = <0>;
266 gpmc,wr-access-ns = <40>;
267 gpmc,wr-data-mux-bus-ns = <0>;
269 #address-cells = <1>;
276 pinctrl-names = "default";
277 pinctrl-0 = <&uart0_pins>;
283 pinctrl-names = "default";
284 pinctrl-0 = <&uart1_pins>;
285 dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
286 dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
287 dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
288 rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>;
289 cts-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
290 rts-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
296 pinctrl-names = "default";
297 pinctrl-0 = <&uart2_pins>;
298 dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
299 dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
300 dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
301 rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
302 cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
303 rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
309 pinctrl-names = "default";
310 pinctrl-0 = <&i2c1_pins>;
313 clock-frequency = <400000>;
319 interrupt-parent = <&gpio1>;
320 interrupts = <28 GPIO_ACTIVE_LOW>;
321 pinctrl-names = "default";
322 pinctrl-0 = <&tps65910_pins>;
326 compatible = "at24,24c02";
332 compatible = "ti,tca6416";
336 interrupt-parent = <&gpio0>;
337 interrupts = <20 GPIO_ACTIVE_LOW>;
338 pinctrl-names = "default";
339 pinctrl-0 = <&tca6416_pins>;
373 #include "tps65910.dtsi"
376 vcc1-supply = <&vbat>;
377 vcc2-supply = <&vbat>;
378 vcc3-supply = <&vbat>;
379 vcc4-supply = <&vbat>;
380 vcc5-supply = <&vbat>;
381 vcc6-supply = <&vbat>;
382 vcc7-supply = <&vbat>;
383 vccio-supply = <&vbat>;
385 ti,en-ck32k-xtal = <1>;
388 vrtc_reg: regulator@0 {
392 vio_reg: regulator@1 {
396 vdd1_reg: regulator@2 {
397 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
398 regulator-name = "vdd_mpu";
399 regulator-min-microvolt = <912500>;
400 regulator-max-microvolt = <1312500>;
405 vdd2_reg: regulator@3 {
406 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
407 regulator-name = "vdd_core";
408 regulator-min-microvolt = <912500>;
409 regulator-max-microvolt = <1150000>;
414 vdd3_reg: regulator@4 {
418 vdig1_reg: regulator@5 {
422 vdig2_reg: regulator@6 {
426 vpll_reg: regulator@7 {
430 vdac_reg: regulator@8 {
434 vaux1_reg: regulator@9 {
438 vaux2_reg: regulator@10 {
442 vaux33_reg: regulator@11 {
446 vmmc_reg: regulator@12 {
447 regulator-min-microvolt = <1800000>;
448 regulator-max-microvolt = <3300000>;
455 pinctrl-names = "default", "sleep";
456 pinctrl-0 = <&cpsw_default>;
457 pinctrl-1 = <&cpsw_sleep>;
464 pinctrl-names = "default", "sleep";
465 pinctrl-0 = <&davinci_mdio_default>;
466 pinctrl-1 = <&davinci_mdio_sleep>;
472 phy_id = <&davinci_mdio>, <0>;
474 dual_emac_res_vlan = <1>;
478 phy_id = <&davinci_mdio>, <7>;
479 phy-mode = "rgmii-txid";
480 dual_emac_res_vlan = <2>;
484 rmii-clock-ext = <1>;
488 vmmc-supply = <&vmmc_reg>;
494 vmmc-supply = <&wl12xx_vmmc>;
498 pinctrl-names = "default";
499 pinctrl-0 = <&mmc2_pins>;
501 #address-cells = <1>;
504 compatible = "ti,wl1835";
506 interrupt-parent = <&gpio3>;
507 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
524 pinctrl-names = "default";
525 pinctrl-0 = <&dcan1_pins>;