arch/arm/boot/dts/am335x-tx48.dts

   1 /*
   2  * Copyright (C) 2013 Ka-Ro electronics GmbH - http://www.karo-electronics.com
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 /dts-v1/;
   9
  10 /include/ "am33xx.dtsi"
  11
  12 / {
  13         model = "Ka-Ro electronics TX48 module (TI AM335x)";
  14         compatible = "karo,am335x-tx48", "ti,am33xx";
  15
  16         aliases {
  17                 ethernet0 = &cpsw_emac0;
  18                 ethernet1 = &cpsw_emac1;
  19         };
  20
  21         cpus {
  22                 cpu@0 {
  23 //                      cpu0-supply = <&sw2_reg>;
  24                 };
  25         };
  26
  27         memory {
  28                 device_type = "memory";
  29                 reg = <0 0>; /* will be set up by bootloader */
  30         };
  31
  32         reg_3v3: fixedregulator@0 {
  33                 compatible = "regulator-fixed";
  34                 regulator-name = "vbat";
  35                 regulator-min-microvolt = <3300000>;
  36                 regulator-max-microvolt = <3300000>;
  37                 regulator-boot-on;
  38         };
  39 };
  40
  41 &am33xx_pinmux {
  42         pinctrl-names = "default";
  43
  44         /* pinconfig:
  45                 0x08 PU/PD enable
  46                 0x10 PULLUP select
  47                 0x20 INPUT active
  48                 0x40 FAST slew rate
  49         */
  50         pinctrl_gpmc_1: gpmcgrp-1 {
  51                 pinctrl-single,pins = <
  52                         0x00 0x38       /* gpmc_ad0.gpmc_ad0, I/O | MODE0; GPMC_AD0 */
  53                         0x04 0x38       /* gpmc_ad1.gpmc_ad1, I/O | MODE0; GPMC_AD0 */
  54                         0x08 0x38       /* gpmc_ad2.gpmc_ad2, I/O | MODE0; GPMC_AD0 */
  55                         0x0c 0x38       /* gpmc_ad3.gpmc_ad3, I/O | MODE0; GPMC_AD0 */
  56                         0x10 0x38       /* gpmc_ad4.gpmc_ad4, I/O | MODE0; GPMC_AD0 */
  57                         0x14 0x38       /* gpmc_ad5.gpmc_ad5, I/O | MODE0; GPMC_AD0 */
  58                         0x18 0x38       /* gpmc_ad6.gpmc_ad6, I/O | MODE0; GPMC_AD0 */
  59                         0x1c 0x38       /* gpmc_ad7.gpmc_ad7, I/O | MODE0; GPMC_AD0 */
  60                         0x9c 0x18       /* gpmc_ben0_cle.gpmc_ben0_cle, OUTPUT | MODE0; GPMC_BEn0_CLE */
  61                         0x90 0x18       /* gpmc_advn_ale.gpmc_advn_ale, OUTPUT | MODE0; GPMC_ADVn_ALE */
  62                         0x7c 0x18       /* gpmc_csn0.gpmc_csn0, OUTPUT | MODE0; GPMC_CSn0 */
  63                         0x94 0x18       /* gpmc_oe_re.gpmc_oe_re, I/O | MODE0; GPMC_OE_RE */
  64                         0x98 0x18       /* gpmc_wen.gpmc_wen, OUTPUT | MODE0; GPMC_WEn */
  65                         0x74 0x18       /* gpmc_wpn.gpmc_wpn, OUTPUT | MODE0; GPMC_WPn */
  66                         0x70 0x38       /* gpmc_wait0.gpmc_wait0, INPUT | MODE0; GPMC_WAIT0 */
  67                 >;
  68         };
  69
  70         pinctrl_usb_host0_1: usbhostgrp-1 {
  71                 pinctrl-single,pins = <
  72                         0x234 0x0       /* usb1_drvvbus.usb1_drvvbus, OUTPUT | MODE0; USBH_VBUSEN */
  73                         0x21c 0x7       /* usb0_drvvbus.gpio0_18, INPUT | MODE0; #USBH_OC */
  74                 >;
  75         };
  76
  77         pinctrl_usbotg0_1: usbotggrp-1 { // USB-OTG / 2nd CAN
  78                 pinctrl-single,pins = <
  79                         0x100 0x7       /* mmc0_clk.gpio2_30, OUTPUT | MODE7; USBOTG_VBUSEN */
  80                         0x104 0x7       /* mmc0_cmd.gpio2_31, OUTPUT | MODE7; #USBOTG_OC */
  81                 >;
  82         };
  83
  84         pinctrl_dcan1_1: dcan1grp-1 { // USB-OTG / 2nd CAN
  85                 pinctrl-single,pins = <
  86                         0x100 0x24      /* mmc0_clk.dcan1_tx, OUTPUT | MODE4; USBOTG_VBUSEN */
  87                         0x104 0x24      /* mmc0_cmd.dcan1_rx,  INPUT | MODE4; #USBOTG_OC */
  88                 >;
  89         };
  90
  91         pinctrl_i2c0_1: i2c0grp-1 {
  92                 pinctrl-single,pins = <
  93                         0x188 0x30      /* i2c0_sda.i2c0_sda, I/O OD PU | MODE0; I2C_DATA */
  94                         0x18c 0x30      /* i2c0_scl.i2c0_scl, I/O OD PU | MODE0; I2C_CLK */
  95                 >;
  96         };
  97
  98         pinctrl_pwm0_1: pwm0grp-1 {
  99                 pinctrl-single,pins = <
 100                         0x190 0x1       /* mcasp0_aclkx.ehrpwm0a, OUTPUT | MODE1; PWM */
 101                 >;
 102         };
 103
 104         pinctrl_ow0_1: ow0grp-1 {
 105                 pinctrl-single,pins = <
 106                         0xf4 0x27       /* mmc0_dat2.gpio2_27, OUTPUT | MODE7; OWDAT */
 107                 >;
 108         };
 109
 110         pinctrl_cspi0_1: cspi0grp-1 {
 111                 pinctrl-single,pins = <
 112                         0x15c 0x0       /* spi0_cs0.spi0_cs0, I/O | MODE0; CSPI_SS */
 113                         0x160 0x0       /* spi0_cs1.spi0_cs1, I/O | MODE0; CSPI_SS */
 114                         0x154 0x0       /* spi0_d0.spi0_d0, I/O | MODE0; CSPI_MOSI */
 115                         0x158 0x20      /* spi0_d1.spi0_d1, I/O | MODE0; CSPI_MISO */
 116                         0x150 0x0       /* spi0_sclk.spi0_sclk, I/O | MODE0; CSPI_SCLK */
 117                 >;
 118         };
 119
 120         pinctrl_mmc1_1: mmc1grp-1 {
 121                 pinctrl-single,pins = <
 122                         0x194 0x24      /* mcasp0_fsx.mmc1_sdcd, INPUT | MODE4; SD1_CD */
 123                         0x12c 0x24      /* mii1_tx_clk.mmc1_dat0, I/O | MODE4; SD1_D[0] */
 124                         0x130 0x24      /* mii1_rx_clk.mmc1_dat1, I/O | MODE4; SD1_D[1] */
 125                         0x134 0x24      /* mii1_rxd3.mmc1_dat2, I/O | MODE4; SD1_D[2] */
 126                         0x138 0x24      /* mii1_rxd2.mmc1_dat3, I/O | MODE4; SD1_D[3] */
 127                         0x84  0x22      /* gpmc_csn2.mmc1_cmd, I/O | MODE2; SD1_CMD */
 128                         0x80  0x2       /* gpmc_csn1.mmc1_clk, I/O | MODE2; SD1_CLK */
 129                 >;
 130         };
 131
 132         pinctrl_uart1_1: uart1grp-1 {
 133                 pinctrl-single,pins = <
 134                         0x174 0x0       /* uart0_txd.uart0_txd, OUTPUT | MODE0; TXD */
 135                         0x170 0x20      /* uart0_rxd.uart0_rxd,  INPUT | MODE0; RXD */
 136                         0x168 0x20      /* uart0_ctsn.uart0_ctsn,  INPUT | MODE0; RTS/CTS IN */
 137                         0x16c 0x0       /* uart0_rtsn.uart0_rtsn, OUTPUT | MODE0; CTS/RTS OUT */
 138                 >;
 139         };
 140
 141         pinctrl_uart2_1: uart2grp-1 {
 142                 pinctrl-single,pins = <
 143                         0x184 0x0       /* uart1_txd.uart1_txd, OUTPUT | MODE0; TXD */
 144                         0x180 0x0       /* uart1_rxd.uart1_rxd,  INPUT | MODE0; RXD */
 145                         0x178 0x0       /* uart1_ctsn.uart1_ctsn,  INPUT | MODE0; RTS/CTS IN */
 146                         0x17c 0x0       /* uart1_rtsn.uart1_rtsn, OUTPUT | MODE0; CTS/RTS OUT */
 147                 >;
 148         };
 149
 150         pinctrl_uart6_1: uart6grp-1 {
 151                 pinctrl-single,pins = <
 152                         0x118 0x3       /* mii1_rx_dv.uart5_txd, OUTPUT | MODE3; TXD */
 153                         0x108 0x3       /* mii1_col.uart5_rxd, INPUT | MODE3; RXD */
 154                         0xf8  0x2       /* mmc0_dat1.uart5_ctsn,  INPUT | MODE2; RTS/CTS IN */
 155                         0xfc  0x2       /* mmc0_dat0.uart5_rtsn, OUTPUT | MODE2; CTS/RTS OUT */
 156                 >;
 157         };
 158
 159         pinctrl_matrix_keypad0_1: matrix-keypad0grp-1 {
 160                 pinctrl-single,pins = <
 161                         0xf0  0x7       /* mmc0_dat3.gpio2_26, I/O | MODE7; KP_COL[0] */
 162                         0x19c 0x7       /* mcasp0_ahclkr.gpio3_17, I/O | MODE7; KP_COL[1] */
 163                         0x164 0x7       /* ecap0_in_pwm0_out.gpio0_7, I/O | MODE7; KP_COL[2] */
 164                         0x78  0x7       /* gpmc_ben1.gpio1_28, I/O | MODE7; KP_COL[3] */
 165                         0x1b0 0x27      /* xdma_event_intr0.gpio0_19, I/O | MODE7; KP_ROW[0] */
 166                         0x1b4 0x27      /* xdma_event_intr1.gpio0_20, I/O | MODE7; KP_ROW[1] */
 167                         0x8c  0x27      /* gpmc_clk.gpio2_1, I/O | MODE7; KP_ROW[2] */
 168                         0x88  0x27      /* gpmc_csn3.gpio2_0, I/O | MODE7; KP_ROW[3] */
 169                 >;
 170         };
 171         pinctrl_dcan0_1: dcan0grp-1 {
 172                 pinctrl-single,pins = <
 173                         0x11c 0x1       /* mii1_txd3.dcan0_tx, OUTPUT | MODE1; TXCAN */
 174                         0x120 0x1       /* mii1_txd2.dcan0_rx,  INPUT | MODE1; RXCAN */
 175                 >;
 176         };
 177         pinctrl_ssi0_1: ssi0grp-1 {
 178                 pinctrl-single,pins = <
 179                         0x198 0x7       /* mcasp0_axr0.gpio3_16, I/O | MODE7; SSI1_INT */
 180                         0x1a8 0x3       /* mcasp0_axr1.mcasp1_axr0, I/O | MODE3; SSI1_RXD */
 181                         0x1ac 0x3       /* mcasp0_ahclkx.mcasp1_axr1, I/O | MODE3; SSI1_TXD */
 182                         0x1a0 0x3       /* mcasp0_aclkr.mcasp1_aclkx, I/O | MODE3; SSI1_CLK */
 183                         0x1a4 0x0       /* mcasp0_fsr.mcasp1_fsx, I/O | MODE3; SSI1_FS */
 184                 >;
 185         };
 186         pinctrl_lcd0_1: lcd0grp-1 {
 187                 pinctrl-single,pins = <
 188                         0x20 0x0        /* gpmc_ad8.lcd_data23, OUTPUT | MODE1; LD0 */
 189                         0x2c 0x0        /* gpmc_ad11.lcd_data20, OUTPUT | MODE1; LD1 */
 190                         0x38 0x0        /* gpmc_ad14.lcd_data17, OUTPUT | MODE1; LD2 */
 191                         0xcc 0x0        /* lcd_data11.lcd_data11, I/O | MODE0; LD3 */
 192                         0xd0 0x0        /* lcd_data12.lcd_data12, I/O | MODE0; LD4 */
 193                         0xd4 0x0        /* lcd_data13.lcd_data13, I/O | MODE0; LD5 */
 194                         0xd8 0x0        /* lcd_data14.lcd_data14, I/O | MODE0; LD6 */
 195                         0xdc 0x0        /* lcd_data15.lcd_data15, I/O | MODE0; LD7 */
 196                         0x24 0x0        /* gpmc_ad9.lcd_data22, OUTPUT | MODE1; LD8 */
 197                         0x30 0x0        /* gpmc_ad12.lcd_data19, OUTPUT | MODE1; LD9 */
 198                         0xb4 0x0        /* lcd_data5.lcd_data5, I/O | MODE0; LD10 */
 199                         0xb8 0x0        /* lcd_data6.lcd_data6, I/O | MODE0; LD11 */
 200                         0xbc 0x0        /* lcd_data7.lcd_data7, I/O | MODE0; LD12 */
 201                         0xc0 0x0        /* lcd_data8.lcd_data8, I/O | MODE0; LD13 */
 202                         0xc4 0x0        /* lcd_data9.lcd_data9, I/O | MODE0; LD14 */
 203                         0xc8 0x0        /* lcd_data10.lcd_data10, I/O | MODE0; LD15 */
 204                         0x28 0x0        /* gpmc_ad10.lcd_data21, OUTPUT | MODE1; LD16 */
 205                         0x34 0x0        /* gpmc_ad13.lcd_data18, OUTPUT | MODE1; LD17 */
 206                         0x3c 0x0        /* gpmc_ad15.lcd_data16, OUTPUT | MODE1; LD18 */
 207                         0xa0 0x0        /* lcd_data0.lcd_data0, I/O | MODE0; LD19 */
 208                         0xa4 0x0        /* lcd_data1.lcd_data1, I/O | MODE0; LD20 */
 209                         0xa8 0x0        /* lcd_data2.lcd_data2, I/O | MODE0; LD21 */
 210                         0xac 0x0        /* lcd_data3.lcd_data3, I/O | MODE0; LD22 */
 211                         0xb0 0x0        /* lcd_data4.lcd_data4, I/O | MODE0; LD23 */
 212                         0xe4 0x0        /* lcd_hsync.lcd_hsync, OUTPUT | MODE0; HSYNC */
 213                         0xe0 0x0        /* lcd_vsync.lcd_vsync, OUTPUT | MODE0; VSYNC */
 214                         0xec 0x0        /* lcd_ac_bias_en.lcd_ac_bias_en, OUTPUT | MODE0; OE_ACD */
 215                         0xe8 0x0        /* lcd_pclk.lcd_pclk, OUTPUT | MODE0; LSCLK */
 216                 >;
 217         };
 218
 219         pinctrl_tsc2007: tsc2007grp-1 {
 220                 pinctrl-single,pins = <
 221                         0x198 0x27      /* mcasp0_axr0.gpio3_16, I/O | MODE 7; GPIO3_16 */
 222                 >;
 223         };
 224
 225         leds {
 226                 compatible = "gpio-leds";
 227                 heartbeat {
 228                         label = "heartbeat";
 229                         gpios = <&gpio1 26 0>;
 230                         linux,default-trigger = "heartbeat";
 231                 };
 232         };
 233
 234         matrix_keypad: matrix_keypad@0 {
 235                 compatible = "gpio-matrix-keypad";
 236                 debounce-delay-ms = <5>;
 237                 col-scan-delay-us = <2>;
 238
 239                 pinctrl-names = "default";
 240                 pinctrl-0 = <&pinctrl_matrix_keypad0_1>;
 241
 242                 row-gpios = <
 243                         &gpio0 19 0
 244                         &gpio0 20 0
 245                         &gpio2  1 0
 246                         &gpio2  0 0
 247                 >;
 248
 249                 col-gpios = <
 250                         &gpio2 26 0
 251                         &gpio3 17 0
 252                         &gpio0 7 0
 253                         &gpio1 28 0
 254                 >;
 255
 256                 linux,keymap = <
 257                         0x00000074      /* POWER */
 258                 >;
 259         };
 260 };
 261
 262 &cpsw_emac0 {
 263         phy_id = <&davinci_mdio>, <0>;
 264 };
 265
 266 &cpsw_emac1 {
 267         phy_id = <&davinci_mdio>, <1>;
 268 };
 269
 270 &uart1 {
 271         status = "okay";
 272         pinctrl-names = "default";
 273         pinctrl-0 = <&pinctrl_uart1_1>;
 274 };
 275
 276 &uart2 {
 277         status = "okay";
 278         pinctrl-names = "default";
 279         pinctrl-0 = <&pinctrl_uart2_1>;
 280 };
 281
 282 &uart6 {
 283         status = "okay";
 284         pinctrl-names = "default";
 285         pinctrl-0 = <&pinctrl_uart6_1>;
 286 };
 287
 288 &gpmc {
 289         pinctrl-names = "default";
 290         pinctrl-0 = <&pinctrl_gpmc_1>;
 291
 292         omap2-nand@0 {
 293                 reg = <0 0 0>;
 294                 nand-bus-width = <8>;
 295                 ti,nand-ecc-opt = "bch8";
 296
 297                 gpmc,sync-clk = <0>;
 298                 gpmc,cs-on = <0>;
 299                 gpmc,cs-rd-off = <44>;
 300                 gpmc,cs-wr-off = <44>;
 301                 gpmc,adv-on = <6>;
 302                 gpmc,adv-rd-off = <34>;
 303                 gpmc,adv-wr-off = <44>;
 304                 gpmc,we-off = <40>;
 305                 gpmc,oe-off = <54>;
 306                 gpmc,access = <64>;
 307                 gpmc,rd-cycle = <82>;
 308                 gpmc,wr-cycle = <82>;
 309                 gpmc,wr-access = <40>;
 310                 gpmc,wr-data-mux-bus = <0>;
 311
 312                 #address-cells = <1>;
 313                 #size-cells = <1>;
 314
 315                 partitions {
 316                         /* filled in by U-Boot */
 317                 };
 318         };
 319 };
 320
 321 &i2c1 {
 322         status = "okay";
 323         pinctrl-names = "default";
 324         pinctrl-0 = <&pinctrl_i2c0_1>;
 325
 326         rtc1: ds1339@68 {
 327                 compatible = "dallas,ds1339";
 328                 reg = <0x68>;
 329         };
 330
 331         pmic: lt3589@34 {
 332                 compatible = "lt,lt3589";
 333                 reg = <0x34>;
 334         };
 335
 336         codec: sgtl5000@0a {
 337                 compatible = "fsl,sgtl5000";
 338                 reg = <0x0a>;
 339                 VDDA-supply = <&reg_2v5>;
 340                 VDDIO-supply = <&sw4_reg>;
 341         };
 342
 343         touchscreen: tsc2007@48 {
 344                 compatible = "ti,tsc2007";
 345                 reg = <0x48>;
 346                 interrupt-parent = <&gpio3>;
 347                 interrupts = <16 0>;
 348                 pendown-gpios = <&gpio3 16 1>;
 349                 model = "2007";
 350                 x-plate-ohms = <660>;
 351                 pinctrl-names = "default";
 352                 pinctrl-0 = <&pinctrl_tsc2007>;
 353         };
 354
 355         polytouch: edt-ft5x06@38 {
 356                 compatible = "edt,edt-ft5x06";
 357                 reg = <0x38>;
 358                 interrupt-parent = <&gpio1>;
 359                 interrupts = <17>;
 360                 // TODO: add DT support to driver
 361                 reset-gpios = <&gpio1 18 1>;
 362                 wake-gpios = <&gpio1 27 0>;
 363         };
 364 };
 365
 366 &pmic {
 367         regulators {
 368                 sw1_reg: regulator@4 {
 369                         // VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance
 370                         regulator-name = "vdd_core";
 371                         regulator-min-microvolt = <912000>;
 372                         regulator-max-microvolt = <1144000>;
 373                         regulator-boot-on;
 374                         regulator-always-on;
 375                 };
 376
 377                 sw2_reg: regulator@5 {
 378                         // VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance
 379                         regulator-name = "vdd_mpu";
 380                         regulator-min-microvolt = <912000>;
 381                         regulator-max-microvolt = <1310400>;
 382                         regulator-boot-on;
 383                         regulator-always-on;
 384                 };
 385
 386                 sw4_reg: regulator@7 {
 387                         compatible = "regulator-fixed";
 388                         regulator-name = "3v3";
 389                         regulator-min-microvolt = <3300000>;
 390                         regulator-max-microvolt = <3300000>;
 391                         regulator-always-on;
 392                 };
 393         };
 394 };
 395
 396 &codec {
 397         regulators {
 398                 reg_2v5: regulator@0 {
 399                         compatible = "regulator-fixed";
 400                         regulator-name = "2v5";
 401                         regulator-min-microvolt = <2500000>;
 402                         regulator-max-microvolt = <2500000>;
 403                         regulator-always-on;
 404                 };
 405         };
 406 };
 407
 408 &dcan0 {
 409         status = "okay";
 410 };
 411
 412 &dcan1 {
 413         status = "okay";
 414 };
 415
 416 &spi0 {
 417         status = "okay";
 418         pinctrl-names = "default";
 419         pinctrl-0 = <&pinctrl_cspi0_1>;
 420 };
 421
 422 &mmchs1 {
 423         status = "okay";
 424         cd-gpios = <&gpio3 15 1>;
 425         pinctrl-names = "default";
 426         pinctrl-0 = <&pinctrl_mmc1_1>;
 427         vmmc-supply = <&reg_3v3>;
 428 };