2 * Device Tree Source for AM4372 SoC
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include "skeleton.dtsi"
16 compatible = "ti,am4372", "ti,am43";
17 interrupt-parent = <&gic>;
28 compatible = "arm,cortex-a9";
34 gic: interrupt-controller@48241000 {
35 compatible = "arm,cortex-a9-gic";
37 #interrupt-cells = <3>;
38 reg = <0x48241000 0x1000>,
43 compatible = "simple-bus";
48 uart0: serial@44e09000 {
49 compatible = "ti,am4372-uart","ti,omap2-uart";
50 reg = <0x44e09000 0x2000>;
51 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
55 uart1: serial@48022000 {
56 compatible = "ti,am4372-uart","ti,omap2-uart";
57 reg = <0x48022000 0x2000>;
58 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
63 uart2: serial@48024000 {
64 compatible = "ti,am4372-uart","ti,omap2-uart";
65 reg = <0x48024000 0x2000>;
66 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
71 uart3: serial@481a6000 {
72 compatible = "ti,am4372-uart","ti,omap2-uart";
73 reg = <0x481a6000 0x2000>;
74 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
79 uart4: serial@481a8000 {
80 compatible = "ti,am4372-uart","ti,omap2-uart";
81 reg = <0x481a8000 0x2000>;
82 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
87 uart5: serial@481aa000 {
88 compatible = "ti,am4372-uart","ti,omap2-uart";
89 reg = <0x481aa000 0x2000>;
90 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
95 timer1: timer@44e31000 {
96 compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
97 reg = <0x44e31000 0x400>;
98 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
100 ti,hwmods = "timer1";
103 timer2: timer@48040000 {
104 compatible = "ti,am4372-timer","ti,am335x-timer";
105 reg = <0x48040000 0x400>;
106 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
107 ti,hwmods = "timer2";
110 timer3: timer@48042000 {
111 compatible = "ti,am4372-timer","ti,am335x-timer";
112 reg = <0x48042000 0x400>;
113 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
114 ti,hwmods = "timer3";
118 timer4: timer@48044000 {
119 compatible = "ti,am4372-timer","ti,am335x-timer";
120 reg = <0x48044000 0x400>;
121 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
123 ti,hwmods = "timer4";
127 timer5: timer@48046000 {
128 compatible = "ti,am4372-timer","ti,am335x-timer";
129 reg = <0x48046000 0x400>;
130 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
132 ti,hwmods = "timer5";
136 timer6: timer@48048000 {
137 compatible = "ti,am4372-timer","ti,am335x-timer";
138 reg = <0x48048000 0x400>;
139 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
141 ti,hwmods = "timer6";
145 timer7: timer@4804a000 {
146 compatible = "ti,am4372-timer","ti,am335x-timer";
147 reg = <0x4804a000 0x400>;
148 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
150 ti,hwmods = "timer7";
154 timer8: timer@481c1000 {
155 compatible = "ti,am4372-timer","ti,am335x-timer";
156 reg = <0x481c1000 0x400>;
157 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
158 ti,hwmods = "timer8";
162 timer9: timer@4833d000 {
163 compatible = "ti,am4372-timer","ti,am335x-timer";
164 reg = <0x4833d000 0x400>;
165 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
166 ti,hwmods = "timer9";
170 timer10: timer@4833f000 {
171 compatible = "ti,am4372-timer","ti,am335x-timer";
172 reg = <0x4833f000 0x400>;
173 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
174 ti,hwmods = "timer10";
178 timer11: timer@48341000 {
179 compatible = "ti,am4372-timer","ti,am335x-timer";
180 reg = <0x48341000 0x400>;
181 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
182 ti,hwmods = "timer11";
186 counter32k: counter@44e86000 {
187 compatible = "ti,am4372-counter32k","ti,omap-counter32k";
188 reg = <0x44e86000 0x40>;
189 ti,hwmods = "counter_32k";
193 compatible = "ti,am4372-rtc","ti,da830-rtc";
194 reg = <0x44e3e000 0x1000>;
195 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
196 GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
202 compatible = "ti,am4372-wdt","ti,omap3-wdt";
203 reg = <0x44e35000 0x1000>;
204 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
205 ti,hwmods = "wd_timer2";
209 gpio0: gpio@44e07000 {
210 compatible = "ti,am4372-gpio","ti,omap4-gpio";
211 reg = <0x44e07000 0x1000>;
212 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
215 interrupt-controller;
216 #interrupt-cells = <2>;
221 gpio1: gpio@4804c000 {
222 compatible = "ti,am4372-gpio","ti,omap4-gpio";
223 reg = <0x4804c000 0x1000>;
224 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
227 interrupt-controller;
228 #interrupt-cells = <2>;
233 gpio2: gpio@481ac000 {
234 compatible = "ti,am4372-gpio","ti,omap4-gpio";
235 reg = <0x481ac000 0x1000>;
236 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
239 interrupt-controller;
240 #interrupt-cells = <2>;
245 gpio3: gpio@481ae000 {
246 compatible = "ti,am4372-gpio","ti,omap4-gpio";
247 reg = <0x481ae000 0x1000>;
248 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
251 interrupt-controller;
252 #interrupt-cells = <2>;
257 gpio4: gpio@48320000 {
258 compatible = "ti,am4372-gpio","ti,omap4-gpio";
259 reg = <0x48320000 0x1000>;
260 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
263 interrupt-controller;
264 #interrupt-cells = <2>;
269 gpio5: gpio@48322000 {
270 compatible = "ti,am4372-gpio","ti,omap4-gpio";
271 reg = <0x48322000 0x1000>;
272 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
275 interrupt-controller;
276 #interrupt-cells = <2>;
282 compatible = "ti,am4372-i2c","ti,omap4-i2c";
283 reg = <0x44e0b000 0x1000>;
284 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
286 #address-cells = <1>;
292 compatible = "ti,am4372-i2c","ti,omap4-i2c";
293 reg = <0x4802a000 0x1000>;
294 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
296 #address-cells = <1>;
302 compatible = "ti,am4372-i2c","ti,omap4-i2c";
303 reg = <0x4819c000 0x1000>;
304 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
306 #address-cells = <1>;
312 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
313 reg = <0x48030000 0x400>;
314 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
316 #address-cells = <1>;
322 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
323 reg = <0x481a0000 0x400>;
324 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
326 #address-cells = <1>;
332 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
333 reg = <0x481a2000 0x400>;
334 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
336 #address-cells = <1>;
342 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
343 reg = <0x481a4000 0x400>;
344 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
346 #address-cells = <1>;
352 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
353 reg = <0x48345000 0x400>;
354 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
356 #address-cells = <1>;
361 mac: ethernet@4a100000 {
362 compatible = "ti,am4372-cpsw","ti,cpsw";
363 reg = <0x4a100000 0x800
365 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH
366 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH
367 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
368 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
369 ti,hwmods = "cpgmac0";
373 epwmss0: epwmss@48300000 {
374 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
375 reg = <0x48300000 0x10>;
376 ti,hwmods = "epwmss0";
380 epwmss1: epwmss@48302000 {
381 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
382 reg = <0x48302000 0x10>;
383 ti,hwmods = "epwmss1";
387 epwmss2: epwmss@48304000 {
388 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
389 reg = <0x48304000 0x10>;
390 ti,hwmods = "epwmss2";
394 epwmss3: epwmss@48306000 {
395 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
396 reg = <0x48306000 0x10>;
397 ti,hwmods = "epwmss3";
401 epwmss4: epwmss@48308000 {
402 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
403 reg = <0x48308000 0x10>;
404 ti,hwmods = "epwmss4";
408 epwmss5: epwmss@4830a000 {
409 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
410 reg = <0x4830a000 0x10>;
411 ti,hwmods = "epwmss5";
416 compatible = "ti,omap4-aes";
418 reg = <0x53501000 0xa0>;
419 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
423 compatible = "ti,omap4-des";
425 reg = <0x53701000 0xa0>;
426 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;