2 * Device Tree Source for AM4372 SoC
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include "skeleton.dtsi"
16 compatible = "ti,am4372", "ti,am43";
17 interrupt-parent = <&gic>;
25 ethernet0 = &cpsw_emac0;
26 ethernet1 = &cpsw_emac1;
33 compatible = "arm,cortex-a9";
39 gic: interrupt-controller@48241000 {
40 compatible = "arm,cortex-a9-gic";
42 #interrupt-cells = <3>;
43 reg = <0x48241000 0x1000>,
47 l2-cache-controller@48242000 {
48 compatible = "arm,pl310-cache";
49 reg = <0x48242000 0x1000>;
54 am43xx_pinmux: pinmux@44e10800 {
55 compatible = "pinctrl-single";
56 reg = <0x44e10800 0x31c>;
59 pinctrl-single,register-width = <32>;
60 pinctrl-single,function-mask = <0xffffffff>;
64 compatible = "simple-bus";
68 ti,hwmods = "l3_main";
71 compatible = "ti,edma3";
72 ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
73 reg = <0x49000000 0x10000>,
75 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
76 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
77 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
80 ti,edma-regions = <4>;
81 ti,edma-slots = <256>;
84 uart0: serial@44e09000 {
85 compatible = "ti,am4372-uart","ti,omap2-uart";
86 reg = <0x44e09000 0x2000>;
87 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
91 uart1: serial@48022000 {
92 compatible = "ti,am4372-uart","ti,omap2-uart";
93 reg = <0x48022000 0x2000>;
94 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
99 uart2: serial@48024000 {
100 compatible = "ti,am4372-uart","ti,omap2-uart";
101 reg = <0x48024000 0x2000>;
102 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
107 uart3: serial@481a6000 {
108 compatible = "ti,am4372-uart","ti,omap2-uart";
109 reg = <0x481a6000 0x2000>;
110 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
115 uart4: serial@481a8000 {
116 compatible = "ti,am4372-uart","ti,omap2-uart";
117 reg = <0x481a8000 0x2000>;
118 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
123 uart5: serial@481aa000 {
124 compatible = "ti,am4372-uart","ti,omap2-uart";
125 reg = <0x481aa000 0x2000>;
126 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
131 mailbox: mailbox@480C8000 {
132 compatible = "ti,omap4-mailbox";
133 reg = <0x480C8000 0x200>;
134 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
135 ti,hwmods = "mailbox";
136 ti,mbox-num-users = <4>;
137 ti,mbox-num-fifos = <8>;
138 ti,mbox-names = "wkup_m3";
139 ti,mbox-data = <0 0 0 0>;
143 timer1: timer@44e31000 {
144 compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
145 reg = <0x44e31000 0x400>;
146 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
148 ti,hwmods = "timer1";
151 timer2: timer@48040000 {
152 compatible = "ti,am4372-timer","ti,am335x-timer";
153 reg = <0x48040000 0x400>;
154 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
155 ti,hwmods = "timer2";
158 timer3: timer@48042000 {
159 compatible = "ti,am4372-timer","ti,am335x-timer";
160 reg = <0x48042000 0x400>;
161 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
162 ti,hwmods = "timer3";
166 timer4: timer@48044000 {
167 compatible = "ti,am4372-timer","ti,am335x-timer";
168 reg = <0x48044000 0x400>;
169 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
171 ti,hwmods = "timer4";
175 timer5: timer@48046000 {
176 compatible = "ti,am4372-timer","ti,am335x-timer";
177 reg = <0x48046000 0x400>;
178 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
180 ti,hwmods = "timer5";
184 timer6: timer@48048000 {
185 compatible = "ti,am4372-timer","ti,am335x-timer";
186 reg = <0x48048000 0x400>;
187 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
189 ti,hwmods = "timer6";
193 timer7: timer@4804a000 {
194 compatible = "ti,am4372-timer","ti,am335x-timer";
195 reg = <0x4804a000 0x400>;
196 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
198 ti,hwmods = "timer7";
202 timer8: timer@481c1000 {
203 compatible = "ti,am4372-timer","ti,am335x-timer";
204 reg = <0x481c1000 0x400>;
205 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
206 ti,hwmods = "timer8";
210 timer9: timer@4833d000 {
211 compatible = "ti,am4372-timer","ti,am335x-timer";
212 reg = <0x4833d000 0x400>;
213 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
214 ti,hwmods = "timer9";
218 timer10: timer@4833f000 {
219 compatible = "ti,am4372-timer","ti,am335x-timer";
220 reg = <0x4833f000 0x400>;
221 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
222 ti,hwmods = "timer10";
226 timer11: timer@48341000 {
227 compatible = "ti,am4372-timer","ti,am335x-timer";
228 reg = <0x48341000 0x400>;
229 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
230 ti,hwmods = "timer11";
234 counter32k: counter@44e86000 {
235 compatible = "ti,am4372-counter32k","ti,omap-counter32k";
236 reg = <0x44e86000 0x40>;
237 ti,hwmods = "counter_32k";
241 compatible = "ti,am4372-rtc","ti,da830-rtc";
242 reg = <0x44e3e000 0x1000>;
243 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
244 GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
250 compatible = "ti,am4372-wdt","ti,omap3-wdt";
251 reg = <0x44e35000 0x1000>;
252 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
253 ti,hwmods = "wd_timer2";
256 gpio0: gpio@44e07000 {
257 compatible = "ti,am4372-gpio","ti,omap4-gpio";
258 reg = <0x44e07000 0x1000>;
259 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
262 interrupt-controller;
263 #interrupt-cells = <2>;
268 gpio1: gpio@4804c000 {
269 compatible = "ti,am4372-gpio","ti,omap4-gpio";
270 reg = <0x4804c000 0x1000>;
271 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
274 interrupt-controller;
275 #interrupt-cells = <2>;
280 gpio2: gpio@481ac000 {
281 compatible = "ti,am4372-gpio","ti,omap4-gpio";
282 reg = <0x481ac000 0x1000>;
283 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
286 interrupt-controller;
287 #interrupt-cells = <2>;
292 gpio3: gpio@481ae000 {
293 compatible = "ti,am4372-gpio","ti,omap4-gpio";
294 reg = <0x481ae000 0x1000>;
295 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
298 interrupt-controller;
299 #interrupt-cells = <2>;
304 gpio4: gpio@48320000 {
305 compatible = "ti,am4372-gpio","ti,omap4-gpio";
306 reg = <0x48320000 0x1000>;
307 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
310 interrupt-controller;
311 #interrupt-cells = <2>;
316 gpio5: gpio@48322000 {
317 compatible = "ti,am4372-gpio","ti,omap4-gpio";
318 reg = <0x48322000 0x1000>;
319 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
322 interrupt-controller;
323 #interrupt-cells = <2>;
329 compatible = "ti,am4372-i2c","ti,omap4-i2c";
330 reg = <0x44e0b000 0x1000>;
331 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
333 #address-cells = <1>;
339 compatible = "ti,am4372-i2c","ti,omap4-i2c";
340 reg = <0x4802a000 0x1000>;
341 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
343 #address-cells = <1>;
349 compatible = "ti,am4372-i2c","ti,omap4-i2c";
350 reg = <0x4819c000 0x1000>;
351 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
353 #address-cells = <1>;
359 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
360 reg = <0x48030000 0x400>;
361 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
363 #address-cells = <1>;
369 compatible = "ti,omap4-hsmmc";
370 reg = <0x48060000 0x1000>;
373 ti,needs-special-reset;
376 dma-names = "tx", "rx";
377 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
382 compatible = "ti,omap4-hsmmc";
383 reg = <0x481d8000 0x1000>;
385 ti,needs-special-reset;
388 dma-names = "tx", "rx";
389 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
394 compatible = "ti,omap4-hsmmc";
395 reg = <0x47810000 0x1000>;
397 ti,needs-special-reset;
398 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
403 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
404 reg = <0x481a0000 0x400>;
405 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
407 #address-cells = <1>;
413 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
414 reg = <0x481a2000 0x400>;
415 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
417 #address-cells = <1>;
423 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
424 reg = <0x481a4000 0x400>;
425 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
427 #address-cells = <1>;
433 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
434 reg = <0x48345000 0x400>;
435 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
437 #address-cells = <1>;
442 mac: ethernet@4a100000 {
443 compatible = "ti,am4372-cpsw","ti,cpsw";
444 reg = <0x4a100000 0x800
446 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH
447 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH
448 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
449 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
450 #address-cells = <1>;
452 ti,hwmods = "cpgmac0";
454 cpdma_channels = <8>;
455 ale_entries = <1024>;
456 bd_ram_size = <0x2000>;
459 mac_control = <0x20>;
462 cpts_clock_mult = <0x80000000>;
463 cpts_clock_shift = <29>;
466 davinci_mdio: mdio@4a101000 {
467 compatible = "ti,am4372-mdio","ti,davinci_mdio";
468 reg = <0x4a101000 0x100>;
469 #address-cells = <1>;
471 ti,hwmods = "davinci_mdio";
472 bus_freq = <1000000>;
476 cpsw_emac0: slave@4a100200 {
477 /* Filled in by U-Boot */
478 mac-address = [ 00 00 00 00 00 00 ];
481 cpsw_emac1: slave@4a100300 {
482 /* Filled in by U-Boot */
483 mac-address = [ 00 00 00 00 00 00 ];
487 epwmss0: epwmss@48300000 {
488 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
489 reg = <0x48300000 0x10>;
490 #address-cells = <1>;
493 ti,hwmods = "epwmss0";
496 ecap0: ecap@48300100 {
497 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
498 reg = <0x48300100 0x80>;
503 ehrpwm0: ehrpwm@48300200 {
504 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
505 reg = <0x48300200 0x80>;
506 ti,hwmods = "ehrpwm0";
511 epwmss1: epwmss@48302000 {
512 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
513 reg = <0x48302000 0x10>;
514 #address-cells = <1>;
517 ti,hwmods = "epwmss1";
520 ecap1: ecap@48302100 {
521 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
522 reg = <0x48302100 0x80>;
527 ehrpwm1: ehrpwm@48302200 {
528 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
529 reg = <0x48302200 0x80>;
530 ti,hwmods = "ehrpwm1";
535 epwmss2: epwmss@48304000 {
536 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
537 reg = <0x48304000 0x10>;
538 #address-cells = <1>;
541 ti,hwmods = "epwmss2";
544 ecap2: ecap@48304100 {
545 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
546 reg = <0x48304100 0x80>;
551 ehrpwm2: ehrpwm@48304200 {
552 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
553 reg = <0x48304200 0x80>;
554 ti,hwmods = "ehrpwm2";
559 epwmss3: epwmss@48306000 {
560 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
561 reg = <0x48306000 0x10>;
562 #address-cells = <1>;
565 ti,hwmods = "epwmss3";
568 ehrpwm3: ehrpwm@48306200 {
569 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
570 reg = <0x48306200 0x80>;
571 ti,hwmods = "ehrpwm3";
576 epwmss4: epwmss@48308000 {
577 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
578 reg = <0x48308000 0x10>;
579 #address-cells = <1>;
582 ti,hwmods = "epwmss4";
585 ehrpwm4: ehrpwm@48308200 {
586 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
587 reg = <0x48308200 0x80>;
588 ti,hwmods = "ehrpwm4";
593 epwmss5: epwmss@4830a000 {
594 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
595 reg = <0x4830a000 0x10>;
596 #address-cells = <1>;
599 ti,hwmods = "epwmss5";
602 ehrpwm5: ehrpwm@4830a200 {
603 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
604 reg = <0x4830a200 0x80>;
605 ti,hwmods = "ehrpwm5";
610 sham: sham@53100000 {
611 compatible = "ti,omap5-sham";
613 reg = <0x53100000 0x300>;
616 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
620 compatible = "ti,omap4-aes";
622 reg = <0x53501000 0xa0>;
623 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
626 dma-names = "tx", "rx";
630 compatible = "ti,omap4-des";
632 reg = <0x53701000 0xa0>;
633 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
636 dma-names = "tx", "rx";
639 mcasp0: mcasp@48038000 {
640 compatible = "ti,am33xx-mcasp-audio";
641 ti,hwmods = "mcasp0";
642 reg = <0x48038000 0x2000>,
643 <0x46000000 0x400000>;
644 reg-names = "mpu", "dat";
645 interrupts = <80>, <81>;
646 interrupts-names = "tx", "rx";
650 dma-names = "tx", "rx";
653 mcasp1: mcasp@4803C000 {
654 compatible = "ti,am33xx-mcasp-audio";
655 ti,hwmods = "mcasp1";
656 reg = <0x4803C000 0x2000>,
657 <0x46400000 0x400000>;
658 reg-names = "mpu", "dat";
659 interrupts = <82>, <83>;
660 interrupts-names = "tx", "rx";
664 dma-names = "tx", "rx";