2 * Device Tree Source for AM4372 SoC
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include "skeleton.dtsi"
16 compatible = "ti,am4372", "ti,am43";
17 interrupt-parent = <&gic>;
25 ethernet0 = &cpsw_emac0;
26 ethernet1 = &cpsw_emac1;
33 compatible = "arm,cortex-a9";
39 gic: interrupt-controller@48241000 {
40 compatible = "arm,cortex-a9-gic";
42 #interrupt-cells = <3>;
43 reg = <0x48241000 0x1000>,
47 l2-cache-controller@48242000 {
48 compatible = "arm,pl310-cache";
49 reg = <0x48242000 0x1000>;
54 am43xx_pinmux: pinmux@44e10800 {
55 compatible = "pinctrl-single";
56 reg = <0x44e10800 0x31c>;
59 pinctrl-single,register-width = <32>;
60 pinctrl-single,function-mask = <0xffffffff>;
64 compatible = "simple-bus";
68 ti,hwmods = "l3_main";
71 compatible = "ti,am4-prcm";
72 reg = <0x44df0000 0x11000>;
79 prcm_clockdomains: clockdomains {
84 compatible = "ti,am4-scrm";
85 reg = <0x44e10000 0x2000>;
92 scrm_clockdomains: clockdomains {
97 compatible = "ti,edma3";
98 ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
99 reg = <0x49000000 0x10000>,
101 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
102 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
103 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
106 ti,edma-regions = <4>;
107 ti,edma-slots = <256>;
110 uart0: serial@44e09000 {
111 compatible = "ti,am4372-uart","ti,omap2-uart";
112 reg = <0x44e09000 0x2000>;
113 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
117 uart1: serial@48022000 {
118 compatible = "ti,am4372-uart","ti,omap2-uart";
119 reg = <0x48022000 0x2000>;
120 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
125 uart2: serial@48024000 {
126 compatible = "ti,am4372-uart","ti,omap2-uart";
127 reg = <0x48024000 0x2000>;
128 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
133 uart3: serial@481a6000 {
134 compatible = "ti,am4372-uart","ti,omap2-uart";
135 reg = <0x481a6000 0x2000>;
136 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
141 uart4: serial@481a8000 {
142 compatible = "ti,am4372-uart","ti,omap2-uart";
143 reg = <0x481a8000 0x2000>;
144 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
149 uart5: serial@481aa000 {
150 compatible = "ti,am4372-uart","ti,omap2-uart";
151 reg = <0x481aa000 0x2000>;
152 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
157 mailbox: mailbox@480C8000 {
158 compatible = "ti,omap4-mailbox";
159 reg = <0x480C8000 0x200>;
160 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
161 ti,hwmods = "mailbox";
162 ti,mbox-num-users = <4>;
163 ti,mbox-num-fifos = <8>;
164 ti,mbox-names = "wkup_m3";
165 ti,mbox-data = <0 0 0 0>;
169 timer1: timer@44e31000 {
170 compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
171 reg = <0x44e31000 0x400>;
172 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
174 ti,hwmods = "timer1";
177 timer2: timer@48040000 {
178 compatible = "ti,am4372-timer","ti,am335x-timer";
179 reg = <0x48040000 0x400>;
180 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
181 ti,hwmods = "timer2";
184 timer3: timer@48042000 {
185 compatible = "ti,am4372-timer","ti,am335x-timer";
186 reg = <0x48042000 0x400>;
187 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
188 ti,hwmods = "timer3";
192 timer4: timer@48044000 {
193 compatible = "ti,am4372-timer","ti,am335x-timer";
194 reg = <0x48044000 0x400>;
195 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
197 ti,hwmods = "timer4";
201 timer5: timer@48046000 {
202 compatible = "ti,am4372-timer","ti,am335x-timer";
203 reg = <0x48046000 0x400>;
204 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
206 ti,hwmods = "timer5";
210 timer6: timer@48048000 {
211 compatible = "ti,am4372-timer","ti,am335x-timer";
212 reg = <0x48048000 0x400>;
213 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
215 ti,hwmods = "timer6";
219 timer7: timer@4804a000 {
220 compatible = "ti,am4372-timer","ti,am335x-timer";
221 reg = <0x4804a000 0x400>;
222 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
224 ti,hwmods = "timer7";
228 timer8: timer@481c1000 {
229 compatible = "ti,am4372-timer","ti,am335x-timer";
230 reg = <0x481c1000 0x400>;
231 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
232 ti,hwmods = "timer8";
236 timer9: timer@4833d000 {
237 compatible = "ti,am4372-timer","ti,am335x-timer";
238 reg = <0x4833d000 0x400>;
239 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
240 ti,hwmods = "timer9";
244 timer10: timer@4833f000 {
245 compatible = "ti,am4372-timer","ti,am335x-timer";
246 reg = <0x4833f000 0x400>;
247 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
248 ti,hwmods = "timer10";
252 timer11: timer@48341000 {
253 compatible = "ti,am4372-timer","ti,am335x-timer";
254 reg = <0x48341000 0x400>;
255 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
256 ti,hwmods = "timer11";
260 counter32k: counter@44e86000 {
261 compatible = "ti,am4372-counter32k","ti,omap-counter32k";
262 reg = <0x44e86000 0x40>;
263 ti,hwmods = "counter_32k";
267 compatible = "ti,am4372-rtc","ti,da830-rtc";
268 reg = <0x44e3e000 0x1000>;
269 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
270 GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
276 compatible = "ti,am4372-wdt","ti,omap3-wdt";
277 reg = <0x44e35000 0x1000>;
278 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
279 ti,hwmods = "wd_timer2";
282 gpio0: gpio@44e07000 {
283 compatible = "ti,am4372-gpio","ti,omap4-gpio";
284 reg = <0x44e07000 0x1000>;
285 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
288 interrupt-controller;
289 #interrupt-cells = <2>;
294 gpio1: gpio@4804c000 {
295 compatible = "ti,am4372-gpio","ti,omap4-gpio";
296 reg = <0x4804c000 0x1000>;
297 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
300 interrupt-controller;
301 #interrupt-cells = <2>;
306 gpio2: gpio@481ac000 {
307 compatible = "ti,am4372-gpio","ti,omap4-gpio";
308 reg = <0x481ac000 0x1000>;
309 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
312 interrupt-controller;
313 #interrupt-cells = <2>;
318 gpio3: gpio@481ae000 {
319 compatible = "ti,am4372-gpio","ti,omap4-gpio";
320 reg = <0x481ae000 0x1000>;
321 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
324 interrupt-controller;
325 #interrupt-cells = <2>;
330 gpio4: gpio@48320000 {
331 compatible = "ti,am4372-gpio","ti,omap4-gpio";
332 reg = <0x48320000 0x1000>;
333 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
336 interrupt-controller;
337 #interrupt-cells = <2>;
342 gpio5: gpio@48322000 {
343 compatible = "ti,am4372-gpio","ti,omap4-gpio";
344 reg = <0x48322000 0x1000>;
345 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
348 interrupt-controller;
349 #interrupt-cells = <2>;
355 compatible = "ti,am4372-i2c","ti,omap4-i2c";
356 reg = <0x44e0b000 0x1000>;
357 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
359 #address-cells = <1>;
365 compatible = "ti,am4372-i2c","ti,omap4-i2c";
366 reg = <0x4802a000 0x1000>;
367 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
369 #address-cells = <1>;
375 compatible = "ti,am4372-i2c","ti,omap4-i2c";
376 reg = <0x4819c000 0x1000>;
377 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
379 #address-cells = <1>;
385 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
386 reg = <0x48030000 0x400>;
387 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
389 #address-cells = <1>;
395 compatible = "ti,omap4-hsmmc";
396 reg = <0x48060000 0x1000>;
399 ti,needs-special-reset;
402 dma-names = "tx", "rx";
403 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
408 compatible = "ti,omap4-hsmmc";
409 reg = <0x481d8000 0x1000>;
411 ti,needs-special-reset;
414 dma-names = "tx", "rx";
415 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
420 compatible = "ti,omap4-hsmmc";
421 reg = <0x47810000 0x1000>;
423 ti,needs-special-reset;
424 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
429 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
430 reg = <0x481a0000 0x400>;
431 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
433 #address-cells = <1>;
439 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
440 reg = <0x481a2000 0x400>;
441 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
443 #address-cells = <1>;
449 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
450 reg = <0x481a4000 0x400>;
451 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
453 #address-cells = <1>;
459 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
460 reg = <0x48345000 0x400>;
461 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
463 #address-cells = <1>;
468 mac: ethernet@4a100000 {
469 compatible = "ti,am4372-cpsw","ti,cpsw";
470 reg = <0x4a100000 0x800
472 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH
473 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH
474 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
475 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
476 #address-cells = <1>;
478 ti,hwmods = "cpgmac0";
480 cpdma_channels = <8>;
481 ale_entries = <1024>;
482 bd_ram_size = <0x2000>;
485 mac_control = <0x20>;
488 cpts_clock_mult = <0x80000000>;
489 cpts_clock_shift = <29>;
492 davinci_mdio: mdio@4a101000 {
493 compatible = "ti,am4372-mdio","ti,davinci_mdio";
494 reg = <0x4a101000 0x100>;
495 #address-cells = <1>;
497 ti,hwmods = "davinci_mdio";
498 bus_freq = <1000000>;
502 cpsw_emac0: slave@4a100200 {
503 /* Filled in by U-Boot */
504 mac-address = [ 00 00 00 00 00 00 ];
507 cpsw_emac1: slave@4a100300 {
508 /* Filled in by U-Boot */
509 mac-address = [ 00 00 00 00 00 00 ];
513 epwmss0: epwmss@48300000 {
514 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
515 reg = <0x48300000 0x10>;
516 #address-cells = <1>;
519 ti,hwmods = "epwmss0";
522 ecap0: ecap@48300100 {
523 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
524 reg = <0x48300100 0x80>;
529 ehrpwm0: ehrpwm@48300200 {
530 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
531 reg = <0x48300200 0x80>;
532 ti,hwmods = "ehrpwm0";
537 epwmss1: epwmss@48302000 {
538 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
539 reg = <0x48302000 0x10>;
540 #address-cells = <1>;
543 ti,hwmods = "epwmss1";
546 ecap1: ecap@48302100 {
547 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
548 reg = <0x48302100 0x80>;
553 ehrpwm1: ehrpwm@48302200 {
554 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
555 reg = <0x48302200 0x80>;
556 ti,hwmods = "ehrpwm1";
561 epwmss2: epwmss@48304000 {
562 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
563 reg = <0x48304000 0x10>;
564 #address-cells = <1>;
567 ti,hwmods = "epwmss2";
570 ecap2: ecap@48304100 {
571 compatible = "ti,am4372-ecap","ti,am33xx-ecap";
572 reg = <0x48304100 0x80>;
577 ehrpwm2: ehrpwm@48304200 {
578 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
579 reg = <0x48304200 0x80>;
580 ti,hwmods = "ehrpwm2";
585 epwmss3: epwmss@48306000 {
586 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
587 reg = <0x48306000 0x10>;
588 #address-cells = <1>;
591 ti,hwmods = "epwmss3";
594 ehrpwm3: ehrpwm@48306200 {
595 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
596 reg = <0x48306200 0x80>;
597 ti,hwmods = "ehrpwm3";
602 epwmss4: epwmss@48308000 {
603 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
604 reg = <0x48308000 0x10>;
605 #address-cells = <1>;
608 ti,hwmods = "epwmss4";
611 ehrpwm4: ehrpwm@48308200 {
612 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
613 reg = <0x48308200 0x80>;
614 ti,hwmods = "ehrpwm4";
619 epwmss5: epwmss@4830a000 {
620 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
621 reg = <0x4830a000 0x10>;
622 #address-cells = <1>;
625 ti,hwmods = "epwmss5";
628 ehrpwm5: ehrpwm@4830a200 {
629 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
630 reg = <0x4830a200 0x80>;
631 ti,hwmods = "ehrpwm5";
636 sham: sham@53100000 {
637 compatible = "ti,omap5-sham";
639 reg = <0x53100000 0x300>;
642 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
646 compatible = "ti,omap4-aes";
648 reg = <0x53501000 0xa0>;
649 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
652 dma-names = "tx", "rx";
656 compatible = "ti,omap4-des";
658 reg = <0x53701000 0xa0>;
659 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
662 dma-names = "tx", "rx";
665 mcasp0: mcasp@48038000 {
666 compatible = "ti,am33xx-mcasp-audio";
667 ti,hwmods = "mcasp0";
668 reg = <0x48038000 0x2000>,
669 <0x46000000 0x400000>;
670 reg-names = "mpu", "dat";
671 interrupts = <80>, <81>;
672 interrupts-names = "tx", "rx";
676 dma-names = "tx", "rx";
679 mcasp1: mcasp@4803C000 {
680 compatible = "ti,am33xx-mcasp-audio";
681 ti,hwmods = "mcasp1";
682 reg = <0x4803C000 0x2000>,
683 <0x46400000 0x400000>;
684 reg-names = "mpu", "dat";
685 interrupts = <82>, <83>;
686 interrupts-names = "tx", "rx";
690 dma-names = "tx", "rx";
695 /include/ "am43xx-clocks.dtsi"