2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
13 #include "am4372.dtsi"
14 #include <dt-bindings/pinctrl/am43xx.h>
15 #include <dt-bindings/pwm/pwm.h>
16 #include <dt-bindings/gpio/gpio.h>
19 model = "TI AM437x GP EVM";
20 compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43";
30 evm_v3_3d: fixedregulator-v3_3d {
31 compatible = "regulator-fixed";
32 regulator-name = "evm_v3_3d";
33 regulator-min-microvolt = <3300000>;
34 regulator-max-microvolt = <3300000>;
38 vtt_fixed: fixedregulator-vtt {
39 compatible = "regulator-fixed";
40 regulator-name = "vtt_fixed";
41 regulator-min-microvolt = <1500000>;
42 regulator-max-microvolt = <1500000>;
46 gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
49 vmmcwl_fixed: fixedregulator-mmcwl {
50 compatible = "regulator-fixed";
51 regulator-name = "vmmcwl_fixed";
52 regulator-min-microvolt = <1800000>;
53 regulator-max-microvolt = <1800000>;
54 gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>;
59 compatible = "pwm-backlight";
60 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
61 brightness-levels = <0 51 53 56 62 75 101 152 255>;
62 default-brightness-level = <8>;
65 matrix_keypad: matrix_keypad0 {
66 compatible = "gpio-matrix-keypad";
67 debounce-delay-ms = <5>;
68 col-scan-delay-us = <2>;
70 row-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH /* Bank3, pin21 */
71 &gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */
72 &gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */
74 col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */
75 &gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */
77 linux,keymap = <0x00000201 /* P1 */
80 0x0101006a /* RIGHT */
82 0x0201006c>; /* DOWN */
86 compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
90 clock-frequency = <33000000>;
102 pixelclk-active = <1>;
107 remote-endpoint = <&dpi_out>;
112 /* fixed 12MHz oscillator */
115 compatible = "fixed-clock";
116 clock-frequency = <12000000>;
119 /* fixed 32k external oscillator clock */
120 clk_32k_rtc: clk_32k_rtc {
122 compatible = "fixed-clock";
123 clock-frequency = <32768>;
127 compatible = "simple-audio-card";
128 simple-audio-card,name = "AM437x-GP-EVM";
129 simple-audio-card,widgets =
130 "Headphone", "Headphone Jack",
132 simple-audio-card,routing =
133 "Headphone Jack", "HPLOUT",
134 "Headphone Jack", "HPROUT",
137 simple-audio-card,format = "dsp_b";
138 simple-audio-card,bitclock-master = <&sound0_master>;
139 simple-audio-card,frame-master = <&sound0_master>;
140 simple-audio-card,bitclock-inversion;
142 simple-audio-card,cpu {
143 sound-dai = <&mcasp1>;
144 system-clock-frequency = <12000000>;
147 sound0_master: simple-audio-card,codec {
148 sound-dai = <&tlv320aic3106>;
149 system-clock-frequency = <12000000>;
155 pinctrl-names = "default", "sleep";
156 pinctrl-0 = <&wlan_pins_default>;
157 pinctrl-1 = <&wlan_pins_sleep>;
159 i2c0_pins: i2c0_pins {
160 pinctrl-single,pins = <
161 AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
162 AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
166 i2c1_pins: i2c1_pins {
167 pinctrl-single,pins = <
168 AM4372_IOPAD(0x95c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
169 AM4372_IOPAD(0x958, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
173 mmc1_pins: pinmux_mmc1_pins {
174 pinctrl-single,pins = <
175 AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
179 ecap0_pins: backlight_pins {
180 pinctrl-single,pins = <
181 AM4372_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
185 pixcir_ts_pins: pixcir_ts_pins {
186 pinctrl-single,pins = <
187 AM4372_IOPAD(0xa64, PIN_INPUT_PULLUP | MUX_MODE7) /* spi2_d0.gpio3_22 */
191 cpsw_default: cpsw_default {
192 pinctrl-single,pins = <
194 AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */
195 AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */
196 AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */
197 AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */
198 AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */
199 AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */
200 AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
201 AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
202 AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */
203 AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */
204 AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */
205 AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */
209 cpsw_sleep: cpsw_sleep {
210 pinctrl-single,pins = <
211 /* Slave 1 reset value */
212 AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
213 AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
214 AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
215 AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
216 AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
217 AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
218 AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
219 AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
220 AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
221 AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
222 AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
223 AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
227 davinci_mdio_default: davinci_mdio_default {
228 pinctrl-single,pins = <
230 AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
231 AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
235 davinci_mdio_sleep: davinci_mdio_sleep {
236 pinctrl-single,pins = <
237 /* MDIO reset value */
238 AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
239 AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
243 nand_flash_x8: nand_flash_x8 {
244 pinctrl-single,pins = <
245 AM4372_IOPAD(0x800, PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
246 AM4372_IOPAD(0x804, PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
247 AM4372_IOPAD(0x808, PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
248 AM4372_IOPAD(0x80c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
249 AM4372_IOPAD(0x810, PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
250 AM4372_IOPAD(0x814, PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
251 AM4372_IOPAD(0x818, PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
252 AM4372_IOPAD(0x81c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
253 AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
254 AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
255 AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
256 AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
257 AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
258 AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
259 AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
264 pinctrl-single,pins = <
265 AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
266 AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1)
267 AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1)
268 AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1)
269 AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1)
270 AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1)
271 AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1)
272 AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
273 AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
274 AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0)
275 AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0)
276 AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0)
277 AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0)
278 AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0)
279 AM4372_IOPAD(0x8b8, PIN_OUTPUT_PULLUP | MUX_MODE0)
280 AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0)
281 AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0)
282 AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0)
283 AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0)
284 AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0)
285 AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0)
286 AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0)
287 AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0)
288 AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
289 AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
290 AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
291 AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
292 AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
297 display_mux_pins: display_mux_pins {
298 pinctrl-single,pins = <
299 /* GPIO 5_8 to select LCD / HDMI */
300 AM4372_IOPAD(0xa38, PIN_OUTPUT_PULLUP | MUX_MODE7)
304 dcan0_default: dcan0_default_pins {
305 pinctrl-single,pins = <
306 AM4372_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */
307 AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.d_can0_rx */
311 dcan0_sleep: dcan0_sleep_pins {
312 pinctrl-single,pins = <
313 AM4372_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_ctsn.gpio0_12 */
314 AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_rtsn.gpio0_13 */
318 dcan1_default: dcan1_default_pins {
319 pinctrl-single,pins = <
320 AM4372_IOPAD(0x980, PIN_OUTPUT | MUX_MODE2) /* uart1_rxd.d_can1_tx */
321 AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */
325 dcan1_sleep: dcan1_sleep_pins {
326 pinctrl-single,pins = <
327 AM4372_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_rxd.gpio0_14 */
328 AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_txd.gpio0_15 */
332 vpfe0_pins_default: vpfe0_pins_default {
333 pinctrl-single,pins = <
334 AM4372_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/
335 AM4372_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/
336 AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/
337 AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/
338 AM4372_IOPAD(0x9c8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/
339 AM4372_IOPAD(0xa08, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/
340 AM4372_IOPAD(0xa0c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/
341 AM4372_IOPAD(0xa10, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/
342 AM4372_IOPAD(0xa14, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/
343 AM4372_IOPAD(0xa18, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/
344 AM4372_IOPAD(0xa1c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/
345 AM4372_IOPAD(0xa20, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/
346 AM4372_IOPAD(0xa24, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/
350 vpfe0_pins_sleep: vpfe0_pins_sleep {
351 pinctrl-single,pins = <
352 AM4372_IOPAD(0x9b0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_hd mode 0*/
353 AM4372_IOPAD(0x9b4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_vd mode 0*/
354 AM4372_IOPAD(0x9c0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_pclk mode 0*/
355 AM4372_IOPAD(0x9c4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data8 mode 0*/
356 AM4372_IOPAD(0x9c8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data9 mode 0*/
357 AM4372_IOPAD(0xa08, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data0 mode 0*/
358 AM4372_IOPAD(0xa0c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data1 mode 0*/
359 AM4372_IOPAD(0xa10, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data2 mode 0*/
360 AM4372_IOPAD(0xa14, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data3 mode 0*/
361 AM4372_IOPAD(0xa18, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data4 mode 0*/
362 AM4372_IOPAD(0xa1c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data5 mode 0*/
363 AM4372_IOPAD(0xa20, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data6 mode 0*/
364 AM4372_IOPAD(0xa24, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data7 mode 0*/
368 vpfe1_pins_default: vpfe1_pins_default {
369 pinctrl-single,pins = <
370 AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0*/
371 AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0*/
372 AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0*/
373 AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0*/
374 AM4372_IOPAD(0x9dC, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0*/
375 AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0*/
376 AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0*/
377 AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0*/
378 AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0*/
379 AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0*/
380 AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0*/
381 AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0*/
382 AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0*/
386 vpfe1_pins_sleep: vpfe1_pins_sleep {
387 pinctrl-single,pins = <
388 AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data9 mode 0*/
389 AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data8 mode 0*/
390 AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_hd mode 0*/
391 AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_vd mode 0*/
392 AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_pclk mode 0*/
393 AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data0 mode 0*/
394 AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data1 mode 0*/
395 AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data2 mode 0*/
396 AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data3 mode 0*/
397 AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data4 mode 0*/
398 AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data5 mode 0*/
399 AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data6 mode 0*/
400 AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data7 mode 0*/
404 mmc3_pins_default: pinmux_mmc3_pins_default {
405 pinctrl-single,pins = <
406 AM4372_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk */
407 AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */
408 AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0 */
409 AM4372_IOPAD(0x848, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1 */
410 AM4372_IOPAD(0x84c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2 */
411 AM4372_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be1n.mmc2_dat3 */
415 mmc3_pins_sleep: pinmux_mmc3_pins_sleep {
416 pinctrl-single,pins = <
417 AM4372_IOPAD(0x88c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_clk.mmc2_clk */
418 AM4372_IOPAD(0x888, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.mmc2_cmd */
419 AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a1.mmc2_dat0 */
420 AM4372_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a2.mmc2_dat1 */
421 AM4372_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a3.mmc2_dat2 */
422 AM4372_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_be1n.mmc2_dat3 */
426 wlan_pins_default: pinmux_wlan_pins_default {
427 pinctrl-single,pins = <
428 AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */
429 AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/
430 AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/
434 wlan_pins_sleep: pinmux_wlan_pins_sleep {
435 pinctrl-single,pins = <
436 AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */
437 AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/
438 AM4372_IOPAD(0x840, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/
442 uart3_pins: uart3_pins {
443 pinctrl-single,pins = <
444 AM4372_IOPAD(0xa28, PIN_INPUT | MUX_MODE0) /* uart3_rxd.uart3_rxd */
445 AM4372_IOPAD(0xa2c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */
446 AM4372_IOPAD(0xa30, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_ctsn.uart3_ctsn */
447 AM4372_IOPAD(0xa34, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */
451 mcasp1_pins: mcasp1_pins {
452 pinctrl-single,pins = <
453 AM4372_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
454 AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
455 AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
456 AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
460 mcasp1_sleep_pins: mcasp1_sleep_pins {
461 pinctrl-single,pins = <
462 AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7)
463 AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
464 AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
465 AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
469 gpio0_pins: gpio0_pins {
470 pinctrl-single,pins = <
471 AM4372_IOPAD(0xa6c, PIN_OUTPUT | MUX_MODE9) /* spi2_cs0.gpio0_23 SEL_eMMCorNANDn */
475 emmc_pins_default: emmc_pins_default {
476 pinctrl-single,pins = <
477 AM4372_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
478 AM4372_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
479 AM4372_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
480 AM4372_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
481 AM4372_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
482 AM4372_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
483 AM4372_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
484 AM4372_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
485 AM4372_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
486 AM4372_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
490 emmc_pins_sleep: emmc_pins_sleep {
491 pinctrl-single,pins = <
492 AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad0.gpio1_0 */
493 AM4372_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad1.gpio1_1 */
494 AM4372_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad2.gpio1_2 */
495 AM4372_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad3.gpio1_3 */
496 AM4372_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */
497 AM4372_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */
498 AM4372_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */
499 AM4372_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */
500 AM4372_IOPAD(0x880, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn1.gpio1_30 */
501 AM4372_IOPAD(0x884, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn2.gpio1_31 */
508 pinctrl-names = "default";
509 pinctrl-0 = <&i2c0_pins>;
510 clock-frequency = <100000>;
512 tps65218: tps65218@24 {
514 compatible = "ti,tps65218";
515 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
516 interrupt-controller;
517 #interrupt-cells = <2>;
519 dcdc1: regulator-dcdc1 {
520 regulator-name = "vdd_core";
521 regulator-min-microvolt = <912000>;
522 regulator-max-microvolt = <1144000>;
527 dcdc2: regulator-dcdc2 {
528 regulator-name = "vdd_mpu";
529 regulator-min-microvolt = <912000>;
530 regulator-max-microvolt = <1378000>;
535 dcdc3: regulator-dcdc3 {
536 regulator-name = "vdcdc3";
537 regulator-min-microvolt = <1500000>;
538 regulator-max-microvolt = <1500000>;
541 regulator-state-mem {
542 regulator-on-in-suspend;
544 regulator-state-disk {
545 regulator-off-in-suspend;
549 dcdc5: regulator-dcdc5 {
550 regulator-name = "v1_0bat";
551 regulator-min-microvolt = <1000000>;
552 regulator-max-microvolt = <1000000>;
555 regulator-state-mem {
556 regulator-on-in-suspend;
560 dcdc6: regulator-dcdc6 {
561 regulator-name = "v1_8bat";
562 regulator-min-microvolt = <1800000>;
563 regulator-max-microvolt = <1800000>;
566 regulator-state-mem {
567 regulator-on-in-suspend;
571 ldo1: regulator-ldo1 {
572 regulator-min-microvolt = <1800000>;
573 regulator-max-microvolt = <1800000>;
580 compatible = "ovti,ov2659";
583 clocks = <&refclk 0>;
584 clock-names = "xvclk";
588 remote-endpoint = <&vpfe1_ep>;
589 link-frequencies = /bits/ 64 <70000000>;
597 pinctrl-names = "default";
598 pinctrl-0 = <&i2c1_pins>;
600 compatible = "pixcir,pixcir_tangoc";
601 pinctrl-names = "default";
602 pinctrl-0 = <&pixcir_ts_pins>;
605 attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
608 * 0x264 represents the offset of padconf register of
609 * gpio3_22 from am43xx_pinmux base.
611 interrupts-extended = <&gpio3 22 IRQ_TYPE_EDGE_FALLING>,
612 <&am43xx_pinmux 0x264>;
613 interrupt-names = "tsc", "wakeup";
615 touchscreen-size-x = <1024>;
616 touchscreen-size-y = <600>;
621 compatible = "ovti,ov2659";
624 clocks = <&refclk 0>;
625 clock-names = "xvclk";
629 remote-endpoint = <&vpfe0_ep>;
630 link-frequencies = /bits/ 64 <70000000>;
635 tlv320aic3106: tlv320aic3106@1b {
636 #sound-dai-cells = <0>;
637 compatible = "ti,tlv320aic3106";
642 IOVDD-supply = <&evm_v3_3d>; /* V3_3D -> <tps63031> EN: V1_8D -> VBAT */
643 AVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */
644 DRVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */
645 DVDD-supply = <&ldo1>; /* V1_8D -> LDO1 */
657 ti,adc-channels = <0 1 2 3 4 5 6 7>;
663 pinctrl-names = "default";
664 pinctrl-0 = <&ecap0_pins>;
668 pinctrl-names = "default";
669 pinctrl-0 = <&gpio0_pins>;
674 gpios = <23 GPIO_ACTIVE_HIGH>;
675 /* SelEMMCorNAND selects between eMMC and NAND:
678 * When changing this line make sure the newly
679 * selected device node is enabled and the previously
680 * selected device node is disabled.
683 line-name = "SelEMMCorNAND";
700 pinctrl-names = "default";
701 pinctrl-0 = <&display_mux_pins>;
707 * SelLCDorHDMI selects between display and audio paths:
708 * Low: HDMI display with audio via HDMI
709 * High: LCD display with analog audio via aic3111 codec
712 gpios = <8 GPIO_ACTIVE_HIGH>;
714 line-name = "SelLCDorHDMI";
720 vmmc-supply = <&evm_v3_3d>;
722 pinctrl-names = "default";
723 pinctrl-0 = <&mmc1_pins>;
724 cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
727 /* eMMC sits on mmc2 */
730 * When enabling eMMC, disable GPMC/NAND and set
731 * SelEMMCorNAND to output-high
734 vmmc-supply = <&evm_v3_3d>;
736 pinctrl-names = "default", "sleep";
737 pinctrl-0 = <&emmc_pins_default>;
738 pinctrl-1 = <&emmc_pins_sleep>;
744 /* these are on the crossbar and are outlined in the
745 xbar-event-map element */
746 dmas = <&edma_xbar 30 0 1>,
748 dma-names = "tx", "rx";
749 vmmc-supply = <&vmmcwl_fixed>;
751 pinctrl-names = "default", "sleep";
752 pinctrl-0 = <&mmc3_pins_default>;
753 pinctrl-1 = <&mmc3_pins_sleep>;
755 keep-power-in-suspend;
758 #address-cells = <1>;
761 compatible = "ti,wl1835";
763 interrupt-parent = <&gpio1>;
764 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
770 pinctrl-names = "default";
771 pinctrl-0 = <&uart3_pins>;
779 dr_mode = "peripheral";
794 pinctrl-names = "default", "sleep";
795 pinctrl-0 = <&cpsw_default>;
796 pinctrl-1 = <&cpsw_sleep>;
801 pinctrl-names = "default", "sleep";
802 pinctrl-0 = <&davinci_mdio_default>;
803 pinctrl-1 = <&davinci_mdio_sleep>;
808 phy_id = <&davinci_mdio>, <0>;
818 * When enabling GPMC, disable eMMC and set
819 * SelEMMCorNAND to output-low
822 pinctrl-names = "default";
823 pinctrl-0 = <&nand_flash_x8>;
824 ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */
826 compatible = "ti,omap2-nand";
827 reg = <0 0 4>; /* device IO registers */
828 interrupt-parent = <&gpmc>;
829 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
830 <1 IRQ_TYPE_NONE>; /* termcount */
831 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
832 ti,nand-ecc-opt = "bch16";
834 nand-bus-width = <8>;
835 gpmc,device-width = <1>;
836 gpmc,sync-clk-ps = <0>;
838 gpmc,cs-rd-off-ns = <40>;
839 gpmc,cs-wr-off-ns = <40>;
840 gpmc,adv-on-ns = <0>;
841 gpmc,adv-rd-off-ns = <25>;
842 gpmc,adv-wr-off-ns = <25>;
844 gpmc,we-off-ns = <20>;
846 gpmc,oe-off-ns = <30>;
847 gpmc,access-ns = <30>;
848 gpmc,rd-cycle-ns = <40>;
849 gpmc,wr-cycle-ns = <40>;
850 gpmc,bus-turnaround-ns = <0>;
851 gpmc,cycle2cycle-delay-ns = <0>;
852 gpmc,clk-activation-ns = <0>;
853 gpmc,wr-access-ns = <40>;
854 gpmc,wr-data-mux-bus-ns = <0>;
855 /* MTD partition table */
856 /* All SPL-* partitions are sized to minimal length
857 * which can be independently programmable. For
858 * NAND flash this is equal to size of erase-block */
859 #address-cells = <1>;
863 reg = <0x00000000 0x00040000>;
866 label = "NAND.SPL.backup1";
867 reg = <0x00040000 0x00040000>;
870 label = "NAND.SPL.backup2";
871 reg = <0x00080000 0x00040000>;
874 label = "NAND.SPL.backup3";
875 reg = <0x000c0000 0x00040000>;
878 label = "NAND.u-boot-spl-os";
879 reg = <0x00100000 0x00080000>;
882 label = "NAND.u-boot";
883 reg = <0x00180000 0x00100000>;
886 label = "NAND.u-boot-env";
887 reg = <0x00280000 0x00040000>;
890 label = "NAND.u-boot-env.backup1";
891 reg = <0x002c0000 0x00040000>;
894 label = "NAND.kernel";
895 reg = <0x00300000 0x00700000>;
898 label = "NAND.file-system";
899 reg = <0x00a00000 0x1f600000>;
907 pinctrl-names = "default";
908 pinctrl-0 = <&dss_pins>;
912 remote-endpoint = <&lcd_in>;
919 pinctrl-names = "default", "sleep";
920 pinctrl-0 = <&dcan0_default>;
921 pinctrl-1 = <&dcan0_sleep>;
926 pinctrl-names = "default", "sleep";
927 pinctrl-0 = <&dcan1_default>;
928 pinctrl-1 = <&dcan1_sleep>;
934 pinctrl-names = "default", "sleep";
935 pinctrl-0 = <&vpfe0_pins_default>;
936 pinctrl-1 = <&vpfe0_pins_sleep>;
940 remote-endpoint = <&ov2659_1>;
941 ti,am437x-vpfe-interface = <0>;
951 pinctrl-names = "default", "sleep";
952 pinctrl-0 = <&vpfe1_pins_default>;
953 pinctrl-1 = <&vpfe1_pins_sleep>;
957 remote-endpoint = <&ov2659_0>;
958 ti,am437x-vpfe-interface = <0>;
967 #sound-dai-cells = <0>;
968 pinctrl-names = "default", "sleep";
969 pinctrl-0 = <&mcasp1_pins>;
970 pinctrl-1 = <&mcasp1_sleep_pins>;
974 op-mode = <0>; /* MCASP_IIS_MODE */
977 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
985 clocks = <&clk_32k_rtc>, <&clk_32768_ck>;
986 clock-names = "ext-clk", "int-clk";
991 cpu0-supply = <&dcdc2>;