arch/arm/boot/dts/am43x-epos-evm.dts

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /* AM43x EPOS EVM */
  10
  11 /dts-v1/;
  12
  13 #include "am4372.dtsi"
  14 #include <dt-bindings/pinctrl/am43xx.h>
  15 #include <dt-bindings/gpio/gpio.h>
  16 #include <dt-bindings/pwm/pwm.h>
  17 #include <dt-bindings/sound/tlv320aic31xx-micbias.h>
  18
  19 / {
  20         model = "TI AM43x EPOS EVM";
  21         compatible = "ti,am43x-epos-evm","ti,am4372","ti,am43";
  22
  23         aliases {
  24                 display0 = &lcd0;
  25         };
  26
  27         vmmcsd_fixed: fixedregulator-sd {
  28                 compatible = "regulator-fixed";
  29                 regulator-name = "vmmcsd_fixed";
  30                 regulator-min-microvolt = <3300000>;
  31                 regulator-max-microvolt = <3300000>;
  32                 enable-active-high;
  33         };
  34
  35         vbat: fixedregulator@0 {
  36                 compatible = "regulator-fixed";
  37                 regulator-name = "vbat";
  38                 regulator-min-microvolt = <5000000>;
  39                 regulator-max-microvolt = <5000000>;
  40                 regulator-boot-on;
  41         };
  42
  43         lcd0: display {
  44                 compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
  45                 label = "lcd";
  46
  47                 panel-timing {
  48                         clock-frequency = <33000000>;
  49                         hactive = <800>;
  50                         vactive = <480>;
  51                         hfront-porch = <210>;
  52                         hback-porch = <16>;
  53                         hsync-len = <30>;
  54                         vback-porch = <10>;
  55                         vfront-porch = <22>;
  56                         vsync-len = <13>;
  57                         hsync-active = <0>;
  58                         vsync-active = <0>;
  59                         de-active = <1>;
  60                         pixelclk-active = <1>;
  61                 };
  62
  63                 port {
  64                         lcd_in: endpoint {
  65                                 remote-endpoint = <&dpi_out>;
  66                         };
  67                 };
  68         };
  69
  70         matrix_keypad: matrix_keypad@0 {
  71                 compatible = "gpio-matrix-keypad";
  72                 debounce-delay-ms = <5>;
  73                 col-scan-delay-us = <2>;
  74
  75                 row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH         /* Bank0, pin12 */
  76                              &gpio0 13 GPIO_ACTIVE_HIGH         /* Bank0, pin13 */
  77                              &gpio0 14 GPIO_ACTIVE_HIGH         /* Bank0, pin14 */
  78                              &gpio0 15 GPIO_ACTIVE_HIGH>;       /* Bank0, pin15 */
  79
  80                 col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH          /* Bank3, pin9 */
  81                              &gpio3 10 GPIO_ACTIVE_HIGH         /* Bank3, pin10 */
  82                              &gpio2 18 GPIO_ACTIVE_HIGH         /* Bank2, pin18 */
  83                              &gpio2 19 GPIO_ACTIVE_HIGH>;       /* Bank2, pin19 */
  84
  85                 linux,keymap = <0x00000201      /* P1 */
  86                         0x01000204      /* P4 */
  87                         0x02000207      /* P7 */
  88                         0x0300020a      /* NUMERIC_STAR */
  89                         0x00010202      /* P2 */
  90                         0x01010205      /* P5 */
  91                         0x02010208      /* P8 */
  92                         0x03010200      /* P0 */
  93                         0x00020203      /* P3 */
  94                         0x01020206      /* P6 */
  95                         0x02020209      /* P9 */
  96                         0x0302020b      /* NUMERIC_POUND */
  97                         0x00030067      /* UP */
  98                         0x0103006a      /* RIGHT */
  99                         0x0203006c      /* DOWN */
 100                         0x03030069>;    /* LEFT */
 101         };
 102
 103         backlight {
 104                 compatible = "pwm-backlight";
 105                 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
 106                 brightness-levels = <0 51 53 56 62 75 101 152 255>;
 107                 default-brightness-level = <8>;
 108         };
 109 };
 110
 111 &am43xx_pinmux {
 112                 cpsw_default: cpsw_default {
 113                         pinctrl-single,pins = <
 114                                 /* Slave 1 */
 115                                 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* mii1_crs.rmii1_crs */
 116                                 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* mii1_rxerr.rmii1_rxerr */
 117                                 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */
 118                                 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* mii1_rxdv.rmii1_rxdv */
 119                                 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
 120                                 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
 121                                 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* mii1_rxd1.rmii1_rxd1 */
 122                                 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* mii1_rxd0.rmii1_rxd0 */
 123                                 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0)  /* rmii1_refclk.rmii1_refclk */
 124                         >;
 125                 };
 126
 127                 cpsw_sleep: cpsw_sleep {
 128                         pinctrl-single,pins = <
 129                                 /* Slave 1 reset value */
 130                                 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
 131                                 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 132                                 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 133                                 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 134                                 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 135                                 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 136                                 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
 137                                 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 138                                 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 139                         >;
 140                 };
 141
 142                 davinci_mdio_default: davinci_mdio_default {
 143                         pinctrl-single,pins = <
 144                                 /* MDIO */
 145                                 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* mdio_data.mdio_data */
 146                                 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)                   /* mdio_clk.mdio_clk */
 147                         >;
 148                 };
 149
 150                 davinci_mdio_sleep: davinci_mdio_sleep {
 151                         pinctrl-single,pins = <
 152                                 /* MDIO reset value */
 153                                 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 154                                 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
 155                         >;
 156                 };
 157
 158                 i2c0_pins: pinmux_i2c0_pins {
 159                         pinctrl-single,pins = <
 160                                 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* i2c0_sda.i2c0_sda */
 161                                 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* i2c0_scl.i2c0_scl */
 162                         >;
 163                 };
 164
 165                 nand_flash_x8: nand_flash_x8 {
 166                         pinctrl-single,pins = <
 167                                 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_a0.SELQSPIorNAND/GPIO */
 168                                 0x0  (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad0.gpmc_ad0 */
 169                                 0x4  (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad1.gpmc_ad1 */
 170                                 0x8  (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad2.gpmc_ad2 */
 171                                 0xc  (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad3.gpmc_ad3 */
 172                                 0x10 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad4.gpmc_ad4 */
 173                                 0x14 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad5.gpmc_ad5 */
 174                                 0x18 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad6.gpmc_ad6 */
 175                                 0x1c (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad7.gpmc_ad7 */
 176                                 0x70 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_wait0.gpmc_wait0 */
 177                                 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7)    /* gpmc_wpn.gpmc_wpn */
 178                                 0x7c (PIN_OUTPUT | MUX_MODE0)           /* gpmc_csn0.gpmc_csn0  */
 179                                 0x90 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_advn_ale.gpmc_advn_ale */
 180                                 0x94 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_oen_ren.gpmc_oen_ren */
 181                                 0x98 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_wen.gpmc_wen */
 182                                 0x9c (PIN_OUTPUT | MUX_MODE0)           /* gpmc_be0n_cle.gpmc_be0n_cle */
 183                         >;
 184                 };
 185
 186                 ecap0_pins: backlight_pins {
 187                         pinctrl-single,pins = <
 188                                 0x164 MUX_MODE0         /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
 189                         >;
 190                 };
 191
 192                 i2c2_pins: pinmux_i2c2_pins {
 193                         pinctrl-single,pins = <
 194                                 0x1c0 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8)    /* i2c2_sda.i2c2_sda */
 195                                 0x1c4 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8)    /* i2c2_scl.i2c2_scl */
 196                         >;
 197                 };
 198
 199                 spi0_pins: pinmux_spi0_pins {
 200                         pinctrl-single,pins = <
 201                                 0x150 (PIN_INPUT | MUX_MODE0)           /* spi0_clk.spi0_clk */
 202                                 0x154 (PIN_OUTPUT | MUX_MODE0)           /* spi0_d0.spi0_d0 */
 203                                 0x158 (PIN_INPUT | MUX_MODE0)           /* spi0_d1.spi0_d1 */
 204                                 0x15c (PIN_OUTPUT | MUX_MODE0)          /* spi0_cs0.spi0_cs0 */
 205                         >;
 206                 };
 207
 208                 spi1_pins: pinmux_spi1_pins {
 209                         pinctrl-single,pins = <
 210                                 0x190 (PIN_INPUT | MUX_MODE3)           /* mcasp0_aclkx.spi1_clk */
 211                                 0x194 (PIN_OUTPUT | MUX_MODE3)           /* mcasp0_fsx.spi1_d0 */
 212                                 0x198 (PIN_INPUT | MUX_MODE3)           /* mcasp0_axr0.spi1_d1 */
 213                                 0x19c (PIN_OUTPUT | MUX_MODE3)          /* mcasp0_ahclkr.spi1_cs0 */
 214                         >;
 215                 };
 216
 217                 mmc1_pins: pinmux_mmc1_pins {
 218                         pinctrl-single,pins = <
 219                                 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
 220                         >;
 221                 };
 222
 223                 qspi1_default: qspi1_default {
 224                         pinctrl-single,pins = <
 225                                 0x7c (PIN_INPUT_PULLUP | MUX_MODE3)
 226                                 0x88 (PIN_INPUT_PULLUP | MUX_MODE2)
 227                                 0x90 (PIN_INPUT_PULLUP | MUX_MODE3)
 228                                 0x94 (PIN_INPUT_PULLUP | MUX_MODE3)
 229                                 0x98 (PIN_INPUT_PULLUP | MUX_MODE3)
 230                                 0x9c (PIN_INPUT_PULLUP | MUX_MODE3)
 231                         >;
 232                 };
 233
 234                 pixcir_ts_pins: pixcir_ts_pins {
 235                         pinctrl-single,pins = <
 236                                 0x44 (PIN_INPUT_PULLUP | MUX_MODE7)     /* gpmc_a1.gpio1_17 */
 237                         >;
 238                 };
 239
 240                 hdq_pins: pinmux_hdq_pins {
 241                         pinctrl-single,pins = <
 242                                 0x234 (PIN_INPUT_PULLUP | MUX_MODE1)    /* cam1_wen.hdq_gpio */
 243                         >;
 244                 };
 245
 246                 dss_pins: dss_pins {
 247                         pinctrl-single,pins = <
 248                                 0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
 249                                 0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1)
 250                                 0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1)
 251                                 0x02C (PIN_OUTPUT_PULLUP | MUX_MODE1)
 252                                 0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1)
 253                                 0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1)
 254                                 0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1)
 255                                 0x03C (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
 256                                 0x0A0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
 257                                 0x0A4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 258                                 0x0A8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 259                                 0x0AC (PIN_OUTPUT_PULLUP | MUX_MODE0)
 260                                 0x0B0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 261                                 0x0B4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 262                                 0x0B8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 263                                 0x0BC (PIN_OUTPUT_PULLUP | MUX_MODE0)
 264                                 0x0C0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 265                                 0x0C4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 266                                 0x0C8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 267                                 0x0CC (PIN_OUTPUT_PULLUP | MUX_MODE0)
 268                                 0x0D0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 269                                 0x0D4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 270                                 0x0D8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 271                                 0x0DC (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
 272                                 0x0E0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
 273                                 0x0E4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
 274                                 0x0E8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
 275                                 0x0EC (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
 276                         >;
 277                 };
 278
 279                 display_mux_pins: display_mux_pins {
 280                         pinctrl-single,pins = <
 281                                 /* GPMC CLK -> GPIO 2_1 to select LCD / HDMI */
 282                                 0x08C (PIN_OUTPUT_PULLUP | MUX_MODE7)
 283                         >;
 284                 };
 285
 286                 vpfe1_pins_default: vpfe1_pins_default {
 287                         pinctrl-single,pins = <
 288                                 0x1cc (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data9 mode 0 */
 289                                 0x1d0 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data8 mode 0 */
 290                                 0x1d4 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_hd mode 0 */
 291                                 0x1d8 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_vd mode 0 */
 292                                 0x1dc (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_pclk mode 0 */
 293                                 0x1e8 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data0 mode 0 */
 294                                 0x1ec (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data1 mode 0 */
 295                                 0x1f0 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data2 mode 0 */
 296                                 0x1f4 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data3 mode 0 */
 297                                 0x1f8 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data4 mode 0 */
 298                                 0x1fc (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data5 mode 0 */
 299                                 0x200 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data6 mode 0 */
 300                                 0x204 (PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data7 mode 0 */
 301                         >;
 302                 };
 303
 304                 vpfe1_pins_sleep: vpfe1_pins_sleep {
 305                         pinctrl-single,pins = <
 306                                 0x1cc (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
 307                                 0x1d0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
 308                                 0x1d4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
 309                                 0x1d8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
 310                                 0x1dc (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
 311                                 0x1e8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
 312                                 0x1ec (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
 313                                 0x1f0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
 314                                 0x1f4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
 315                                 0x1f8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
 316                                 0x1fc (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
 317                                 0x200 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
 318                                 0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
 319                         >;
 320                 };
 321
 322                 mcasp1_pins: mcasp1_pins {
 323                         pinctrl-single,pins = <
 324                                 0x1a0 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_ACLKR/MCASP1_ACLKX */
 325                                 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_FSR/MCASP1_FSX */
 326                                 0x1a8 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)/* MCASP0_AXR1/MCASP1_AXR0 */
 327                                 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_AHCLKX/MCASP1_AXR1 */
 328                         >;
 329                 };
 330
 331                 mcasp1_sleep_pins: mcasp1_sleep_pins {
 332                         pinctrl-single,pins = <
 333                                 0x1a0 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 334                                 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 335                                 0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 336                                 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE7)
 337                         >;
 338                 };
 339 };
 340
 341 &mmc1 {
 342         status = "okay";
 343         vmmc-supply = <&vmmcsd_fixed>;
 344         bus-width = <4>;
 345         pinctrl-names = "default";
 346         pinctrl-0 = <&mmc1_pins>;
 347         cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
 348 };
 349
 350 &mac {
 351         pinctrl-names = "default", "sleep";
 352         pinctrl-0 = <&cpsw_default>;
 353         pinctrl-1 = <&cpsw_sleep>;
 354         status = "okay";
 355 };
 356
 357 &davinci_mdio {
 358         pinctrl-names = "default", "sleep";
 359         pinctrl-0 = <&davinci_mdio_default>;
 360         pinctrl-1 = <&davinci_mdio_sleep>;
 361         status = "okay";
 362 };
 363
 364 &cpsw_emac0 {
 365         phy_id = <&davinci_mdio>, <16>;
 366         phy-mode = "rmii";
 367 };
 368
 369 &cpsw_emac1 {
 370         phy_id = <&davinci_mdio>, <1>;
 371         phy-mode = "rmii";
 372 };
 373
 374 &phy_sel {
 375         rmii-clock-ext;
 376 };
 377
 378 &i2c0 {
 379         status = "okay";
 380         pinctrl-names = "default";
 381         pinctrl-0 = <&i2c0_pins>;
 382         clock-frequency = <400000>;
 383
 384         tps65218: tps65218@24 {
 385                 reg = <0x24>;
 386                 compatible = "ti,tps65218";
 387                 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
 388                 interrupt-controller;
 389                 #interrupt-cells = <2>;
 390
 391                 dcdc1: regulator-dcdc1 {
 392                         compatible = "ti,tps65218-dcdc1";
 393                         regulator-name = "vdd_core";
 394                         regulator-min-microvolt = <912000>;
 395                         regulator-max-microvolt = <1144000>;
 396                         regulator-boot-on;
 397                         regulator-always-on;
 398                 };
 399
 400                 dcdc2: regulator-dcdc2 {
 401                         compatible = "ti,tps65218-dcdc2";
 402                         regulator-name = "vdd_mpu";
 403                         regulator-min-microvolt = <912000>;
 404                         regulator-max-microvolt = <1378000>;
 405                         regulator-boot-on;
 406                         regulator-always-on;
 407                 };
 408
 409                 dcdc3: regulator-dcdc3 {
 410                         compatible = "ti,tps65218-dcdc3";
 411                         regulator-name = "vdcdc3";
 412                         regulator-min-microvolt = <1500000>;
 413                         regulator-max-microvolt = <1500000>;
 414                         regulator-boot-on;
 415                         regulator-always-on;
 416                 };
 417
 418                 dcdc4: regulator-dcdc4 {
 419                         compatible = "ti,tps65218-dcdc4";
 420                         regulator-name = "vdcdc4";
 421                         regulator-min-microvolt = <3300000>;
 422                         regulator-max-microvolt = <3300000>;
 423                         regulator-boot-on;
 424                         regulator-always-on;
 425                 };
 426
 427                 dcdc5: regulator-dcdc5 {
 428                         compatible = "ti,tps65218-dcdc5";
 429                         regulator-name = "v1_0bat";
 430                         regulator-min-microvolt = <1000000>;
 431                         regulator-max-microvolt = <1000000>;
 432                 };
 433
 434                 dcdc6: regulator-dcdc6 {
 435                         compatible = "ti,tps65218-dcdc6";
 436                         regulator-name = "v1_8bat";
 437                         regulator-min-microvolt = <1800000>;
 438                         regulator-max-microvolt = <1800000>;
 439                 };
 440
 441                 ldo1: regulator-ldo1 {
 442                         compatible = "ti,tps65218-ldo1";
 443                         regulator-min-microvolt = <1800000>;
 444                         regulator-max-microvolt = <1800000>;
 445                         regulator-boot-on;
 446                         regulator-always-on;
 447                 };
 448         };
 449
 450         at24@50 {
 451                 compatible = "at24,24c256";
 452                 pagesize = <64>;
 453                 reg = <0x50>;
 454         };
 455
 456         pixcir_ts@5c {
 457                 compatible = "pixcir,pixcir_tangoc";
 458                 pinctrl-names = "default";
 459                 pinctrl-0 = <&pixcir_ts_pins>;
 460                 reg = <0x5c>;
 461                 interrupt-parent = <&gpio1>;
 462                 interrupts = <17 0>;
 463
 464                 attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
 465
 466                 touchscreen-size-x = <1024>;
 467                 touchscreen-size-y = <600>;
 468         };
 469
 470         tlv320aic3111: tlv320aic3111@18 {
 471                 compatible = "ti,tlv320aic3111";
 472                 reg = <0x18>;
 473                 status = "okay";
 474
 475                 ai31xx-micbias-vg = <MICBIAS_2_0V>;
 476
 477                 /* Regulators */
 478                 HPVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */
 479                 SPRVDD-supply = <&vbat>; /* vbat */
 480                 SPLVDD-supply = <&vbat>; /* vbat */
 481                 AVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */
 482                 IOVDD-supply = <&dcdc4>; /* V3_3D -> DCDC4 */
 483                 DVDD-supply = <&ldo1>; /* V1_8AUD -> V1_8D -> LDO1 */
 484         };
 485 };
 486
 487 &i2c2 {
 488         pinctrl-names = "default";
 489         pinctrl-0 = <&i2c2_pins>;
 490         status = "okay";
 491 };
 492
 493 &gpio0 {
 494         status = "okay";
 495 };
 496
 497 &gpio1 {
 498         status = "okay";
 499 };
 500
 501 &gpio2 {
 502         pinctrl-names = "default";
 503         pinctrl-0 = <&display_mux_pins>;
 504         status = "okay";
 505
 506         p1 {
 507                 /*
 508                  * SelLCDorHDMI selects between display and audio paths:
 509                  * Low: HDMI display with audio via HDMI
 510                  * High: LCD display with analog audio via aic3111 codec
 511                  */
 512                 gpio-hog;
 513                 gpios = <1 GPIO_ACTIVE_HIGH>;
 514                 output-high;
 515                 line-name = "SelLCDorHDMI";
 516         };
 517 };
 518
 519 &gpio3 {
 520         status = "okay";
 521 };
 522
 523 &elm {
 524         status = "okay";
 525 };
 526
 527 &gpmc {
 528         status = "okay";        /* Disable QSPI when enabling GPMC (NAND) */
 529         pinctrl-names = "default";
 530         pinctrl-0 = <&nand_flash_x8>;
 531         ranges = <0 0 0x08000000 0x1000000>;    /* CS0: 16MB for NAND */
 532         nand@0,0 {
 533                 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
 534                 ti,nand-ecc-opt = "bch16";
 535                 ti,elm-id = <&elm>;
 536                 nand-bus-width = <8>;
 537                 gpmc,device-width = <1>;
 538                 gpmc,sync-clk-ps = <0>;
 539                 gpmc,cs-on-ns = <0>;
 540                 gpmc,cs-rd-off-ns = <40>; /* tCEA + tCHZ + 1 */
 541                 gpmc,cs-wr-off-ns = <40>;
 542                 gpmc,adv-on-ns = <0>;  /* cs-on-ns */
 543                 gpmc,adv-rd-off-ns = <25>; /* min( tALH + tALS + 1) */
 544                 gpmc,adv-wr-off-ns = <25>; /* min( tALH + tALS + 1) */
 545                 gpmc,we-on-ns = <0>;   /* cs-on-ns */
 546                 gpmc,we-off-ns = <20>; /* we-on-time + tWP + 2 */
 547                 gpmc,oe-on-ns = <3>;  /* cs-on-ns + tRR + 2 */
 548                 gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */
 549                 gpmc,access-ns = <30>; /* tCEA + 4*/
 550                 gpmc,rd-cycle-ns = <40>;
 551                 gpmc,wr-cycle-ns = <40>;
 552                 gpmc,wait-pin = <0>;
 553                 gpmc,bus-turnaround-ns = <0>;
 554                 gpmc,cycle2cycle-delay-ns = <0>;
 555                 gpmc,clk-activation-ns = <0>;
 556                 gpmc,wait-monitoring-ns = <0>;
 557                 gpmc,wr-access-ns = <40>;
 558                 gpmc,wr-data-mux-bus-ns = <0>;
 559                 /* MTD partition table */
 560                 /* All SPL-* partitions are sized to minimal length
 561                  * which can be independently programmable. For
 562                  * NAND flash this is equal to size of erase-block */
 563                 #address-cells = <1>;
 564                 #size-cells = <1>;
 565                 partition@0 {
 566                         label = "NAND.SPL";
 567                         reg = <0x00000000 0x00040000>;
 568                 };
 569                 partition@1 {
 570                         label = "NAND.SPL.backup1";
 571                         reg = <0x00040000 0x00040000>;
 572                 };
 573                 partition@2 {
 574                         label = "NAND.SPL.backup2";
 575                         reg = <0x00080000 0x00040000>;
 576                 };
 577                 partition@3 {
 578                         label = "NAND.SPL.backup3";
 579                         reg = <0x000C0000 0x00040000>;
 580                 };
 581                 partition@4 {
 582                         label = "NAND.u-boot-spl-os";
 583                         reg = <0x00100000 0x00080000>;
 584                 };
 585                 partition@5 {
 586                         label = "NAND.u-boot";
 587                         reg = <0x00180000 0x00100000>;
 588                 };
 589                 partition@6 {
 590                         label = "NAND.u-boot-env";
 591                         reg = <0x00280000 0x00040000>;
 592                 };
 593                 partition@7 {
 594                         label = "NAND.u-boot-env.backup1";
 595                         reg = <0x002C0000 0x00040000>;
 596                 };
 597                 partition@8 {
 598                         label = "NAND.kernel";
 599                         reg = <0x00300000 0x00700000>;
 600                 };
 601                 partition@9 {
 602                         label = "NAND.file-system";
 603                         reg = <0x00a00000 0x1f600000>;
 604                 };
 605         };
 606 };
 607
 608 &epwmss0 {
 609         status = "okay";
 610 };
 611
 612 &tscadc {
 613         status = "okay";
 614
 615         adc {
 616                 ti,adc-channels = <0 1 2 3 4 5 6 7>;
 617         };
 618 };
 619
 620 &ecap0 {
 621                 status = "okay";
 622                 pinctrl-names = "default";
 623                 pinctrl-0 = <&ecap0_pins>;
 624 };
 625
 626 &spi0 {
 627         pinctrl-names = "default";
 628         pinctrl-0 = <&spi0_pins>;
 629         status = "okay";
 630 };
 631
 632 &spi1 {
 633         pinctrl-names = "default";
 634         pinctrl-0 = <&spi1_pins>;
 635         status = "okay";
 636 };
 637
 638 &usb2_phy1 {
 639         status = "okay";
 640 };
 641
 642 &usb1 {
 643         dr_mode = "peripheral";
 644         status = "okay";
 645 };
 646
 647 &usb2_phy2 {
 648         status = "okay";
 649 };
 650
 651 &usb2 {
 652         dr_mode = "host";
 653         status = "okay";
 654 };
 655
 656 &qspi {
 657         status = "disabled";    /* Disable GPMC (NAND) when enabling QSPI */
 658         pinctrl-names = "default";
 659         pinctrl-0 = <&qspi1_default>;
 660
 661         spi-max-frequency = <48000000>;
 662         m25p80@0 {
 663                 compatible = "mx66l51235l";
 664                 spi-max-frequency = <48000000>;
 665                 reg = <0>;
 666                 spi-cpol;
 667                 spi-cpha;
 668                 spi-tx-bus-width = <1>;
 669                 spi-rx-bus-width = <4>;
 670                 #address-cells = <1>;
 671                 #size-cells = <1>;
 672
 673                 /* MTD partition table.
 674                  * The ROM checks the first 512KiB
 675                  * for a valid file to boot(XIP).
 676                  */
 677                 partition@0 {
 678                         label = "QSPI.U_BOOT";
 679                         reg = <0x00000000 0x000080000>;
 680                 };
 681                 partition@1 {
 682                         label = "QSPI.U_BOOT.backup";
 683                         reg = <0x00080000 0x00080000>;
 684                 };
 685                 partition@2 {
 686                         label = "QSPI.U-BOOT-SPL_OS";
 687                         reg = <0x00100000 0x00010000>;
 688                 };
 689                 partition@3 {
 690                         label = "QSPI.U_BOOT_ENV";
 691                         reg = <0x00110000 0x00010000>;
 692                 };
 693                 partition@4 {
 694                         label = "QSPI.U-BOOT-ENV.backup";
 695                         reg = <0x00120000 0x00010000>;
 696                 };
 697                 partition@5 {
 698                         label = "QSPI.KERNEL";
 699                         reg = <0x00130000 0x0800000>;
 700                 };
 701                 partition@6 {
 702                         label = "QSPI.FILESYSTEM";
 703                         reg = <0x00930000 0x36D0000>;
 704                 };
 705         };
 706 };
 707
 708 &hdq {
 709         status = "okay";
 710         pinctrl-names = "default";
 711         pinctrl-0 = <&hdq_pins>;
 712 };
 713
 714 &dss {
 715         status = "ok";
 716
 717         pinctrl-names = "default";
 718         pinctrl-0 = <&dss_pins>;
 719
 720         port {
 721                 dpi_out: endpoint@0 {
 722                         remote-endpoint = <&lcd_in>;
 723                         data-lines = <24>;
 724                 };
 725         };
 726 };
 727
 728 &vpfe1 {
 729         status = "okay";
 730         pinctrl-names = "default", "sleep";
 731         pinctrl-0 = <&vpfe1_pins_default>;
 732         pinctrl-1 = <&vpfe1_pins_sleep>;
 733
 734         port {
 735                 vpfe1_ep: endpoint {
 736                         /* remote-endpoint = <&sensor>; add once we have it */
 737                         ti,am437x-vpfe-interface = <0>;
 738                         bus-width = <8>;
 739                         hsync-active = <0>;
 740                         vsync-active = <0>;
 741                 };
 742         };
 743 };
 744
 745 &mcasp1 {
 746         pinctrl-names = "default", "sleep";
 747         pinctrl-0 = <&mcasp1_pins>;
 748         pinctrl-1 = <&mcasp1_sleep_pins>;
 749
 750         status = "okay";
 751
 752         op-mode = <0>;          /* MCASP_IIS_MODE */
 753         tdm-slots = <2>;
 754         /* 4 serializer */
 755         serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
 756                 1 2 0 0
 757         >;
 758         tx-num-evt = <32>;
 759         rx-num-evt = <32>;
 760 };