2 * Device Tree Source for AM43xx clock data
4 * Copyright (C) 2013 Texas Instruments, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 sys_clkin_ck: sys_clkin_ck {
13 compatible = "ti,mux-clock";
14 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
19 adc_tsc_fck: adc_tsc_fck {
21 compatible = "fixed-factor-clock";
22 clocks = <&sys_clkin_ck>;
27 dcan0_fck: dcan0_fck {
29 compatible = "fixed-factor-clock";
30 clocks = <&sys_clkin_ck>;
35 dcan1_fck: dcan1_fck {
37 compatible = "fixed-factor-clock";
38 clocks = <&sys_clkin_ck>;
43 mcasp0_fck: mcasp0_fck {
45 compatible = "fixed-factor-clock";
46 clocks = <&sys_clkin_ck>;
51 mcasp1_fck: mcasp1_fck {
53 compatible = "fixed-factor-clock";
54 clocks = <&sys_clkin_ck>;
59 smartreflex0_fck: smartreflex0_fck {
61 compatible = "fixed-factor-clock";
62 clocks = <&sys_clkin_ck>;
67 smartreflex1_fck: smartreflex1_fck {
69 compatible = "fixed-factor-clock";
70 clocks = <&sys_clkin_ck>;
77 compatible = "fixed-factor-clock";
78 clocks = <&sys_clkin_ck>;
85 compatible = "fixed-factor-clock";
86 clocks = <&sys_clkin_ck>;
92 clk_32768_ck: clk_32768_ck {
94 compatible = "fixed-clock";
95 clock-frequency = <32768>;
98 clk_rc32k_ck: clk_rc32k_ck {
100 compatible = "fixed-clock";
101 clock-frequency = <32768>;
104 virt_19200000_ck: virt_19200000_ck {
106 compatible = "fixed-clock";
107 clock-frequency = <19200000>;
110 virt_24000000_ck: virt_24000000_ck {
112 compatible = "fixed-clock";
113 clock-frequency = <24000000>;
116 virt_25000000_ck: virt_25000000_ck {
118 compatible = "fixed-clock";
119 clock-frequency = <25000000>;
122 virt_26000000_ck: virt_26000000_ck {
124 compatible = "fixed-clock";
125 clock-frequency = <26000000>;
128 tclkin_ck: tclkin_ck {
130 compatible = "fixed-clock";
131 clock-frequency = <26000000>;
134 dpll_core_ck: dpll_core_ck {
136 compatible = "ti,am3-dpll-core-clock";
137 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
138 reg = <0x2d20>, <0x2d24>, <0x2d2c>;
141 dpll_core_x2_ck: dpll_core_x2_ck {
143 compatible = "ti,am3-dpll-x2-clock";
144 clocks = <&dpll_core_ck>;
147 dpll_core_m4_ck: dpll_core_m4_ck {
149 compatible = "ti,divider-clock";
150 clocks = <&dpll_core_x2_ck>;
152 ti,autoidle-shift = <8>;
154 ti,index-starts-at-one;
155 ti,invert-autoidle-bit;
158 dpll_core_m5_ck: dpll_core_m5_ck {
160 compatible = "ti,divider-clock";
161 clocks = <&dpll_core_x2_ck>;
163 ti,autoidle-shift = <8>;
165 ti,index-starts-at-one;
166 ti,invert-autoidle-bit;
169 dpll_core_m6_ck: dpll_core_m6_ck {
171 compatible = "ti,divider-clock";
172 clocks = <&dpll_core_x2_ck>;
174 ti,autoidle-shift = <8>;
176 ti,index-starts-at-one;
177 ti,invert-autoidle-bit;
180 dpll_mpu_ck: dpll_mpu_ck {
182 compatible = "ti,am3-dpll-clock";
183 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
184 reg = <0x2d60>, <0x2d64>, <0x2d6c>;
187 dpll_mpu_m2_ck: dpll_mpu_m2_ck {
189 compatible = "ti,divider-clock";
190 clocks = <&dpll_mpu_ck>;
192 ti,autoidle-shift = <8>;
194 ti,index-starts-at-one;
195 ti,invert-autoidle-bit;
198 dpll_ddr_ck: dpll_ddr_ck {
200 compatible = "ti,am3-dpll-clock";
201 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
202 reg = <0x2da0>, <0x2da4>, <0x2dac>;
205 dpll_ddr_m2_ck: dpll_ddr_m2_ck {
207 compatible = "ti,divider-clock";
208 clocks = <&dpll_ddr_ck>;
210 ti,autoidle-shift = <8>;
212 ti,index-starts-at-one;
213 ti,invert-autoidle-bit;
216 dpll_disp_ck: dpll_disp_ck {
218 compatible = "ti,am3-dpll-clock";
219 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
220 reg = <0x2e20>, <0x2e24>, <0x2e2c>;
223 dpll_disp_m2_ck: dpll_disp_m2_ck {
225 compatible = "ti,divider-clock";
226 clocks = <&dpll_disp_ck>;
228 ti,autoidle-shift = <8>;
230 ti,index-starts-at-one;
231 ti,invert-autoidle-bit;
234 dpll_per_ck: dpll_per_ck {
236 compatible = "ti,am3-dpll-j-type-clock";
237 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
238 reg = <0x2de0>, <0x2de4>, <0x2dec>;
241 dpll_per_m2_ck: dpll_per_m2_ck {
243 compatible = "ti,divider-clock";
244 clocks = <&dpll_per_ck>;
246 ti,autoidle-shift = <8>;
248 ti,index-starts-at-one;
249 ti,invert-autoidle-bit;
252 dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
254 compatible = "fixed-factor-clock";
255 clocks = <&dpll_per_m2_ck>;
260 dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
262 compatible = "fixed-factor-clock";
263 clocks = <&dpll_per_m2_ck>;
268 clk_24mhz: clk_24mhz {
270 compatible = "fixed-factor-clock";
271 clocks = <&dpll_per_m2_ck>;
276 clkdiv32k_ck: clkdiv32k_ck {
278 compatible = "fixed-factor-clock";
279 clocks = <&clk_24mhz>;
284 clkdiv32k_ick: clkdiv32k_ick {
286 compatible = "ti,gate-clock";
287 clocks = <&clkdiv32k_ck>;
292 sysclk_div: sysclk_div {
294 compatible = "fixed-factor-clock";
295 clocks = <&dpll_core_m4_ck>;
300 pruss_ocp_gclk: pruss_ocp_gclk {
302 compatible = "ti,mux-clock";
303 clocks = <&sysclk_div>, <&dpll_disp_m2_ck>;
307 clk_32k_tpm_ck: clk_32k_tpm_ck {
309 compatible = "fixed-clock";
310 clock-frequency = <32768>;
313 timer1_fck: timer1_fck {
315 compatible = "ti,mux-clock";
316 clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>;
320 timer2_fck: timer2_fck {
322 compatible = "ti,mux-clock";
323 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
327 timer3_fck: timer3_fck {
329 compatible = "ti,mux-clock";
330 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
334 timer4_fck: timer4_fck {
336 compatible = "ti,mux-clock";
337 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
341 timer5_fck: timer5_fck {
343 compatible = "ti,mux-clock";
344 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
348 timer6_fck: timer6_fck {
350 compatible = "ti,mux-clock";
351 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
355 timer7_fck: timer7_fck {
357 compatible = "ti,mux-clock";
358 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
364 compatible = "ti,mux-clock";
365 clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
371 compatible = "fixed-factor-clock";
372 clocks = <&dpll_core_m4_ck>;
377 dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
379 compatible = "fixed-factor-clock";
380 clocks = <&sysclk_div>;
385 l4hs_gclk: l4hs_gclk {
387 compatible = "fixed-factor-clock";
388 clocks = <&dpll_core_m4_ck>;
395 compatible = "fixed-factor-clock";
396 clocks = <&dpll_core_m4_div2_ck>;
401 l4ls_gclk: l4ls_gclk {
403 compatible = "fixed-factor-clock";
404 clocks = <&dpll_core_m4_div2_ck>;
409 cpsw_125mhz_gclk: cpsw_125mhz_gclk {
411 compatible = "fixed-factor-clock";
412 clocks = <&dpll_core_m5_ck>;
417 cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
419 compatible = "ti,mux-clock";
420 clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>;
424 clk_32k_mosc_ck: clk_32k_mosc_ck {
426 compatible = "fixed-clock";
427 clock-frequency = <32768>;
430 gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck {
432 compatible = "ti,mux-clock";
433 clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>;
437 gpio0_dbclk: gpio0_dbclk {
439 compatible = "ti,gate-clock";
440 clocks = <&gpio0_dbclk_mux_ck>;
445 gpio1_dbclk: gpio1_dbclk {
447 compatible = "ti,gate-clock";
448 clocks = <&clkdiv32k_ick>;
453 gpio2_dbclk: gpio2_dbclk {
455 compatible = "ti,gate-clock";
456 clocks = <&clkdiv32k_ick>;
461 gpio3_dbclk: gpio3_dbclk {
463 compatible = "ti,gate-clock";
464 clocks = <&clkdiv32k_ick>;
469 gpio4_dbclk: gpio4_dbclk {
471 compatible = "ti,gate-clock";
472 clocks = <&clkdiv32k_ick>;
477 gpio5_dbclk: gpio5_dbclk {
479 compatible = "ti,gate-clock";
480 clocks = <&clkdiv32k_ick>;
487 compatible = "fixed-factor-clock";
488 clocks = <&dpll_per_m2_ck>;
493 gfx_fclk_clksel_ck: gfx_fclk_clksel_ck {
495 compatible = "ti,mux-clock";
496 clocks = <&sysclk_div>, <&dpll_per_m2_ck>;
501 gfx_fck_div_ck: gfx_fck_div_ck {
503 compatible = "ti,divider-clock";
504 clocks = <&gfx_fclk_clksel_ck>;
511 compatible = "ti,mux-clock";
512 clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
516 dpll_extdev_ck: dpll_extdev_ck {
518 compatible = "ti,am3-dpll-clock";
519 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
520 reg = <0x2e60>, <0x2e64>, <0x2e6c>;
523 dpll_extdev_m2_ck: dpll_extdev_m2_ck {
525 compatible = "ti,divider-clock";
526 clocks = <&dpll_extdev_ck>;
528 ti,autoidle-shift = <8>;
530 ti,index-starts-at-one;
531 ti,invert-autoidle-bit;
534 mux_synctimer32k_ck: mux_synctimer32k_ck {
536 compatible = "ti,mux-clock";
537 clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>;
541 synctimer_32kclk: synctimer_32kclk {
543 compatible = "ti,gate-clock";
544 clocks = <&mux_synctimer32k_ck>;
549 timer8_fck: timer8_fck {
551 compatible = "ti,mux-clock";
552 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
556 timer9_fck: timer9_fck {
558 compatible = "ti,mux-clock";
559 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
563 timer10_fck: timer10_fck {
565 compatible = "ti,mux-clock";
566 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
570 timer11_fck: timer11_fck {
572 compatible = "ti,mux-clock";
573 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
577 cpsw_50m_clkdiv: cpsw_50m_clkdiv {
579 compatible = "fixed-factor-clock";
580 clocks = <&dpll_core_m5_ck>;
585 cpsw_5m_clkdiv: cpsw_5m_clkdiv {
587 compatible = "fixed-factor-clock";
588 clocks = <&cpsw_50m_clkdiv>;
593 dpll_ddr_x2_ck: dpll_ddr_x2_ck {
595 compatible = "ti,am3-dpll-x2-clock";
596 clocks = <&dpll_ddr_ck>;
599 dpll_ddr_m4_ck: dpll_ddr_m4_ck {
601 compatible = "ti,divider-clock";
602 clocks = <&dpll_ddr_x2_ck>;
604 ti,autoidle-shift = <8>;
606 ti,index-starts-at-one;
607 ti,invert-autoidle-bit;
610 dpll_per_clkdcoldo: dpll_per_clkdcoldo {
612 compatible = "fixed-factor-clock";
613 clocks = <&dpll_per_ck>;
618 dll_aging_clk_div: dll_aging_clk_div {
620 compatible = "ti,divider-clock";
621 clocks = <&sys_clkin_ck>;
623 ti,dividers = <8>, <16>, <32>;
626 div_core_25m_ck: div_core_25m_ck {
628 compatible = "fixed-factor-clock";
629 clocks = <&sysclk_div>;
634 func_12m_clk: func_12m_clk {
636 compatible = "fixed-factor-clock";
637 clocks = <&dpll_per_m2_ck>;
642 vtp_clk_div: vtp_clk_div {
644 compatible = "fixed-factor-clock";
645 clocks = <&sys_clkin_ck>;
650 usbphy_32khz_clkmux: usbphy_32khz_clkmux {
652 compatible = "ti,mux-clock";
653 clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>;