2 * Device Tree Include file for Marvell Armada 370 and Armada XP SoC
4 * Copyright (C) 2012 Marvell
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
15 * This file contains the definitions that are common to the Armada
16 * 370 and Armada XP SoC.
19 /include/ "skeleton64.dtsi"
21 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
24 model = "Marvell Armada 370 and XP SoC";
25 compatible = "marvell,armada-370-xp";
36 compatible = "marvell,sheeva-v7";
45 controller = <&mbusc>;
46 interrupt-parent = <&mpic>;
47 pcie-mem-aperture = <0xe0000000 0x8000000>;
48 pcie-io-aperture = <0xe8000000 0x100000>;
51 compatible = "marvell,mvebu-devbus";
52 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
53 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
56 clocks = <&coreclk 0>;
61 compatible = "marvell,mvebu-devbus";
62 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
63 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
66 clocks = <&coreclk 0>;
71 compatible = "marvell,mvebu-devbus";
72 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
73 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
76 clocks = <&coreclk 0>;
81 compatible = "marvell,mvebu-devbus";
82 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
83 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
86 clocks = <&coreclk 0>;
91 compatible = "marvell,mvebu-devbus";
92 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
93 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
96 clocks = <&coreclk 0>;
101 compatible = "simple-bus";
102 #address-cells = <1>;
104 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
107 compatible = "marvell,orion-rtc";
108 reg = <0x10300 0x20>;
113 compatible = "marvell,orion-spi";
114 reg = <0x10600 0x28>;
115 #address-cells = <1>;
119 clocks = <&coreclk 0>;
124 compatible = "marvell,orion-spi";
125 reg = <0x10680 0x28>;
126 #address-cells = <1>;
130 clocks = <&coreclk 0>;
135 compatible = "marvell,mv64xxx-i2c";
136 #address-cells = <1>;
140 clocks = <&coreclk 0>;
145 compatible = "marvell,mv64xxx-i2c";
146 #address-cells = <1>;
150 clocks = <&coreclk 0>;
155 compatible = "snps,dw-apb-uart";
156 reg = <0x12000 0x100>;
163 compatible = "snps,dw-apb-uart";
164 reg = <0x12100 0x100>;
171 coredivclk: corediv-clock@18740 {
172 compatible = "marvell,armada-370-corediv-clock";
176 clock-output-names = "nand";
179 mbusc: mbus-controller@20000 {
180 compatible = "marvell,mbus-controller";
181 reg = <0x20000 0x100>, <0x20180 0x20>;
184 mpic: interrupt-controller@20000 {
185 compatible = "marvell,mpic";
186 #interrupt-cells = <1>;
188 interrupt-controller;
192 coherency-fabric@20200 {
193 compatible = "marvell,coherency-fabric";
194 reg = <0x20200 0xb0>, <0x21010 0x1c>;
198 reg = <0x20300 0x30>, <0x21040 0x30>;
199 interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
203 compatible = "marvell,orion-ehci";
204 reg = <0x50000 0x500>;
210 compatible = "marvell,orion-ehci";
211 reg = <0x51000 0x500>;
216 eth0: ethernet@70000 {
217 compatible = "marvell,armada-370-neta";
218 reg = <0x70000 0x4000>;
220 clocks = <&gateclk 4>;
225 #address-cells = <1>;
227 compatible = "marvell,orion-mdio";
231 eth1: ethernet@74000 {
232 compatible = "marvell,armada-370-neta";
233 reg = <0x74000 0x4000>;
235 clocks = <&gateclk 3>;
240 compatible = "marvell,armada-370-sata";
241 reg = <0xa0000 0x5000>;
243 clocks = <&gateclk 15>, <&gateclk 30>;
244 clock-names = "0", "1";
249 compatible = "marvell,armada370-nand";
250 reg = <0xd0000 0x54>;
251 #address-cells = <1>;
254 clocks = <&coredivclk 0>;
259 compatible = "marvell,orion-sdio";
260 reg = <0xd4000 0x200>;
262 clocks = <&gateclk 17>;
273 /* 2 GHz fixed main PLL */
275 compatible = "fixed-clock";
277 clock-frequency = <2000000000>;