arch/arm/boot/dts/armada-370.dtsi

   1 /*
   2  * Device Tree Include file for Marvell Armada 370 family SoC
   3  *
   4  * Copyright (C) 2012 Marvell
   5  *
   6  * Lior Amsalem <alior@marvell.com>
   7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   8  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   9  *
  10  * This file is licensed under the terms of the GNU General Public
  11  * License version 2.  This program is licensed "as is" without any
  12  * warranty of any kind, whether express or implied.
  13  *
  14  * Contains definitions specific to the Armada 370 SoC that are not
  15  * common to all Armada SoCs.
  16  */
  17
  18 /include/ "armada-370-xp.dtsi"
  19
  20 / {
  21         model = "Marvell Armada 370 family SoC";
  22         compatible = "marvell,armada370", "marvell,armada-370-xp";
  23
  24         aliases {
  25                 gpio0 = &gpio0;
  26                 gpio1 = &gpio1;
  27                 gpio2 = &gpio2;
  28         };
  29
  30         soc {
  31
  32                 mpic: interrupt-controller@20000 {
  33                         reg = <0x20a00 0x1d0>,
  34                               <0x21870 0x58>;
  35                 };
  36
  37                 system-controller@18200 {
  38                                 compatible = "marvell,armada-370-xp-system-controller";
  39                                 reg = <0x18200 0x100>;
  40                 };
  41
  42                 L2: l2-cache {
  43                         compatible = "marvell,aurora-outer-cache";
  44                         reg = <0xd0008000 0x1000>;
  45                         cache-id-part = <0x100>;
  46                         wt-override;
  47                 };
  48
  49                 pinctrl {
  50                         compatible = "marvell,mv88f6710-pinctrl";
  51                         reg = <0x18000 0x38>;
  52
  53                         sdio_pins1: sdio-pins1 {
  54                               marvell,pins = "mpp9",  "mpp11", "mpp12",
  55                                              "mpp13", "mpp14", "mpp15";
  56                               marvell,function = "sd0";
  57                         };
  58
  59                         sdio_pins2: sdio-pins2 {
  60                               marvell,pins = "mpp47", "mpp48", "mpp49",
  61                                              "mpp50", "mpp51", "mpp52";
  62                               marvell,function = "sd0";
  63                         };
  64
  65                         sdio_pins3: sdio-pins3 {
  66                               marvell,pins = "mpp48", "mpp49", "mpp50",
  67                                              "mpp51", "mpp52", "mpp53";
  68                               marvell,function = "sd0";
  69                         };
  70                 };
  71
  72                 gpio0: gpio@18100 {
  73                         compatible = "marvell,orion-gpio";
  74                         reg = <0x18100 0x40>;
  75                         ngpios = <32>;
  76                         gpio-controller;
  77                         #gpio-cells = <2>;
  78                         interrupt-controller;
  79                         #interrupts-cells = <2>;
  80                         interrupts = <82>, <83>, <84>, <85>;
  81                 };
  82
  83                 gpio1: gpio@18140 {
  84                         compatible = "marvell,orion-gpio";
  85                         reg = <0x18140 0x40>;
  86                         ngpios = <32>;
  87                         gpio-controller;
  88                         #gpio-cells = <2>;
  89                         interrupt-controller;
  90                         #interrupts-cells = <2>;
  91                         interrupts = <87>, <88>, <89>, <90>;
  92                 };
  93
  94                 gpio2: gpio@18180 {
  95                         compatible = "marvell,orion-gpio";
  96                         reg = <0x18180 0x40>;
  97                         ngpios = <2>;
  98                         gpio-controller;
  99                         #gpio-cells = <2>;
 100                         interrupt-controller;
 101                         #interrupts-cells = <2>;
 102                         interrupts = <91>;
 103                 };
 104
 105                 coreclk: mvebu-sar@18230 {
 106                         compatible = "marvell,armada-370-core-clock";
 107                         reg = <0x18230 0x08>;
 108                         #clock-cells = <1>;
 109                 };
 110
 111                 gateclk: clock-gating-control@18220 {
 112                         compatible = "marvell,armada-370-gating-clock";
 113                         reg = <0x18220 0x4>;
 114                         clocks = <&coreclk 0>;
 115                         #clock-cells = <1>;
 116                 };
 117
 118                 xor@60800 {
 119                         compatible = "marvell,orion-xor";
 120                         reg = <0x60800 0x100
 121                                0x60A00 0x100>;
 122                         status = "okay";
 123
 124                         xor00 {
 125                                 interrupts = <51>;
 126                                 dmacap,memcpy;
 127                                 dmacap,xor;
 128                         };
 129                         xor01 {
 130                                 interrupts = <52>;
 131                                 dmacap,memcpy;
 132                                 dmacap,xor;
 133                                 dmacap,memset;
 134                         };
 135                 };
 136
 137                 xor@60900 {
 138                         compatible = "marvell,orion-xor";
 139                         reg = <0x60900 0x100
 140                                0x60b00 0x100>;
 141                         status = "okay";
 142
 143                         xor10 {
 144                                 interrupts = <94>;
 145                                 dmacap,memcpy;
 146                                 dmacap,xor;
 147                         };
 148                         xor11 {
 149                                 interrupts = <95>;
 150                                 dmacap,memcpy;
 151                                 dmacap,xor;
 152                                 dmacap,memset;
 153                         };
 154                 };
 155
 156                 usb@50000 {
 157                         clocks = <&coreclk 0>;
 158                 };
 159
 160                 usb@51000 {
 161                         clocks = <&coreclk 0>;
 162                 };
 163
 164                 thermal@18300 {
 165                         compatible = "marvell,armada370-thermal";
 166                         reg = <0x18300 0x4
 167                                0x18304 0x4>;
 168                         status = "okay";
 169                 };
 170
 171                 pcie-controller {
 172                         compatible = "marvell,armada-370-pcie";
 173                         status = "disabled";
 174                         device_type = "pci";
 175
 176                         #address-cells = <3>;
 177                         #size-cells = <2>;
 178
 179                         bus-range = <0x00 0xff>;
 180
 181                         reg = <0x40000 0x2000>, <0x80000 0x2000>;
 182
 183                         reg-names = "pcie0.0", "pcie1.0";
 184
 185                         ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000   /* Port 0.0 registers */
 186                                   0x82000000 0 0x80000 0x80000 0 0x00002000   /* Port 1.0 registers */
 187                                   0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
 188                                   0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */
 189
 190                         pcie@1,0 {
 191                                 device_type = "pci";
 192                                 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
 193                                 reg = <0x0800 0 0 0 0>;
 194                                 #address-cells = <3>;
 195                                 #size-cells = <2>;
 196                                 #interrupt-cells = <1>;
 197                                 ranges;
 198                                 interrupt-map-mask = <0 0 0 0>;
 199                                 interrupt-map = <0 0 0 0 &mpic 58>;
 200                                 marvell,pcie-port = <0>;
 201                                 marvell,pcie-lane = <0>;
 202                                 clocks = <&gateclk 5>;
 203                                 status = "disabled";
 204                         };
 205
 206                         pcie@2,0 {
 207                                 device_type = "pci";
 208                                 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
 209                                 reg = <0x1000 0 0 0 0>;
 210                                 #address-cells = <3>;
 211                                 #size-cells = <2>;
 212                                 #interrupt-cells = <1>;
 213                                 ranges;
 214                                 interrupt-map-mask = <0 0 0 0>;
 215                                 interrupt-map = <0 0 0 0 &mpic 62>;
 216                                 marvell,pcie-port = <1>;
 217                                 marvell,pcie-lane = <0>;
 218                                 clocks = <&gateclk 9>;
 219                                 status = "disabled";
 220                         };
 221                 };
 222         };
 223 };