arch/arm/boot/dts/armada-375.dtsi

   1 /*
   2  * Device Tree Include file for Marvell Armada 375 family SoC
   3  *
   4  * Copyright (C) 2014 Marvell
   5  *
   6  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   7  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   8  *
   9  * This file is dual-licensed: you can use it either under the terms
  10  * of the GPL or the X11 license, at your option. Note that this dual
  11  * licensing only applies to this file, and not this project as a
  12  * whole.
  13  *
  14  *  a) This file is free software; you can redistribute it and/or
  15  *     modify it under the terms of the GNU General Public License as
  16  *     published by the Free Software Foundation; either version 2 of the
  17  *     License, or (at your option) any later version.
  18  *
  19  *     This file is distributed in the hope that it will be useful
  20  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  *     GNU General Public License for more details.
  23  *
  24  * Or, alternatively
  25  *
  26  *  b) Permission is hereby granted, free of charge, to any person
  27  *     obtaining a copy of this software and associated documentation
  28  *     files (the "Software"), to deal in the Software without
  29  *     restriction, including without limitation the rights to use
  30  *     copy, modify, merge, publish, distribute, sublicense, and/or
  31  *     sell copies of the Software, and to permit persons to whom the
  32  *     Software is furnished to do so, subject to the following
  33  *     conditions:
  34  *
  35  *     The above copyright notice and this permission notice shall be
  36  *     included in all copies or substantial portions of the Software.
  37  *
  38  *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
  39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
  43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45  *     OTHER DEALINGS IN THE SOFTWARE.
  46  */
  47
  48 #include "skeleton.dtsi"
  49 #include <dt-bindings/interrupt-controller/arm-gic.h>
  50 #include <dt-bindings/interrupt-controller/irq.h>
  51 #include <dt-bindings/phy/phy.h>
  52
  53 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
  54
  55 / {
  56         model = "Marvell Armada 375 family SoC";
  57         compatible = "marvell,armada375";
  58
  59         aliases {
  60                 gpio0 = &gpio0;
  61                 gpio1 = &gpio1;
  62                 gpio2 = &gpio2;
  63         };
  64
  65         clocks {
  66                 /* 2 GHz fixed main PLL */
  67                 mainpll: mainpll {
  68                         compatible = "fixed-clock";
  69                         #clock-cells = <0>;
  70                         clock-frequency = <2000000000>;
  71                 };
  72                 /* 25 MHz reference crystal */
  73                 refclk: oscillator {
  74                         compatible = "fixed-clock";
  75                         #clock-cells = <0>;
  76                         clock-frequency = <25000000>;
  77                 };
  78         };
  79
  80         cpus {
  81                 #address-cells = <1>;
  82                 #size-cells = <0>;
  83                 enable-method = "marvell,armada-375-smp";
  84
  85                 cpu@0 {
  86                         device_type = "cpu";
  87                         compatible = "arm,cortex-a9";
  88                         reg = <0>;
  89                 };
  90                 cpu@1 {
  91                         device_type = "cpu";
  92                         compatible = "arm,cortex-a9";
  93                         reg = <1>;
  94                 };
  95         };
  96
  97         soc {
  98                 compatible = "marvell,armada375-mbus", "simple-bus";
  99                 #address-cells = <2>;
 100                 #size-cells = <1>;
 101                 controller = <&mbusc>;
 102                 interrupt-parent = <&gic>;
 103                 pcie-mem-aperture = <0xe0000000 0x8000000>;
 104                 pcie-io-aperture  = <0xe8000000 0x100000>;
 105
 106                 bootrom {
 107                         compatible = "marvell,bootrom";
 108                         reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
 109                 };
 110
 111                 devbus-bootcs {
 112                         compatible = "marvell,mvebu-devbus";
 113                         reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
 114                         ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
 115                         #address-cells = <1>;
 116                         #size-cells = <1>;
 117                         clocks = <&coreclk 0>;
 118                         status = "disabled";
 119                 };
 120
 121                 devbus-cs0 {
 122                         compatible = "marvell,mvebu-devbus";
 123                         reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
 124                         ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
 125                         #address-cells = <1>;
 126                         #size-cells = <1>;
 127                         clocks = <&coreclk 0>;
 128                         status = "disabled";
 129                 };
 130
 131                 devbus-cs1 {
 132                         compatible = "marvell,mvebu-devbus";
 133                         reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
 134                         ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
 135                         #address-cells = <1>;
 136                         #size-cells = <1>;
 137                         clocks = <&coreclk 0>;
 138                         status = "disabled";
 139                 };
 140
 141                 devbus-cs2 {
 142                         compatible = "marvell,mvebu-devbus";
 143                         reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
 144                         ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
 145                         #address-cells = <1>;
 146                         #size-cells = <1>;
 147                         clocks = <&coreclk 0>;
 148                         status = "disabled";
 149                 };
 150
 151                 devbus-cs3 {
 152                         compatible = "marvell,mvebu-devbus";
 153                         reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
 154                         ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
 155                         #address-cells = <1>;
 156                         #size-cells = <1>;
 157                         clocks = <&coreclk 0>;
 158                         status = "disabled";
 159                 };
 160
 161                 internal-regs {
 162                         compatible = "simple-bus";
 163                         #address-cells = <1>;
 164                         #size-cells = <1>;
 165                         ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
 166
 167                         L2: cache-controller@8000 {
 168                                 compatible = "arm,pl310-cache";
 169                                 reg = <0x8000 0x1000>;
 170                                 cache-unified;
 171                                 cache-level = <2>;
 172                         };
 173
 174                         scu@c000 {
 175                                 compatible = "arm,cortex-a9-scu";
 176                                 reg = <0xc000 0x58>;
 177                         };
 178
 179                         timer@c600 {
 180                                 compatible = "arm,cortex-a9-twd-timer";
 181                                 reg = <0xc600 0x20>;
 182                                 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
 183                                 clocks = <&coreclk 2>;
 184                         };
 185
 186                         gic: interrupt-controller@d000 {
 187                                 compatible = "arm,cortex-a9-gic";
 188                                 #interrupt-cells = <3>;
 189                                 #size-cells = <0>;
 190                                 interrupt-controller;
 191                                 reg = <0xd000 0x1000>,
 192                                       <0xc100 0x100>;
 193                         };
 194
 195                         mdio {
 196                                 #address-cells = <1>;
 197                                 #size-cells = <0>;
 198                                 compatible = "marvell,orion-mdio";
 199                                 reg = <0xc0054 0x4>;
 200                                 clocks = <&gateclk 19>;
 201                         };
 202
 203                         /* Network controller */
 204                         ethernet@f0000 {
 205                                 compatible = "marvell,armada-375-pp2";
 206                                 reg = <0xf0000 0xa000>, /* Packet Processor regs */
 207                                       <0xc0000 0x3060>, /* LMS regs */
 208                                       <0xc4000 0x100>,  /* eth0 regs */
 209                                       <0xc5000 0x100>;  /* eth1 regs */
 210                                 clocks = <&gateclk 3>, <&gateclk 19>;
 211                                 clock-names = "pp_clk", "gop_clk";
 212                                 status = "disabled";
 213
 214                                 eth0: eth0@c4000 {
 215                                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 216                                         port-id = <0>;
 217                                         status = "disabled";
 218                                 };
 219
 220                                 eth1: eth1@c5000 {
 221                                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 222                                         port-id = <1>;
 223                                         status = "disabled";
 224                                 };
 225                         };
 226
 227                         rtc@10300 {
 228                                 compatible = "marvell,orion-rtc";
 229                                 reg = <0x10300 0x20>;
 230                                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 231                         };
 232
 233                         spi0: spi@10600 {
 234                                 compatible = "marvell,orion-spi";
 235                                 reg = <0x10600 0x50>;
 236                                 #address-cells = <1>;
 237                                 #size-cells = <0>;
 238                                 cell-index = <0>;
 239                                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 240                                 clocks = <&coreclk 0>;
 241                                 status = "disabled";
 242                         };
 243
 244                         spi1: spi@10680 {
 245                                 compatible = "marvell,orion-spi";
 246                                 reg = <0x10680 0x50>;
 247                                 #address-cells = <1>;
 248                                 #size-cells = <0>;
 249                                 cell-index = <1>;
 250                                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 251                                 clocks = <&coreclk 0>;
 252                                 status = "disabled";
 253                         };
 254
 255                         i2c0: i2c@11000 {
 256                                 compatible = "marvell,mv64xxx-i2c";
 257                                 reg = <0x11000 0x20>;
 258                                 #address-cells = <1>;
 259                                 #size-cells = <0>;
 260                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 261                                 timeout-ms = <1000>;
 262                                 clocks = <&coreclk 0>;
 263                                 status = "disabled";
 264                         };
 265
 266                         i2c1: i2c@11100 {
 267                                 compatible = "marvell,mv64xxx-i2c";
 268                                 reg = <0x11100 0x20>;
 269                                 #address-cells = <1>;
 270                                 #size-cells = <0>;
 271                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 272                                 timeout-ms = <1000>;
 273                                 clocks = <&coreclk 0>;
 274                                 status = "disabled";
 275                         };
 276
 277                         uart0: serial@12000 {
 278                                 compatible = "snps,dw-apb-uart";
 279                                 reg = <0x12000 0x100>;
 280                                 reg-shift = <2>;
 281                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 282                                 reg-io-width = <1>;
 283                                 clocks = <&coreclk 0>;
 284                                 status = "disabled";
 285                         };
 286
 287                         uart1: serial@12100 {
 288                                 compatible = "snps,dw-apb-uart";
 289                                 reg = <0x12100 0x100>;
 290                                 reg-shift = <2>;
 291                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 292                                 reg-io-width = <1>;
 293                                 clocks = <&coreclk 0>;
 294                                 status = "disabled";
 295                         };
 296
 297                         pinctrl {
 298                                 compatible = "marvell,mv88f6720-pinctrl";
 299                                 reg = <0x18000 0x24>;
 300
 301                                 i2c0_pins: i2c0-pins {
 302                                         marvell,pins = "mpp14",  "mpp15";
 303                                         marvell,function = "i2c0";
 304                                 };
 305
 306                                 i2c1_pins: i2c1-pins {
 307                                         marvell,pins = "mpp61",  "mpp62";
 308                                         marvell,function = "i2c1";
 309                                 };
 310
 311                                 nand_pins: nand-pins {
 312                                         marvell,pins = "mpp0", "mpp1", "mpp2",
 313                                                 "mpp3", "mpp4", "mpp5",
 314                                                 "mpp6", "mpp7", "mpp8",
 315                                                 "mpp9", "mpp10", "mpp11",
 316                                                 "mpp12", "mpp13";
 317                                         marvell,function = "nand";
 318                                 };
 319
 320                                 sdio_pins: sdio-pins {
 321                                         marvell,pins = "mpp24",  "mpp25", "mpp26",
 322                                                      "mpp27", "mpp28", "mpp29";
 323                                         marvell,function = "sd";
 324                                 };
 325
 326                                 spi0_pins: spi0-pins {
 327                                         marvell,pins = "mpp0",  "mpp1", "mpp4",
 328                                                      "mpp5", "mpp8", "mpp9";
 329                                         marvell,function = "spi0";
 330                                 };
 331                         };
 332
 333                         gpio0: gpio@18100 {
 334                                 compatible = "marvell,orion-gpio";
 335                                 reg = <0x18100 0x40>;
 336                                 ngpios = <32>;
 337                                 gpio-controller;
 338                                 #gpio-cells = <2>;
 339                                 interrupt-controller;
 340                                 #interrupt-cells = <2>;
 341                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 342                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 343                                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 344                                              <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 345                         };
 346
 347                         gpio1: gpio@18140 {
 348                                 compatible = "marvell,orion-gpio";
 349                                 reg = <0x18140 0x40>;
 350                                 ngpios = <32>;
 351                                 gpio-controller;
 352                                 #gpio-cells = <2>;
 353                                 interrupt-controller;
 354                                 #interrupt-cells = <2>;
 355                                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 356                                              <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 357                                              <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 358                                              <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 359                         };
 360
 361                         gpio2: gpio@18180 {
 362                                 compatible = "marvell,orion-gpio";
 363                                 reg = <0x18180 0x40>;
 364                                 ngpios = <3>;
 365                                 gpio-controller;
 366                                 #gpio-cells = <2>;
 367                                 interrupt-controller;
 368                                 #interrupt-cells = <2>;
 369                                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 370                         };
 371
 372                         system-controller@18200 {
 373                                 compatible = "marvell,armada-375-system-controller";
 374                                 reg = <0x18200 0x100>;
 375                         };
 376
 377                         gateclk: clock-gating-control@18220 {
 378                                 compatible = "marvell,armada-375-gating-clock";
 379                                 reg = <0x18220 0x4>;
 380                                 clocks = <&coreclk 0>;
 381                                 #clock-cells = <1>;
 382                         };
 383
 384                         usbcluster: usb-cluster@18400 {
 385                                 compatible = "marvell,armada-375-usb-cluster";
 386                                 reg = <0x18400 0x4>;
 387                                 #phy-cells = <1>;
 388                         };
 389
 390                         mbusc: mbus-controller@20000 {
 391                                 compatible = "marvell,mbus-controller";
 392                                 reg = <0x20000 0x100>, <0x20180 0x20>;
 393                         };
 394
 395                         mpic: interrupt-controller@20000 {
 396                                 compatible = "marvell,mpic";
 397                                 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
 398                                 #interrupt-cells = <1>;
 399                                 #size-cells = <1>;
 400                                 interrupt-controller;
 401                                 msi-controller;
 402                                 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
 403                         };
 404
 405                         timer@20300 {
 406                                 compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
 407                                 reg = <0x20300 0x30>, <0x21040 0x30>;
 408                                 interrupts-extended = <&gic  GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
 409                                                       <&gic  GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
 410                                                       <&gic  GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
 411                                                       <&gic  GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 412                                                       <&mpic 5>,
 413                                                       <&mpic 6>;
 414                                 clocks = <&coreclk 0>, <&refclk>;
 415                                 clock-names = "nbclk", "fixed";
 416                         };
 417
 418                         watchdog@20300 {
 419                                 compatible = "marvell,armada-375-wdt";
 420                                 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
 421                                 clocks = <&coreclk 0>, <&refclk>;
 422                                 clock-names = "nbclk", "fixed";
 423                         };
 424
 425                         cpurst@20800 {
 426                                 compatible = "marvell,armada-370-cpu-reset";
 427                                 reg = <0x20800 0x10>;
 428                         };
 429
 430                         coherency-fabric@21010 {
 431                                 compatible = "marvell,armada-375-coherency-fabric";
 432                                 reg = <0x21010 0x1c>;
 433                         };
 434
 435                         usb@50000 {
 436                                 compatible = "marvell,orion-ehci";
 437                                 reg = <0x50000 0x500>;
 438                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 439                                 clocks = <&gateclk 18>;
 440                                 phys = <&usbcluster PHY_TYPE_USB2>;
 441                                 phy-names = "usb";
 442                                 status = "disabled";
 443                         };
 444
 445                         usb@54000 {
 446                                 compatible = "marvell,orion-ehci";
 447                                 reg = <0x54000 0x500>;
 448                                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 449                                 clocks = <&gateclk 26>;
 450                                 status = "disabled";
 451                         };
 452
 453                         usb3@58000 {
 454                                 compatible = "marvell,armada-375-xhci";
 455                                 reg = <0x58000 0x20000>,<0x5b880 0x80>;
 456                                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 457                                 clocks = <&gateclk 16>;
 458                                 phys = <&usbcluster PHY_TYPE_USB3>;
 459                                 phy-names = "usb";
 460                                 status = "disabled";
 461                         };
 462
 463                         xor@60800 {
 464                                 compatible = "marvell,orion-xor";
 465                                 reg = <0x60800 0x100
 466                                        0x60A00 0x100>;
 467                                 clocks = <&gateclk 22>;
 468                                 status = "okay";
 469
 470                                 xor00 {
 471                                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 472                                         dmacap,memcpy;
 473                                         dmacap,xor;
 474                                 };
 475                                 xor01 {
 476                                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 477                                         dmacap,memcpy;
 478                                         dmacap,xor;
 479                                         dmacap,memset;
 480                                 };
 481                         };
 482
 483                         xor@60900 {
 484                                 compatible = "marvell,orion-xor";
 485                                 reg = <0x60900 0x100
 486                                        0x60b00 0x100>;
 487                                 clocks = <&gateclk 23>;
 488                                 status = "okay";
 489
 490                                 xor10 {
 491                                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 492                                         dmacap,memcpy;
 493                                         dmacap,xor;
 494                                 };
 495                                 xor11 {
 496                                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 497                                         dmacap,memcpy;
 498                                         dmacap,xor;
 499                                         dmacap,memset;
 500                                 };
 501                         };
 502
 503                         sata@a0000 {
 504                                 compatible = "marvell,orion-sata";
 505                                 reg = <0xa0000 0x5000>;
 506                                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 507                                 clocks = <&gateclk 14>, <&gateclk 20>;
 508                                 clock-names = "0", "1";
 509                                 status = "disabled";
 510                         };
 511
 512                         nand@d0000 {
 513                                 compatible = "marvell,armada370-nand";
 514                                 reg = <0xd0000 0x54>;
 515                                 #address-cells = <1>;
 516                                 #size-cells = <1>;
 517                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 518                                 clocks = <&gateclk 11>;
 519                                 status = "disabled";
 520                         };
 521
 522                         mvsdio@d4000 {
 523                                 compatible = "marvell,orion-sdio";
 524                                 reg = <0xd4000 0x200>;
 525                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 526                                 clocks = <&gateclk 17>;
 527                                 bus-width = <4>;
 528                                 cap-sdio-irq;
 529                                 cap-sd-highspeed;
 530                                 cap-mmc-highspeed;
 531                                 status = "disabled";
 532                         };
 533
 534                         thermal@e8078 {
 535                                 compatible = "marvell,armada375-thermal";
 536                                 reg = <0xe8078 0x4>, <0xe807c 0x8>;
 537                                 status = "okay";
 538                         };
 539
 540                         coreclk: mvebu-sar@e8204 {
 541                                 compatible = "marvell,armada-375-core-clock";
 542                                 reg = <0xe8204 0x04>;
 543                                 #clock-cells = <1>;
 544                         };
 545
 546                         coredivclk: corediv-clock@e8250 {
 547                                 compatible = "marvell,armada-375-corediv-clock";
 548                                 reg = <0xe8250 0xc>;
 549                                 #clock-cells = <1>;
 550                                 clocks = <&mainpll>;
 551                                 clock-output-names = "nand";
 552                         };
 553                 };
 554
 555                 pcie-controller {
 556                         compatible = "marvell,armada-370-pcie";
 557                         status = "disabled";
 558                         device_type = "pci";
 559
 560                         #address-cells = <3>;
 561                         #size-cells = <2>;
 562
 563                         msi-parent = <&mpic>;
 564                         bus-range = <0x00 0xff>;
 565
 566                         ranges =
 567                                <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
 568                                 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
 569                                 0x82000000 0x1 0       MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */
 570                                 0x81000000 0x1 0       MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO  */
 571                                 0x82000000 0x2 0       MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
 572                                 0x81000000 0x2 0       MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO  */>;
 573
 574                         pcie@1,0 {
 575                                 device_type = "pci";
 576                                 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
 577                                 reg = <0x0800 0 0 0 0>;
 578                                 #address-cells = <3>;
 579                                 #size-cells = <2>;
 580                                 #interrupt-cells = <1>;
 581                                 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
 582                                           0x81000000 0 0 0x81000000 0x1 0 1 0>;
 583                                 interrupt-map-mask = <0 0 0 0>;
 584                                 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 585                                 marvell,pcie-port = <0>;
 586                                 marvell,pcie-lane = <0>;
 587                                 clocks = <&gateclk 5>;
 588                                 status = "disabled";
 589                         };
 590
 591                         pcie@2,0 {
 592                                 device_type = "pci";
 593                                 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
 594                                 reg = <0x1000 0 0 0 0>;
 595                                 #address-cells = <3>;
 596                                 #size-cells = <2>;
 597                                 #interrupt-cells = <1>;
 598                                 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
 599                                           0x81000000 0 0 0x81000000 0x2 0 1 0>;
 600                                 interrupt-map-mask = <0 0 0 0>;
 601                                 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 602                                 marvell,pcie-port = <0>;
 603                                 marvell,pcie-lane = <1>;
 604                                 clocks = <&gateclk 6>;
 605                                 status = "disabled";
 606                         };
 607
 608                 };
 609         };
 610 };