2 * Device Tree Include file for Marvell Armada 375 family SoC
4 * Copyright (C) 2014 Marvell
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include "skeleton.dtsi"
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/interrupt-controller/irq.h>
18 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
21 model = "Marvell Armada 375 family SoC";
22 compatible = "marvell,armada375";
33 /* 2 GHz fixed main PLL */
35 compatible = "fixed-clock";
37 clock-frequency = <2000000000>;
44 enable-method = "marvell,armada-375-smp";
48 compatible = "arm,cortex-a9";
53 compatible = "arm,cortex-a9";
59 compatible = "marvell,armada375-mbus", "marvell,armada370-mbus", "simple-bus";
62 controller = <&mbusc>;
63 interrupt-parent = <&gic>;
64 pcie-mem-aperture = <0xe0000000 0x8000000>;
65 pcie-io-aperture = <0xe8000000 0x100000>;
68 compatible = "marvell,bootrom";
69 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
73 compatible = "marvell,mvebu-devbus";
74 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
75 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
78 clocks = <&coreclk 0>;
83 compatible = "marvell,mvebu-devbus";
84 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
85 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
88 clocks = <&coreclk 0>;
93 compatible = "marvell,mvebu-devbus";
94 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
95 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
98 clocks = <&coreclk 0>;
103 compatible = "marvell,mvebu-devbus";
104 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
105 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
106 #address-cells = <1>;
108 clocks = <&coreclk 0>;
113 compatible = "marvell,mvebu-devbus";
114 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
115 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
116 #address-cells = <1>;
118 clocks = <&coreclk 0>;
123 compatible = "simple-bus";
124 #address-cells = <1>;
126 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
128 L2: cache-controller@8000 {
129 compatible = "arm,pl310-cache";
130 reg = <0x8000 0x1000>;
136 compatible = "arm,cortex-a9-scu";
141 compatible = "arm,cortex-a9-twd-timer";
143 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
144 clocks = <&coreclk 2>;
147 gic: interrupt-controller@d000 {
148 compatible = "arm,cortex-a9-gic";
149 #interrupt-cells = <3>;
151 interrupt-controller;
152 reg = <0xd000 0x1000>,
157 #address-cells = <1>;
159 compatible = "marvell,orion-mdio";
161 clocks = <&gateclk 19>;
164 /* Network controller */
166 compatible = "marvell,armada-375-pp2";
167 reg = <0xf0000 0xa000>, /* Packet Processor regs */
168 <0xc0000 0x3060>, /* LMS regs */
169 <0xc4000 0x100>, /* eth0 regs */
170 <0xc5000 0x100>; /* eth1 regs */
171 clocks = <&gateclk 3>, <&gateclk 19>;
172 clock-names = "pp_clk", "gop_clk";
176 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
182 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
189 compatible = "marvell,orion-rtc";
190 reg = <0x10300 0x20>;
191 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
195 compatible = "marvell,orion-spi";
196 reg = <0x10600 0x50>;
197 #address-cells = <1>;
200 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
201 clocks = <&coreclk 0>;
206 compatible = "marvell,orion-spi";
207 reg = <0x10680 0x50>;
208 #address-cells = <1>;
211 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
212 clocks = <&coreclk 0>;
217 compatible = "marvell,mv64xxx-i2c";
218 reg = <0x11000 0x20>;
219 #address-cells = <1>;
221 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&coreclk 0>;
228 compatible = "marvell,mv64xxx-i2c";
229 reg = <0x11100 0x20>;
230 #address-cells = <1>;
232 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&coreclk 0>;
239 compatible = "snps,dw-apb-uart";
240 reg = <0x12000 0x100>;
242 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&coreclk 0>;
249 compatible = "snps,dw-apb-uart";
250 reg = <0x12100 0x100>;
252 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&coreclk 0>;
259 compatible = "marvell,mv88f6720-pinctrl";
260 reg = <0x18000 0x24>;
262 i2c0_pins: i2c0-pins {
263 marvell,pins = "mpp14", "mpp15";
264 marvell,function = "i2c0";
267 i2c1_pins: i2c1-pins {
268 marvell,pins = "mpp61", "mpp62";
269 marvell,function = "i2c1";
272 nand_pins: nand-pins {
273 marvell,pins = "mpp0", "mpp1", "mpp2",
274 "mpp3", "mpp4", "mpp5",
275 "mpp6", "mpp7", "mpp8",
276 "mpp9", "mpp10", "mpp11",
278 marvell,function = "nand";
281 sdio_pins: sdio-pins {
282 marvell,pins = "mpp24", "mpp25", "mpp26",
283 "mpp27", "mpp28", "mpp29";
284 marvell,function = "sd";
287 spi0_pins: spi0-pins {
288 marvell,pins = "mpp0", "mpp1", "mpp4",
289 "mpp5", "mpp8", "mpp9";
290 marvell,function = "spi0";
295 compatible = "marvell,orion-gpio";
296 reg = <0x18100 0x40>;
300 interrupt-controller;
301 #interrupt-cells = <2>;
302 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
309 compatible = "marvell,orion-gpio";
310 reg = <0x18140 0x40>;
314 interrupt-controller;
315 #interrupt-cells = <2>;
316 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
317 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
318 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
319 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
323 compatible = "marvell,orion-gpio";
324 reg = <0x18180 0x40>;
328 interrupt-controller;
329 #interrupt-cells = <2>;
330 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
333 system-controller@18200 {
334 compatible = "marvell,armada-375-system-controller";
335 reg = <0x18200 0x100>;
338 gateclk: clock-gating-control@18220 {
339 compatible = "marvell,armada-375-gating-clock";
341 clocks = <&coreclk 0>;
345 mbusc: mbus-controller@20000 {
346 compatible = "marvell,mbus-controller";
347 reg = <0x20000 0x100>, <0x20180 0x20>;
350 mpic: interrupt-controller@20000 {
351 compatible = "marvell,mpic";
352 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
353 #interrupt-cells = <1>;
355 interrupt-controller;
357 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
361 compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
362 reg = <0x20300 0x30>, <0x21040 0x30>;
363 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
364 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
365 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
366 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
369 clocks = <&coreclk 0>;
373 compatible = "marvell,armada-375-wdt";
374 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
375 clocks = <&coreclk 0>;
379 compatible = "marvell,armada-370-cpu-reset";
380 reg = <0x20800 0x10>;
383 coherency-fabric@21010 {
384 compatible = "marvell,armada-375-coherency-fabric";
385 reg = <0x21010 0x1c>;
389 compatible = "marvell,orion-ehci";
390 reg = <0x50000 0x500>;
391 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
392 clocks = <&gateclk 18>;
397 compatible = "marvell,orion-ehci";
398 reg = <0x54000 0x500>;
399 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
400 clocks = <&gateclk 26>;
405 compatible = "marvell,armada-375-xhci";
406 reg = <0x58000 0x20000>,<0x5b880 0x80>;
407 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&gateclk 16>;
413 compatible = "marvell,orion-xor";
416 clocks = <&gateclk 22>;
420 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
425 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
433 compatible = "marvell,orion-xor";
436 clocks = <&gateclk 23>;
440 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
445 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
453 compatible = "marvell,orion-sata";
454 reg = <0xa0000 0x5000>;
455 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
456 clocks = <&gateclk 14>, <&gateclk 20>;
457 clock-names = "0", "1";
462 compatible = "marvell,armada370-nand";
463 reg = <0xd0000 0x54>;
464 #address-cells = <1>;
466 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
467 clocks = <&gateclk 11>;
472 compatible = "marvell,orion-sdio";
473 reg = <0xd4000 0x200>;
474 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
475 clocks = <&gateclk 17>;
484 compatible = "marvell,armada375-thermal";
485 reg = <0xe8078 0x4>, <0xe807c 0x8>;
489 coreclk: mvebu-sar@e8204 {
490 compatible = "marvell,armada-375-core-clock";
491 reg = <0xe8204 0x04>;
495 coredivclk: corediv-clock@e8250 {
496 compatible = "marvell,armada-375-corediv-clock";
500 clock-output-names = "nand";
505 compatible = "marvell,armada-370-pcie";
509 #address-cells = <3>;
512 msi-parent = <&mpic>;
513 bus-range = <0x00 0xff>;
516 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
517 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
518 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */
519 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO */
520 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
521 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>;
525 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
526 reg = <0x0800 0 0 0 0>;
527 #address-cells = <3>;
529 #interrupt-cells = <1>;
530 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
531 0x81000000 0 0 0x81000000 0x1 0 1 0>;
532 interrupt-map-mask = <0 0 0 0>;
533 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
534 marvell,pcie-port = <0>;
535 marvell,pcie-lane = <0>;
536 clocks = <&gateclk 5>;
542 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
543 reg = <0x1000 0 0 0 0>;
544 #address-cells = <3>;
546 #interrupt-cells = <1>;
547 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
548 0x81000000 0 0 0x81000000 0x2 0 1 0>;
549 interrupt-map-mask = <0 0 0 0>;
550 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
551 marvell,pcie-port = <0>;
552 marvell,pcie-lane = <1>;
553 clocks = <&gateclk 6>;