2 * Device Tree file for SolidRun Clearfog revision A1 rev 2.0 (88F6828)
4 * Copyright (C) 2015 Russell King
6 * This board is in development; the contents of this file work with
7 * the A1 rev 2.0 of the board, which does not represent final
8 * production board. Things will change, don't expect this file to
9 * remain compatible info the future.
11 * This file is dual-licensed: you can use it either under the terms
12 * of the GPL or the X11 license, at your option. Note that this dual
13 * licensing only applies to this file, and not this project as a
16 * a) This file is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License
18 * version 2 as published by the Free Software Foundation.
20 * This file is distributed in the hope that it will be useful
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
27 * b) Permission is hereby granted, free of charge, to any person
28 * obtaining a copy of this software and associated documentation
29 * files (the "Software"), to deal in the Software without
30 * restriction, including without limitation the rights to use
31 * copy, modify, merge, publish, distribute, sublicense, and/or
32 * sell copies of the Software, and to permit persons to whom the
33 * Software is furnished to do so, subject to the following
36 * The above copyright notice and this permission notice shall be
37 * included in all copies or substantial portions of the Software.
39 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 * OTHER DEALINGS IN THE SOFTWARE.
50 #include "armada-388.dtsi"
51 #include "armada-38x-solidrun-microsom.dtsi"
54 model = "SolidRun Clearfog A1";
55 compatible = "solidrun,clearfog-a1", "marvell,armada388",
56 "marvell,armada385", "marvell,armada380";
59 /* So that mvebu u-boot can update the MAC addresses */
66 stdout-path = "serial0:115200n8";
69 reg_3p3v: regulator-3p3v {
70 compatible = "regulator-fixed";
71 regulator-name = "3P3V";
72 regulator-min-microvolt = <3300000>;
73 regulator-max-microvolt = <3300000>;
81 buffer-manager = <&bm>;
94 buffer-manager = <&bm>;
106 /* Is there anything on this? */
107 clock-frequency = <100000>;
108 pinctrl-0 = <&i2c0_pins>;
109 pinctrl-names = "default";
113 * PCA9655 GPIO expander, up to 1MHz clock.
131 expander0: gpio-expander@20 {
133 * This is how it should be:
134 * compatible = "onnn,pca9655",
136 * but you can't do this because of
139 compatible = "nxp,pca9555";
146 gpios = <0 GPIO_ACTIVE_LOW>;
148 line-name = "pcie1.0-clkreq";
152 gpios = <3 GPIO_ACTIVE_LOW>;
154 line-name = "pcie1.0-w-disable";
158 gpios = <4 GPIO_ACTIVE_LOW>;
160 line-name = "pcie2.0-clkreq";
164 gpios = <7 GPIO_ACTIVE_LOW>;
166 line-name = "pcie2.0-w-disable";
170 gpios = <5 GPIO_ACTIVE_LOW>;
172 line-name = "usb3-current-limit";
176 gpios = <6 GPIO_ACTIVE_HIGH>;
178 line-name = "usb3-power";
182 gpios = <11 GPIO_ACTIVE_HIGH>;
184 line-name = "m.2 devslp";
187 /* SFP loss of signal */
189 gpios = <12 GPIO_ACTIVE_HIGH>;
191 line-name = "sfp-los";
194 /* SFP laser fault */
196 gpios = <13 GPIO_ACTIVE_HIGH>;
198 line-name = "sfp-tx-fault";
201 /* SFP transmit disable */
203 gpios = <14 GPIO_ACTIVE_HIGH>;
205 line-name = "sfp-tx-disable";
208 /* SFP module present */
210 gpios = <15 GPIO_ACTIVE_LOW>;
212 line-name = "sfp-mod-def0";
216 /* The MCP3021 is 100kHz clock only */
217 mikrobus_adc: mcp3021@4c {
218 compatible = "microchip,mcp3021";
222 /* Also something at 0x64 */
227 * Routed to SFP, mikrobus, and PCIe.
228 * SFP limits this to 100kHz, and requires
229 * an AT24C01A/02/04 with address pins tied
230 * low, which takes addresses 0x50 and 0x51.
231 * Mikrobus doesn't specify beyond an I2C
233 * PCIe uses ARP to assign addresses, or
236 clock-frequency = <100000>;
237 pinctrl-0 = <&clearfog_i2c1_pins>;
238 pinctrl-names = "default";
243 pinctrl-0 = <&mdio_pins>;
244 pinctrl-names = "default";
246 phy_dedicated: ethernet-phy@0 {
248 * Annoyingly, the marvell phy driver
249 * configures the LED register, rather
250 * than preserving reset-loaded setting.
251 * We undo that rubbish here.
253 marvell,reg-init = <3 16 0 0x101e>;
259 clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
260 marvell,pins = "mpp46";
261 marvell,function = "ref";
263 clearfog_dsa0_pins: clearfog-dsa0-pins {
264 marvell,pins = "mpp23", "mpp41";
265 marvell,function = "gpio";
267 clearfog_i2c1_pins: i2c1-pins {
268 /* SFP, PCIe, mSATA, mikrobus */
269 marvell,pins = "mpp26", "mpp27";
270 marvell,function = "i2c1";
272 clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
273 marvell,pins = "mpp20";
274 marvell,function = "gpio";
276 clearfog_sdhci_pins: clearfog-sdhci-pins {
277 marvell,pins = "mpp21", "mpp28",
280 marvell,function = "sd0";
282 clearfog_spi1_cs_pins: spi1-cs-pins {
283 marvell,pins = "mpp55";
284 marvell,function = "spi1";
286 mikro_pins: mikro-pins {
287 /* int: mpp22 rst: mpp29 */
288 marvell,pins = "mpp22", "mpp29";
289 marvell,function = "gpio";
291 mikro_spi_pins: mikro-spi-pins {
292 marvell,pins = "mpp43";
293 marvell,function = "spi1";
295 mikro_uart_pins: mikro-uart-pins {
296 marvell,pins = "mpp24", "mpp25";
297 marvell,function = "ua1";
299 rear_button_pins: rear-button-pins {
300 marvell,pins = "mpp34";
301 marvell,function = "gpio";
317 cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
319 pinctrl-0 = <&clearfog_sdhci_pins
320 &clearfog_sdhci_cd_pins>;
321 pinctrl-names = "default";
329 pinctrl-0 = <&mikro_uart_pins>;
330 pinctrl-names = "default";
336 * We don't seem to have the W25Q32 on the
337 * A1 Rev 2.0 boards, so disable SPI.
338 * CS0: W25Q32 (doesn't appear to be present)
342 pinctrl-0 = <&spi1_pins
343 &clearfog_spi1_cs_pins
345 pinctrl-names = "default";
349 #address-cells = <1>;
351 compatible = "w25q32", "jedec,spi-nor";
352 reg = <0>; /* Chip select 0 */
353 spi-max-frequency = <3000000>;
359 /* CON3, nearest power. */
364 /* CON2, nearest CPU, USB2 only. */
377 * The two PCIe units are accessible through
378 * the mini-PCIe connectors on the board.
381 /* Port 1, Lane 0. CON3, nearest power. */
382 reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
386 /* Port 2, Lane 0. CON2, nearest CPU. */
387 reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
394 compatible = "marvell,dsa";
395 dsa,ethernet = <ð1>;
396 dsa,mii-bus = <&mdio>;
397 pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
398 pinctrl-names = "default";
399 #address-cells = <2>;
403 #address-cells = <1>;
438 /* 88E1512 external phy */
450 compatible = "gpio-keys";
451 pinctrl-0 = <&rear_button_pins>;
452 pinctrl-names = "default";
455 /* The rear SW3 button */
456 label = "Rear Button";
457 gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
459 linux,code = <BTN_0>;