2 * Device Tree Include file for Marvell Armada 39x family of SoCs.
4 * Copyright (C) 2015 Marvell
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPL or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
13 * a) This file is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
18 * This file is distributed in the hope that it will be useful
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
37 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
47 #include "skeleton.dtsi"
48 #include <dt-bindings/interrupt-controller/arm-gic.h>
49 #include <dt-bindings/interrupt-controller/irq.h>
51 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
54 model = "Marvell Armada 39x family SoC";
55 compatible = "marvell,armada390";
67 enable-method = "marvell,armada-390-smp";
71 compatible = "arm,cortex-a9";
76 compatible = "arm,cortex-a9";
82 compatible = "arm,cortex-a9-pmu";
83 interrupts-extended = <&mpic 3>;
87 compatible = "marvell,armada390-mbus", "marvell,armadaxp-mbus",
91 controller = <&mbusc>;
92 interrupt-parent = <&gic>;
93 pcie-mem-aperture = <0xe0000000 0x8000000>;
94 pcie-io-aperture = <0xe8000000 0x100000>;
97 compatible = "marvell,bootrom";
98 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
102 compatible = "simple-bus";
103 #address-cells = <1>;
105 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
107 L2: cache-controller@8000 {
108 compatible = "arm,pl310-cache";
109 reg = <0x8000 0x1000>;
112 arm,double-linefill-incr = <1>;
113 arm,double-linefill-wrap = <0>;
114 arm,double-linefill = <1>;
119 compatible = "arm,cortex-a9-scu";
120 reg = <0xc000 0x100>;
124 compatible = "arm,cortex-a9-twd-timer";
126 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
127 clocks = <&coreclk 2>;
130 gic: interrupt-controller@d000 {
131 compatible = "arm,cortex-a9-gic";
132 #interrupt-cells = <3>;
134 interrupt-controller;
135 reg = <0xd000 0x1000>,
140 compatible = "marvell,mv64xxx-i2c";
141 reg = <0x11000 0x20>;
142 #address-cells = <1>;
144 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
146 clocks = <&coreclk 0>;
151 compatible = "marvell,mv64xxx-i2c";
152 reg = <0x11100 0x20>;
153 #address-cells = <1>;
155 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
157 clocks = <&coreclk 0>;
162 compatible = "marvell,mv64xxx-i2c";
163 reg = <0x11200 0x20>;
164 #address-cells = <1>;
166 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
168 clocks = <&coreclk 0>;
173 compatible = "marvell,mv64xxx-i2c";
174 reg = <0x11300 0x20>;
175 #address-cells = <1>;
177 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
179 clocks = <&coreclk 0>;
183 uart0: serial@12000 {
184 compatible = "snps,dw-apb-uart";
185 reg = <0x12000 0x100>;
187 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
189 clocks = <&coreclk 0>;
193 uart1: serial@12100 {
194 compatible = "snps,dw-apb-uart";
195 reg = <0x12100 0x100>;
197 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
199 clocks = <&coreclk 0>;
203 uart2: serial@12200 {
204 compatible = "snps,dw-apb-uart";
205 reg = <0x12200 0x100>;
207 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
209 clocks = <&coreclk 0>;
213 uart3: serial@12300 {
214 compatible = "snps,dw-apb-uart";
215 reg = <0x12300 0x100>;
217 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&coreclk 0>;
224 i2c0_pins: i2c0-pins {
225 marvell,pins = "mpp2", "mpp3";
226 marvell,function = "i2c0";
229 uart0_pins: uart0-pins {
230 marvell,pins = "mpp0", "mpp1";
231 marvell,function = "ua0";
234 uart1_pins: uart1-pins {
235 marvell,pins = "mpp19", "mpp20";
236 marvell,function = "ua1";
239 spi1_pins: spi1-pins {
240 marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59";
241 marvell,function = "spi1";
244 nand_pins: nand-pins {
245 marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33",
246 "mpp38", "mpp28", "mpp40", "mpp42",
247 "mpp35", "mpp36", "mpp25", "mpp30",
249 marvell,function = "dev";
253 system-controller@18200 {
254 compatible = "marvell,armada-390-system-controller",
255 "marvell,armada-370-xp-system-controller";
256 reg = <0x18200 0x100>;
259 gateclk: clock-gating-control@18220 {
260 compatible = "marvell,armada-390-gating-clock";
262 clocks = <&coreclk 0>;
266 coreclk: mvebu-sar@18600 {
267 compatible = "marvell,armada-390-core-clock";
268 reg = <0x18600 0x04>;
272 mbusc: mbus-controller@20000 {
273 compatible = "marvell,mbus-controller";
274 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
277 mpic: interrupt-controller@20a00 {
278 compatible = "marvell,mpic";
279 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
280 #interrupt-cells = <1>;
282 interrupt-controller;
284 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
288 compatible = "marvell,armada-380-timer",
289 "marvell,armada-xp-timer";
290 reg = <0x20300 0x30>, <0x21040 0x30>;
291 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
292 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
293 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
294 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
297 clocks = <&coreclk 2>, <&coreclk 5>;
298 clock-names = "nbclk", "fixed";
302 compatible = "marvell,armada-380-wdt";
303 reg = <0x20300 0x34>, <0x20704 0x4>,
305 clocks = <&coreclk 2>, <&refclk>;
306 clock-names = "nbclk", "fixed";
310 compatible = "marvell,armada-370-cpu-reset";
311 reg = <0x20800 0x10>;
314 mpcore-soc-ctrl@20d20 {
315 compatible = "marvell,armada-380-mpcore-soc-ctrl";
316 reg = <0x20d20 0x6c>;
319 coherency-fabric@21010 {
320 compatible = "marvell,armada-380-coherency-fabric";
321 reg = <0x21010 0x1c>;
325 compatible = "marvell,armada-390-pmsu",
326 "marvell,armada-380-pmsu";
327 reg = <0x22000 0x1000>;
331 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
334 clocks = <&gateclk 22>;
338 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
343 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
351 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
354 clocks = <&gateclk 28>;
358 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
363 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
371 compatible = "marvell,armada370-nand";
372 reg = <0xd0000 0x54>;
373 #address-cells = <1>;
375 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
376 clocks = <&coredivclk 0>;
381 compatible = "marvell,armada-380-sdhci";
382 reg-names = "sdhci", "mbus", "conf-sdio3";
383 reg = <0xd8000 0x1000>,
386 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&gateclk 17>;
388 mrvl,clk-delay-cycles = <0x1F>;
392 coredivclk: clock@e4250 {
393 compatible = "marvell,armada-390-corediv-clock",
394 "marvell,armada-380-corediv-clock";
398 clock-output-names = "nand";
402 compatible = "marvell,armada380-thermal";
403 reg = <0xe4078 0x4>, <0xe4074 0x4>;
409 compatible = "marvell,armada-370-pcie";
413 #address-cells = <3>;
416 msi-parent = <&mpic>;
417 bus-range = <0x00 0xff>;
420 <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
421 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
422 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
423 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
424 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
425 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
426 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
427 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
428 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
429 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */
430 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
431 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>;
434 * This port can be either x4 or x1. When
435 * configured in x4 by the bootloader, then
436 * pcie@4,0 is not available.
440 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
441 reg = <0x0800 0 0 0 0>;
442 #address-cells = <3>;
444 #interrupt-cells = <1>;
445 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
446 0x81000000 0 0 0x81000000 0x1 0 1 0>;
447 interrupt-map-mask = <0 0 0 0>;
448 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
449 marvell,pcie-port = <0>;
450 marvell,pcie-lane = <0>;
451 clocks = <&gateclk 8>;
458 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
459 reg = <0x1000 0 0 0 0>;
460 #address-cells = <3>;
462 #interrupt-cells = <1>;
463 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
464 0x81000000 0 0 0x81000000 0x2 0 1 0>;
465 interrupt-map-mask = <0 0 0 0>;
466 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
467 marvell,pcie-port = <1>;
468 marvell,pcie-lane = <0>;
469 clocks = <&gateclk 5>;
476 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
477 reg = <0x1800 0 0 0 0>;
478 #address-cells = <3>;
480 #interrupt-cells = <1>;
481 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
482 0x81000000 0 0 0x81000000 0x3 0 1 0>;
483 interrupt-map-mask = <0 0 0 0>;
484 interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
485 marvell,pcie-port = <2>;
486 marvell,pcie-lane = <0>;
487 clocks = <&gateclk 6>;
492 * x1 port only available when pcie@1,0 is
493 * configured as a x1 port
497 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
498 reg = <0x2000 0 0 0 0>;
499 #address-cells = <3>;
501 #interrupt-cells = <1>;
502 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
503 0x81000000 0 0 0x81000000 0x4 0 1 0>;
504 interrupt-map-mask = <0 0 0 0>;
505 interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
506 marvell,pcie-port = <3>;
507 marvell,pcie-lane = <0>;
508 clocks = <&gateclk 7>;
514 compatible = "marvell,armada-390-spi",
516 reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>;
517 #address-cells = <1>;
520 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&coreclk 0>;
526 compatible = "marvell,armada-390-spi",
528 reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>;
529 #address-cells = <1>;
532 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
533 clocks = <&coreclk 0>;
539 /* 2 GHz fixed main PLL */
541 compatible = "fixed-clock";
543 clock-frequency = <1000000000>;
546 /* 25 MHz reference crystal */
548 compatible = "fixed-clock";
550 clock-frequency = <25000000>;