arch/arm/boot/dts/armada-xp-mv78460.dtsi

   1 /*
   2  * Device Tree Include file for Marvell Armada XP family SoC
   3  *
   4  * Copyright (C) 2012 Marvell
   5  *
   6  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   7  *
   8  * This file is licensed under the terms of the GNU General Public
   9  * License version 2.  This program is licensed "as is" without any
  10  * warranty of any kind, whether express or implied.
  11  *
  12  * Contains definitions specific to the Armada XP MV78460 SoC that are not
  13  * common to all Armada XP SoCs.
  14  */
  15
  16 /include/ "armada-xp.dtsi"
  17
  18 / {
  19         model = "Marvell Armada XP MV78460 SoC";
  20         compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
  21
  22         aliases {
  23                 gpio0 = &gpio0;
  24                 gpio1 = &gpio1;
  25                 gpio2 = &gpio2;
  26         };
  27
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 cpu@0 {
  34                         device_type = "cpu";
  35                         compatible = "marvell,sheeva-v7";
  36                         reg = <0>;
  37                         clocks = <&cpuclk 0>;
  38                 };
  39
  40                 cpu@1 {
  41                         device_type = "cpu";
  42                         compatible = "marvell,sheeva-v7";
  43                         reg = <1>;
  44                         clocks = <&cpuclk 1>;
  45                 };
  46
  47                 cpu@2 {
  48                         device_type = "cpu";
  49                         compatible = "marvell,sheeva-v7";
  50                         reg = <2>;
  51                         clocks = <&cpuclk 2>;
  52                 };
  53
  54                 cpu@3 {
  55                         device_type = "cpu";
  56                         compatible = "marvell,sheeva-v7";
  57                         reg = <3>;
  58                         clocks = <&cpuclk 3>;
  59                 };
  60         };
  61
  62         soc {
  63                 pinctrl {
  64                         compatible = "marvell,mv78460-pinctrl";
  65                         reg = <0x18000 0x38>;
  66
  67                         sdio_pins: sdio-pins {
  68                                 marvell,pins = "mpp30", "mpp31", "mpp32",
  69                                                "mpp33", "mpp34", "mpp35";
  70                                 marvell,function = "sd0";
  71                         };
  72                 };
  73
  74                 gpio0: gpio@18100 {
  75                         compatible = "marvell,orion-gpio";
  76                         reg = <0x18100 0x40>;
  77                         ngpios = <32>;
  78                         gpio-controller;
  79                         #gpio-cells = <2>;
  80                         interrupt-controller;
  81                         #interrupts-cells = <2>;
  82                         interrupts = <82>, <83>, <84>, <85>;
  83                 };
  84
  85                 gpio1: gpio@18140 {
  86                         compatible = "marvell,orion-gpio";
  87                         reg = <0x18140 0x40>;
  88                         ngpios = <32>;
  89                         gpio-controller;
  90                         #gpio-cells = <2>;
  91                         interrupt-controller;
  92                         #interrupts-cells = <2>;
  93                         interrupts = <87>, <88>, <89>, <90>;
  94                 };
  95
  96                 gpio2: gpio@18180 {
  97                         compatible = "marvell,orion-gpio";
  98                         reg = <0x18180 0x40>;
  99                         ngpios = <3>;
 100                         gpio-controller;
 101                         #gpio-cells = <2>;
 102                         interrupt-controller;
 103                         #interrupts-cells = <2>;
 104                         interrupts = <91>;
 105                 };
 106
 107                 ethernet@34000 {
 108                                 compatible = "marvell,armada-370-neta";
 109                                 reg = <0x34000 0x2500>;
 110                                 interrupts = <14>;
 111                                 clocks = <&gateclk 1>;
 112                                 status = "disabled";
 113                 };
 114
 115                 /*
 116                  * MV78460 has 4 PCIe units Gen2.0: Two units can be
 117                  * configured as x4 or quad x1 lanes. Two units are
 118                  * x4/x1.
 119                  */
 120                 pcie-controller {
 121                         compatible = "marvell,armada-xp-pcie";
 122                         status = "disabled";
 123                         device_type = "pci";
 124
 125                         #address-cells = <3>;
 126                         #size-cells = <2>;
 127
 128                         bus-range = <0x00 0xff>;
 129
 130                         ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000   /* Port 0.0 registers */
 131                                   0x82000000 0 0x42000 0x42000 0 0x00002000   /* Port 2.0 registers */
 132                                   0x82000000 0 0x44000 0x44000 0 0x00002000   /* Port 0.1 registers */
 133                                   0x82000000 0 0x48000 0x48000 0 0x00002000   /* Port 0.2 registers */
 134                                   0x82000000 0 0x4c000 0x4c000 0 0x00002000   /* Port 0.3 registers */
 135                                   0x82000000 0 0x80000 0x80000 0 0x00002000   /* Port 1.0 registers */
 136                                   0x82000000 0 0x82000 0x82000 0 0x00002000   /* Port 3.0 registers */
 137                                   0x82000000 0 0x84000 0x84000 0 0x00002000   /* Port 1.1 registers */
 138                                   0x82000000 0 0x88000 0x88000 0 0x00002000   /* Port 1.2 registers */
 139                                   0x82000000 0 0x8c000 0x8c000 0 0x00002000   /* Port 1.3 registers */
 140                                   0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
 141                                   0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */
 142
 143                         pcie@1,0 {
 144                                 device_type = "pci";
 145                                 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
 146                                 reg = <0x0800 0 0 0 0>;
 147                                 #address-cells = <3>;
 148                                 #size-cells = <2>;
 149                                 #interrupt-cells = <1>;
 150                                 ranges;
 151                                 interrupt-map-mask = <0 0 0 0>;
 152                                 interrupt-map = <0 0 0 0 &mpic 58>;
 153                                 marvell,pcie-port = <0>;
 154                                 marvell,pcie-lane = <0>;
 155                                 clocks = <&gateclk 5>;
 156                                 status = "disabled";
 157                         };
 158
 159                         pcie@2,0 {
 160                                 device_type = "pci";
 161                                 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
 162                                 reg = <0x1000 0 0 0 0>;
 163                                 #address-cells = <3>;
 164                                 #size-cells = <2>;
 165                                 #interrupt-cells = <1>;
 166                                 ranges;
 167                                 interrupt-map-mask = <0 0 0 0>;
 168                                 interrupt-map = <0 0 0 0 &mpic 59>;
 169                                 marvell,pcie-port = <0>;
 170                                 marvell,pcie-lane = <1>;
 171                                 clocks = <&gateclk 6>;
 172                                 status = "disabled";
 173                         };
 174
 175                         pcie@3,0 {
 176                                 device_type = "pci";
 177                                 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
 178                                 reg = <0x1800 0 0 0 0>;
 179                                 #address-cells = <3>;
 180                                 #size-cells = <2>;
 181                                 #interrupt-cells = <1>;
 182                                 ranges;
 183                                 interrupt-map-mask = <0 0 0 0>;
 184                                 interrupt-map = <0 0 0 0 &mpic 60>;
 185                                 marvell,pcie-port = <0>;
 186                                 marvell,pcie-lane = <2>;
 187                                 clocks = <&gateclk 7>;
 188                                 status = "disabled";
 189                         };
 190
 191                         pcie@4,0 {
 192                                 device_type = "pci";
 193                                 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
 194                                 reg = <0x2000 0 0 0 0>;
 195                                 #address-cells = <3>;
 196                                 #size-cells = <2>;
 197                                 #interrupt-cells = <1>;
 198                                 ranges;
 199                                 interrupt-map-mask = <0 0 0 0>;
 200                                 interrupt-map = <0 0 0 0 &mpic 61>;
 201                                 marvell,pcie-port = <0>;
 202                                 marvell,pcie-lane = <3>;
 203                                 clocks = <&gateclk 8>;
 204                                 status = "disabled";
 205                         };
 206
 207                         pcie@5,0 {
 208                                 device_type = "pci";
 209                                 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
 210                                 reg = <0x2800 0 0 0 0>;
 211                                 #address-cells = <3>;
 212                                 #size-cells = <2>;
 213                                 #interrupt-cells = <1>;
 214                                 ranges;
 215                                 interrupt-map-mask = <0 0 0 0>;
 216                                 interrupt-map = <0 0 0 0 &mpic 62>;
 217                                 marvell,pcie-port = <1>;
 218                                 marvell,pcie-lane = <0>;
 219                                 clocks = <&gateclk 9>;
 220                                 status = "disabled";
 221                         };
 222
 223                         pcie@6,0 {
 224                                 device_type = "pci";
 225                                 assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
 226                                 reg = <0x3000 0 0 0 0>;
 227                                 #address-cells = <3>;
 228                                 #size-cells = <2>;
 229                                 #interrupt-cells = <1>;
 230                                 ranges;
 231                                 interrupt-map-mask = <0 0 0 0>;
 232                                 interrupt-map = <0 0 0 0 &mpic 63>;
 233                                 marvell,pcie-port = <1>;
 234                                 marvell,pcie-lane = <1>;
 235                                 clocks = <&gateclk 10>;
 236                                 status = "disabled";
 237                         };
 238
 239                         pcie@7,0 {
 240                                 device_type = "pci";
 241                                 assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
 242                                 reg = <0x3800 0 0 0 0>;
 243                                 #address-cells = <3>;
 244                                 #size-cells = <2>;
 245                                 #interrupt-cells = <1>;
 246                                 ranges;
 247                                 interrupt-map-mask = <0 0 0 0>;
 248                                 interrupt-map = <0 0 0 0 &mpic 64>;
 249                                 marvell,pcie-port = <1>;
 250                                 marvell,pcie-lane = <2>;
 251                                 clocks = <&gateclk 11>;
 252                                 status = "disabled";
 253                         };
 254
 255                         pcie@8,0 {
 256                                 device_type = "pci";
 257                                 assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
 258                                 reg = <0x4000 0 0 0 0>;
 259                                 #address-cells = <3>;
 260                                 #size-cells = <2>;
 261                                 #interrupt-cells = <1>;
 262                                 ranges;
 263                                 interrupt-map-mask = <0 0 0 0>;
 264                                 interrupt-map = <0 0 0 0 &mpic 65>;
 265                                 marvell,pcie-port = <1>;
 266                                 marvell,pcie-lane = <3>;
 267                                 clocks = <&gateclk 12>;
 268                                 status = "disabled";
 269                         };
 270                         pcie@9,0 {
 271                                 device_type = "pci";
 272                                 assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
 273                                 reg = <0x4800 0 0 0 0>;
 274                                 #address-cells = <3>;
 275                                 #size-cells = <2>;
 276                                 #interrupt-cells = <1>;
 277                                 ranges;
 278                                 interrupt-map-mask = <0 0 0 0>;
 279                                 interrupt-map = <0 0 0 0 &mpic 99>;
 280                                 marvell,pcie-port = <2>;
 281                                 marvell,pcie-lane = <0>;
 282                                 clocks = <&gateclk 26>;
 283                                 status = "disabled";
 284                         };
 285
 286                         pcie@10,0 {
 287                                 device_type = "pci";
 288                                 assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
 289                                 reg = <0x5000 0 0 0 0>;
 290                                 #address-cells = <3>;
 291                                 #size-cells = <2>;
 292                                 #interrupt-cells = <1>;
 293                                 ranges;
 294                                 interrupt-map-mask = <0 0 0 0>;
 295                                 interrupt-map = <0 0 0 0 &mpic 103>;
 296                                 marvell,pcie-port = <3>;
 297                                 marvell,pcie-lane = <0>;
 298                                 clocks = <&gateclk 27>;
 299                                 status = "disabled";
 300                         };
 301                 };
 302         };
 303 };