2 * Device Tree Include file for Marvell Armada XP family SoC
4 * Copyright (C) 2012 Marvell
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
15 * Contains definitions specific to the Armada XP SoC that are not
16 * common to all Armada SoCs.
19 /include/ "armada-370-xp.dtsi"
22 model = "Marvell Armada XP family SoC";
23 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
28 compatible = "marvell,aurora-system-cache";
29 reg = <0x08000 0x1000>;
30 cache-id-part = <0x100>;
34 mpic: interrupt-controller@20000 {
35 reg = <0x20a00 0x2d0>,
39 armada-370-xp-pmsu@22000 {
40 compatible = "marvell,armada-370-xp-pmsu";
41 reg = <0x22100 0x430>,
46 compatible = "snps,dw-apb-uart";
47 reg = <0x12200 0x100>;
54 compatible = "snps,dw-apb-uart";
55 reg = <0x12300 0x100>;
66 coreclk: mvebu-sar@18230 {
67 compatible = "marvell,armada-xp-core-clock";
72 cpuclk: clock-complex@18700 {
74 compatible = "marvell,armada-xp-cpu-clock";
76 clocks = <&coreclk 1>;
79 gateclk: clock-gating-control@18220 {
80 compatible = "marvell,armada-xp-gating-clock";
82 clocks = <&coreclk 0>;
86 system-controller@18200 {
87 compatible = "marvell,armada-370-xp-system-controller";
88 reg = <0x18200 0x500>;
92 compatible = "marvell,armada-370-neta";
93 reg = <0x30000 0x2500>;
95 clocks = <&gateclk 2>;
100 compatible = "marvell,orion-xor";
103 clocks = <&gateclk 22>;
120 compatible = "marvell,orion-xor";
123 clocks = <&gateclk 28>;
140 clocks = <&gateclk 18>;
144 clocks = <&gateclk 19>;
148 compatible = "marvell,orion-ehci";
149 reg = <0x52000 0x500>;
151 clocks = <&gateclk 20>;
156 compatible = "marvell,armadaxp-thermal";