2 * Device Tree Include file for Marvell Armada XP family SoC
4 * Copyright (C) 2012 Marvell
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
15 * Contains definitions specific to the Armada XP SoC that are not
16 * common to all Armada SoCs.
19 #include "armada-370-xp.dtsi"
22 model = "Marvell Armada XP family SoC";
23 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
30 compatible = "marvell,armadaxp-mbus", "simple-bus";
33 compatible = "marvell,bootrom";
34 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
39 compatible = "marvell,aurora-system-cache";
40 reg = <0x08000 0x1000>;
41 cache-id-part = <0x100>;
46 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
47 reg = <0x11000 0x100>;
51 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
52 reg = <0x11100 0x100>;
56 compatible = "snps,dw-apb-uart";
57 reg = <0x12200 0x100>;
61 clocks = <&coreclk 0>;
65 compatible = "snps,dw-apb-uart";
66 reg = <0x12300 0x100>;
70 clocks = <&coreclk 0>;
74 system-controller@18200 {
75 compatible = "marvell,armada-370-xp-system-controller";
76 reg = <0x18200 0x500>;
79 gateclk: clock-gating-control@18220 {
80 compatible = "marvell,armada-xp-gating-clock";
82 clocks = <&coreclk 0>;
86 coreclk: mvebu-sar@18230 {
87 compatible = "marvell,armada-xp-core-clock";
93 compatible = "marvell,armadaxp-thermal";
99 cpuclk: clock-complex@18700 {
101 compatible = "marvell,armada-xp-cpu-clock";
102 reg = <0x18700 0xA0>, <0x1c054 0x10>;
103 clocks = <&coreclk 1>;
106 interrupt-controller@20000 {
107 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
111 compatible = "marvell,armada-xp-timer";
112 clocks = <&coreclk 2>, <&refclk>;
113 clock-names = "nbclk", "fixed";
117 compatible = "marvell,armada-xp-wdt";
118 clocks = <&coreclk 2>, <&refclk>;
119 clock-names = "nbclk", "fixed";
123 compatible = "marvell,armada-370-cpu-reset";
124 reg = <0x20800 0x20>;
127 eth2: ethernet@30000 {
128 compatible = "marvell,armada-370-neta";
129 reg = <0x30000 0x4000>;
131 clocks = <&gateclk 2>;
136 clocks = <&gateclk 18>;
140 clocks = <&gateclk 19>;
144 compatible = "marvell,orion-ehci";
145 reg = <0x52000 0x500>;
147 clocks = <&gateclk 20>;
152 compatible = "marvell,orion-xor";
155 clocks = <&gateclk 22>;
172 compatible = "marvell,orion-xor";
175 clocks = <&gateclk 28>;
194 /* 25 MHz reference crystal */
196 compatible = "fixed-clock";
198 clock-frequency = <25000000>;