arch/arm/boot/dts/artpec6.dtsi

   1 /*
   2  * Device Tree Source for the Axis ARTPEC-6 SoC
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include "skeleton.dtsi"
  45
  46 / {
  47         compatible = "axis,artpec6";
  48         interrupt-parent = <&intc>;
  49
  50         cpus {
  51                 #address-cells = <1>;
  52                 #size-cells = <0>;
  53
  54                 cpu0: cpu@0 {
  55                         device_type = "cpu";
  56                         compatible = "arm,cortex-a9";
  57                         reg = <0>;
  58                         next-level-cache = <&pl310>;
  59                 };
  60
  61                 cpu1: cpu@1 {
  62                         device_type = "cpu";
  63                         compatible = "arm,cortex-a9";
  64                         reg = <1>;
  65                         next-level-cache = <&pl310>;
  66                 };
  67         };
  68
  69         syscon {
  70                 compatible = "axis,artpec6-syscon", "syscon";
  71                 reg = <0xf8000000 0x48>;
  72         };
  73
  74         psci {
  75                 compatible = "arm,psci-0.2", "arm,psci";
  76                 method = "smc";
  77                 psci_version = <0x84000000>;
  78                 cpu_on = <0x84000003>;
  79                 system_reset = <0x84000009>;
  80         };
  81
  82         scu@faf00000 {
  83                 compatible = "arm,cortex-a9-scu";
  84                 reg = <0xfaf00000 0x58>;
  85         };
  86
  87         /* Main external clock driving CPU and peripherals */
  88         ext_clk: ext_clk {
  89                 #clock-cells = <0>;
  90                 compatible = "fixed-clock";
  91                 clock-frequency = <50000000>;
  92         };
  93
  94         /* PLL1 is used by CPU and some peripherals */
  95         pll1_clk: pll1_clk@f8000000 {
  96                 #clock-cells = <0>;
  97                 compatible = "axis,artpec6-pll1-clock";
  98                 reg = <0xf8000000 4>;
  99                 clocks = <&ext_clk>;
 100         };
 101
 102         cpu_clk: cpu_clk {
 103                 #clock-cells = <0>;
 104                 compatible = "fixed-factor-clock";
 105                 clock-div = <1>;
 106                 clock-mult = <1>;
 107                 clocks = <&pll1_clk>;
 108                 clock-output-names = "cpu_clk";
 109         };
 110
 111         cpu_clkdiv2: cpu_clkdiv2 {
 112                 #clock-cells = <0>;
 113                 compatible = "fixed-factor-clock";
 114                 clock-div = <2>;
 115                 clock-mult = <1>;
 116                 clocks = <&cpu_clk>;
 117         };
 118
 119         cpu_clkdiv4: cpu_clkdiv4 {
 120                 #clock-cells = <0>;
 121                 compatible = "fixed-factor-clock";
 122                 clock-div = <4>;
 123                 clock-mult = <1>;
 124                 clocks = <&cpu_clk>;
 125         };
 126
 127         apb_pclk: apb_pclk {
 128                 #clock-cells = <0>;
 129                 compatible = "fixed-factor-clock";
 130                 clock-div = <8>;
 131                 clock-mult = <1>;
 132                 clocks = <&cpu_clk>;
 133                 clock-output-names = "apb_pclk";
 134         };
 135
 136         /* PLL2 is used by a number of peripherals, including UDL */
 137         pll2: pll2 {
 138                 #clock-cells = <0>;
 139                 compatible = "fixed-factor-clock";
 140                 clock-div = <1>;
 141                 clock-mult = <24>;
 142                 clocks = <&ext_clk>;
 143         };
 144
 145         /* PLL2DIV2 is used by the Fractional Clock Divider, for i2s */
 146         pll2div2: pll2div2 {
 147                 #clock-cells = <0>;
 148                 compatible = "fixed-factor-clock";
 149                 clock-div = <2>;
 150                 clock-mult = <1>;
 151                 clocks = <&pll2>;
 152         };
 153
 154         pll2div12: pll2div12 {
 155                 #clock-cells = <0>;
 156                 compatible = "fixed-factor-clock";
 157                 clock-div = <12>;
 158                 clock-mult = <1>;
 159                 clocks = <&pll2>;
 160         };
 161
 162         pll2div24: pll2div24 {
 163                 #clock-cells = <0>;
 164                 compatible = "fixed-factor-clock";
 165                 clock-div = <24>;
 166                 clock-mult = <1>;
 167                 clocks = <&pll2>;
 168                 clock-output-names = "uart_clk";
 169         };
 170
 171
 172         gtimer@faf00200 {
 173                 compatible = "arm,cortex-a9-global-timer";
 174                 reg = <0xfaf00200 0x20>;
 175                 interrupts = <GIC_PPI 11 0xf01>;
 176                 clocks = <&cpu_clkdiv2>;
 177         };
 178
 179         timer@faf00600 {
 180                 compatible = "arm,cortex-a9-twd-timer";
 181                 reg = <0xfaf00600 0x20>;
 182                 interrupts = <GIC_PPI 13 0xf04>;
 183                 clocks = <&cpu_clkdiv2>;
 184                 status = "disabled";
 185         };
 186
 187         intc: interrupt-controller@faf01000 {
 188                 interrupt-controller;
 189                 compatible = "arm,cortex-a9-gic";
 190                 #interrupt-cells = <3>;
 191                 reg = < 0xfaf01000 0x1000 >, < 0xfaf00100 0x0100 >;
 192         };
 193
 194         pl310: cache-controller@faf10000 {
 195                 compatible = "arm,pl310-cache";
 196                 cache-unified;
 197                 cache-level = <2>;
 198                 reg = <0xfaf10000 0x1000>;
 199                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 200                 arm,data-latency = <1 1 1>;
 201                 arm,tag-latency = <1 1 1>;
 202                 arm,filter-ranges = <0x0 0x80000000>;
 203         };
 204
 205         pmu {
 206                 compatible = "arm,cortex-a9-pmu";
 207                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 208                         <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 209                 interrupt-parent = <&intc>;
 210         };
 211
 212         amba@0 {
 213                 compatible = "simple-bus";
 214                 #address-cells = <0x1>;
 215                 #size-cells = <0x1>;
 216                 interrupt-parent = <&intc>;
 217                 ranges;
 218                 dma-ranges = <0x80000000 0x00000000 0x40000000>;
 219                 dma-coherent;
 220
 221                 ethernet: ethernet@f8010000 {
 222                         clock-names = "phy_ref_clk", "apb_pclk";
 223                         clocks = <&ext_clk>, <&apb_pclk>;
 224                         compatible = "snps,dwc-qos-ethernet-4.10";
 225                         interrupt-parent = <&intc>;
 226                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 227                         reg = <0xf8010000 0x4000>;
 228
 229                         snps,write-requests = <2>;
 230                         snps,read-requests = <16>;
 231                         snps,txpbl = <8>;
 232                         snps,rxpbl = <2>;
 233
 234                         status = "disabled";
 235                 };
 236
 237                 uart0: serial@f8036000 {
 238                         compatible = "arm,pl011", "arm,primecell";
 239                         reg = <0xf8036000 0x1000>;
 240                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 241                         clocks = <&pll2div24>, <&apb_pclk>;
 242                         clock-names = "uart_clk", "apb_pclk";
 243                         status = "disabled";
 244                 };
 245                 uart1: serial@f8037000 {
 246                         compatible = "arm,pl011", "arm,primecell";
 247                         reg = <0xf8037000 0x1000>;
 248                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 249                         clocks = <&pll2div24>, <&apb_pclk>;
 250                         clock-names = "uart_clk", "apb_pclk";
 251                         status = "disabled";
 252                 };
 253                 uart2: serial@f8038000 {
 254                         compatible = "arm,pl011", "arm,primecell";
 255                         reg = <0xf8038000 0x1000>;
 256                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 257                         clocks = <&pll2div24>, <&apb_pclk>;
 258                         clock-names = "uart_clk", "apb_pclk";
 259                         status = "disabled";
 260                 };
 261                 uart3: serial@f8039000 {
 262                         compatible = "arm,pl011", "arm,primecell";
 263                         reg = <0xf8039000 0x1000>;
 264                         interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
 265                         clocks = <&pll2div24>, <&apb_pclk>;
 266                         clock-names = "uart_clk", "apb_pclk";
 267                         status = "disabled";
 268                 };
 269         };
 270 };