2 * DTS file for CSR SiRFatlas6 SoC
4 * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
6 * Licensed under GPLv2 or later.
9 /include/ "skeleton.dtsi"
11 compatible = "sirf,atlas6";
14 interrupt-parent = <&intc>;
22 d-cache-line-size = <32>;
23 i-cache-line-size = <32>;
24 d-cache-size = <32768>;
25 i-cache-size = <32768>;
27 timebase-frequency = <0>;
29 clock-frequency = <0>;
34 compatible = "simple-bus";
37 ranges = <0x40000000 0x40000000 0x80000000>;
39 intc: interrupt-controller@80020000 {
40 #interrupt-cells = <1>;
42 compatible = "sirf,prima2-intc";
43 reg = <0x80020000 0x1000>;
47 compatible = "simple-bus";
50 ranges = <0x88000000 0x88000000 0x40000>;
52 clks: clock-controller@88000000 {
53 compatible = "sirf,atlas6-clkc";
54 reg = <0x88000000 0x1000>;
59 reset-controller@88010000 {
60 compatible = "sirf,prima2-rstc";
61 reg = <0x88010000 0x1000>;
64 rsc-controller@88020000 {
65 compatible = "sirf,prima2-rsc";
66 reg = <0x88020000 0x1000>;
71 compatible = "simple-bus";
74 ranges = <0x90000000 0x90000000 0x10000>;
76 memory-controller@90000000 {
77 compatible = "sirf,prima2-memc";
78 reg = <0x90000000 0x10000>;
85 compatible = "simple-bus";
88 ranges = <0x90010000 0x90010000 0x30000>;
91 compatible = "sirf,prima2-lcd";
92 reg = <0x90010000 0x20000>;
96 /* later transfer to pwm */
97 bl-gpio = <&gpio 7 0>;
98 default-panel = <&panel0>;
102 compatible = "sirf,prima2-vpp";
103 reg = <0x90020000 0x10000>;
110 compatible = "simple-bus";
111 #address-cells = <1>;
113 ranges = <0x98000000 0x98000000 0x8000000>;
116 compatible = "powervr,sgx510";
117 reg = <0x98000000 0x8000000>;
124 compatible = "simple-bus";
125 #address-cells = <1>;
127 ranges = <0xa8000000 0xa8000000 0x2000000>;
130 compatible = "sirf,prima2-dspif";
131 reg = <0xa8000000 0x10000>;
136 compatible = "sirf,prima2-gps";
137 reg = <0xa8010000 0x10000>;
143 compatible = "sirf,prima2-dsp";
144 reg = <0xa9000000 0x1000000>;
151 compatible = "simple-bus";
152 #address-cells = <1>;
154 ranges = <0xb0000000 0xb0000000 0x180000>,
155 <0x56000000 0x56000000 0x1b00000>;
158 compatible = "sirf,prima2-tick";
159 reg = <0xb0020000 0x1000>;
164 compatible = "sirf,prima2-nand";
165 reg = <0xb0030000 0x10000>;
171 compatible = "sirf,prima2-audio";
172 reg = <0xb0040000 0x10000>;
177 uart0: uart@b0050000 {
179 compatible = "sirf,prima2-uart";
180 reg = <0xb0050000 0x1000>;
184 sirf,uart-dma-rx-channel = <21>;
185 sirf,uart-dma-tx-channel = <2>;
188 uart1: uart@b0060000 {
190 compatible = "sirf,prima2-uart";
191 reg = <0xb0060000 0x1000>;
197 uart2: uart@b0070000 {
199 compatible = "sirf,prima2-uart";
200 reg = <0xb0070000 0x1000>;
204 sirf,uart-dma-rx-channel = <6>;
205 sirf,uart-dma-tx-channel = <7>;
210 compatible = "sirf,prima2-usp";
211 reg = <0xb0080000 0x10000>;
215 sirf,usp-dma-rx-channel = <17>;
216 sirf,usp-dma-tx-channel = <18>;
221 compatible = "sirf,prima2-usp";
222 reg = <0xb0090000 0x10000>;
226 sirf,usp-dma-rx-channel = <14>;
227 sirf,usp-dma-tx-channel = <15>;
230 dmac0: dma-controller@b00b0000 {
232 compatible = "sirf,prima2-dmac";
233 reg = <0xb00b0000 0x10000>;
238 dmac1: dma-controller@b0160000 {
240 compatible = "sirf,prima2-dmac";
241 reg = <0xb0160000 0x10000>;
247 compatible = "sirf,prima2-vip";
248 reg = <0xb00C0000 0x10000>;
251 sirf,vip-dma-rx-channel = <16>;
256 compatible = "sirf,prima2-spi";
257 reg = <0xb00d0000 0x10000>;
259 sirf,spi-num-chipselects = <1>;
260 cs-gpios = <&gpio 0 0>;
261 sirf,spi-dma-rx-channel = <25>;
262 sirf,spi-dma-tx-channel = <20>;
263 #address-cells = <1>;
271 compatible = "sirf,prima2-spi";
272 reg = <0xb0170000 0x10000>;
280 compatible = "sirf,prima2-i2c";
281 reg = <0xb00e0000 0x10000>;
283 #address-cells = <1>;
290 compatible = "sirf,prima2-i2c";
291 reg = <0xb00f0000 0x10000>;
293 #address-cells = <1>;
299 compatible = "sirf,prima2-tsc";
300 reg = <0xb0110000 0x10000>;
305 gpio: pinctrl@b0120000 {
307 #interrupt-cells = <2>;
308 compatible = "sirf,atlas6-pinctrl";
309 reg = <0xb0120000 0x10000>;
310 interrupts = <43 44 45 46 47>;
312 interrupt-controller;
314 lcd_16pins_a: lcd0@0 {
316 sirf,pins = "lcd_16bitsgrp";
317 sirf,function = "lcd_16bits";
320 lcd_18pins_a: lcd0@1 {
322 sirf,pins = "lcd_18bitsgrp";
323 sirf,function = "lcd_18bits";
326 lcd_24pins_a: lcd0@2 {
328 sirf,pins = "lcd_24bitsgrp";
329 sirf,function = "lcd_24bits";
332 lcdrom_pins_a: lcdrom0@0 {
334 sirf,pins = "lcdromgrp";
335 sirf,function = "lcdrom";
338 uart0_pins_a: uart0@0 {
340 sirf,pins = "uart0grp";
341 sirf,function = "uart0";
344 uart0_noflow_pins_a: uart0@1 {
346 sirf,pins = "uart0_nostreamctrlgrp";
347 sirf,function = "uart0_nostreamctrl";
350 uart1_pins_a: uart1@0 {
352 sirf,pins = "uart1grp";
353 sirf,function = "uart1";
356 uart2_pins_a: uart2@0 {
358 sirf,pins = "uart2grp";
359 sirf,function = "uart2";
362 uart2_noflow_pins_a: uart2@1 {
364 sirf,pins = "uart2_nostreamctrlgrp";
365 sirf,function = "uart2_nostreamctrl";
368 spi0_pins_a: spi0@0 {
370 sirf,pins = "spi0grp";
371 sirf,function = "spi0";
374 spi1_pins_a: spi1@0 {
376 sirf,pins = "spi1grp";
377 sirf,function = "spi1";
380 i2c0_pins_a: i2c0@0 {
382 sirf,pins = "i2c0grp";
383 sirf,function = "i2c0";
386 i2c1_pins_a: i2c1@0 {
388 sirf,pins = "i2c1grp";
389 sirf,function = "i2c1";
392 pwm0_pins_a: pwm0@0 {
394 sirf,pins = "pwm0grp";
395 sirf,function = "pwm0";
398 pwm1_pins_a: pwm1@0 {
400 sirf,pins = "pwm1grp";
401 sirf,function = "pwm1";
404 pwm2_pins_a: pwm2@0 {
406 sirf,pins = "pwm2grp";
407 sirf,function = "pwm2";
410 pwm3_pins_a: pwm3@0 {
412 sirf,pins = "pwm3grp";
413 sirf,function = "pwm3";
416 pwm4_pins_a: pwm4@0 {
418 sirf,pins = "pwm4grp";
419 sirf,function = "pwm4";
424 sirf,pins = "gpsgrp";
425 sirf,function = "gps";
430 sirf,pins = "vipgrp";
431 sirf,function = "vip";
434 sdmmc0_pins_a: sdmmc0@0 {
436 sirf,pins = "sdmmc0grp";
437 sirf,function = "sdmmc0";
440 sdmmc1_pins_a: sdmmc1@0 {
442 sirf,pins = "sdmmc1grp";
443 sirf,function = "sdmmc1";
446 sdmmc2_pins_a: sdmmc2@0 {
448 sirf,pins = "sdmmc2grp";
449 sirf,function = "sdmmc2";
452 sdmmc2_nowp_pins_a: sdmmc2_nowp@0 {
454 sirf,pins = "sdmmc2_nowpgrp";
455 sirf,function = "sdmmc2_nowp";
458 sdmmc3_pins_a: sdmmc3@0 {
460 sirf,pins = "sdmmc3grp";
461 sirf,function = "sdmmc3";
464 sdmmc5_pins_a: sdmmc5@0 {
466 sirf,pins = "sdmmc5grp";
467 sirf,function = "sdmmc5";
472 sirf,pins = "i2sgrp";
473 sirf,function = "i2s";
476 i2s_no_din_pins_a: i2s_no_din@0 {
478 sirf,pins = "i2s_no_dingrp";
479 sirf,function = "i2s_no_din";
482 i2s_6chn_pins_a: i2s_6chn@0 {
484 sirf,pins = "i2s_6chngrp";
485 sirf,function = "i2s_6chn";
488 ac97_pins_a: ac97@0 {
490 sirf,pins = "ac97grp";
491 sirf,function = "ac97";
494 nand_pins_a: nand@0 {
496 sirf,pins = "nandgrp";
497 sirf,function = "nand";
500 usp0_pins_a: usp0@0 {
502 sirf,pins = "usp0grp";
503 sirf,function = "usp0";
506 usp0_uart_nostreamctrl_pins_a: usp0@1 {
508 sirf,pins = "usp0_uart_nostreamctrl_grp";
509 sirf,function = "usp0_uart_nostreamctrl";
512 usp1_pins_a: usp1@0 {
514 sirf,pins = "usp1grp";
515 sirf,function = "usp1";
518 usb0_upli_drvbus_pins_a: usb0_upli_drvbus@0 {
520 sirf,pins = "usb0_upli_drvbusgrp";
521 sirf,function = "usb0_upli_drvbus";
524 usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 {
526 sirf,pins = "usb1_utmi_drvbusgrp";
527 sirf,function = "usb1_utmi_drvbus";
530 usb1_dp_dn_pins_a: usb1_dp_dn@0 {
532 sirf,pins = "usb1_dp_dngrp";
533 sirf,function = "usb1_dp_dn";
536 uart1_route_io_usb1_pins_a: uart1_route_io_usb1@0 {
537 uart1_route_io_usb1 {
538 sirf,pins = "uart1_route_io_usb1grp";
539 sirf,function = "uart1_route_io_usb1";
542 warm_rst_pins_a: warm_rst@0 {
544 sirf,pins = "warm_rstgrp";
545 sirf,function = "warm_rst";
548 pulse_count_pins_a: pulse_count@0 {
550 sirf,pins = "pulse_countgrp";
551 sirf,function = "pulse_count";
554 cko0_pins_a: cko0@0 {
556 sirf,pins = "cko0grp";
557 sirf,function = "cko0";
560 cko1_pins_a: cko1@0 {
562 sirf,pins = "cko1grp";
563 sirf,function = "cko1";
569 compatible = "sirf,prima2-pwm";
570 reg = <0xb0130000 0x10000>;
575 compatible = "sirf,prima2-efuse";
576 reg = <0xb0140000 0x10000>;
581 compatible = "sirf,prima2-pulsec";
582 reg = <0xb0150000 0x10000>;
588 compatible = "sirf,prima2-pciiobg", "simple-bus";
589 #address-cells = <1>;
591 ranges = <0x56000000 0x56000000 0x1b00000>;
593 sd0: sdhci@56000000 {
595 compatible = "sirf,prima2-sdhc";
596 reg = <0x56000000 0x100000>;
602 sd1: sdhci@56100000 {
604 compatible = "sirf,prima2-sdhc";
605 reg = <0x56100000 0x100000>;
611 sd2: sdhci@56200000 {
613 compatible = "sirf,prima2-sdhc";
614 reg = <0x56200000 0x100000>;
620 sd3: sdhci@56300000 {
622 compatible = "sirf,prima2-sdhc";
623 reg = <0x56300000 0x100000>;
629 sd5: sdhci@56500000 {
631 compatible = "sirf,prima2-sdhc";
632 reg = <0x56500000 0x100000>;
639 compatible = "sirf,prima2-pcicp";
640 reg = <0x57900000 0x100000>;
644 rom-interface@57a00000 {
645 compatible = "sirf,prima2-romif";
646 reg = <0x57a00000 0x100000>;
652 compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus";
653 #address-cells = <1>;
655 reg = <0x80030000 0x10000>;
658 compatible = "sirf,prima2-gpsrtc";
659 reg = <0x1000 0x1000>;
660 interrupts = <55 56 57>;
664 compatible = "sirf,prima2-sysrtc";
665 reg = <0x2000 0x1000>;
666 interrupts = <52 53 54>;
670 compatible = "sirf,prima2-pwrc";
671 reg = <0x3000 0x1000>;
677 compatible = "simple-bus";
678 #address-cells = <1>;
680 ranges = <0xb8000000 0xb8000000 0x40000>;
683 compatible = "chipidea,ci13611a-prima2";
684 reg = <0xb8000000 0x10000>;
690 compatible = "chipidea,ci13611a-prima2";
691 reg = <0xb8010000 0x10000>;
697 compatible = "sirf,prima2-security";
698 reg = <0xb8030000 0x10000>;