arch/arm/boot/dts/atlas6.dtsi

   1 /*
   2  * DTS file for CSR SiRFatlas6 SoC
   3  *
   4  * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8
   9 /include/ "skeleton.dtsi"
  10 / {
  11         compatible = "sirf,atlas6";
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14         interrupt-parent = <&intc>;
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19
  20                 cpu@0 {
  21                         reg = <0x0>;
  22                         d-cache-line-size = <32>;
  23                         i-cache-line-size = <32>;
  24                         d-cache-size = <32768>;
  25                         i-cache-size = <32768>;
  26                         /* from bootloader */
  27                         timebase-frequency = <0>;
  28                         bus-frequency = <0>;
  29                         clock-frequency = <0>;
  30                 };
  31         };
  32
  33         axi {
  34                 compatible = "simple-bus";
  35                 #address-cells = <1>;
  36                 #size-cells = <1>;
  37                 ranges = <0x40000000 0x40000000 0x80000000>;
  38
  39                 intc: interrupt-controller@80020000 {
  40                         #interrupt-cells = <1>;
  41                         interrupt-controller;
  42                         compatible = "sirf,prima2-intc";
  43                         reg = <0x80020000 0x1000>;
  44                 };
  45
  46                 sys-iobg {
  47                         compatible = "simple-bus";
  48                         #address-cells = <1>;
  49                         #size-cells = <1>;
  50                         ranges = <0x88000000 0x88000000 0x40000>;
  51
  52                         clks: clock-controller@88000000 {
  53                                 compatible = "sirf,atlas6-clkc";
  54                                 reg = <0x88000000 0x1000>;
  55                                 interrupts = <3>;
  56                                 #clock-cells = <1>;
  57                         };
  58
  59                         reset-controller@88010000 {
  60                                 compatible = "sirf,prima2-rstc";
  61                                 reg = <0x88010000 0x1000>;
  62                         };
  63
  64                         rsc-controller@88020000 {
  65                                 compatible = "sirf,prima2-rsc";
  66                                 reg = <0x88020000 0x1000>;
  67                         };
  68                 };
  69
  70                 mem-iobg {
  71                         compatible = "simple-bus";
  72                         #address-cells = <1>;
  73                         #size-cells = <1>;
  74                         ranges = <0x90000000 0x90000000 0x10000>;
  75
  76                         memory-controller@90000000 {
  77                                 compatible = "sirf,prima2-memc";
  78                                 reg = <0x90000000 0x10000>;
  79                                 interrupts = <27>;
  80                                 clocks = <&clks 5>;
  81                         };
  82                 };
  83
  84                 disp-iobg {
  85                         compatible = "simple-bus";
  86                         #address-cells = <1>;
  87                         #size-cells = <1>;
  88                         ranges = <0x90010000 0x90010000 0x30000>;
  89
  90                         lcd@90010000 {
  91                                 compatible = "sirf,prima2-lcd";
  92                                 reg = <0x90010000 0x20000>;
  93                                 interrupts = <30>;
  94                                 clocks = <&clks 34>;
  95                                 display=<&display>;
  96                                 /* later transfer to pwm */
  97                                 bl-gpio = <&gpio 7 0>;
  98                                 default-panel = <&panel0>;
  99                         };
 100
 101                         vpp@90020000 {
 102                                 compatible = "sirf,prima2-vpp";
 103                                 reg = <0x90020000 0x10000>;
 104                                 interrupts = <31>;
 105                                 clocks = <&clks 35>;
 106                         };
 107                 };
 108
 109                 graphics-iobg {
 110                         compatible = "simple-bus";
 111                         #address-cells = <1>;
 112                         #size-cells = <1>;
 113                         ranges = <0x98000000 0x98000000 0x8000000>;
 114
 115                         graphics@98000000 {
 116                                 compatible = "powervr,sgx510";
 117                                 reg = <0x98000000 0x8000000>;
 118                                 interrupts = <6>;
 119                                 clocks = <&clks 32>;
 120                         };
 121                 };
 122
 123                 dsp-iobg {
 124                         compatible = "simple-bus";
 125                         #address-cells = <1>;
 126                         #size-cells = <1>;
 127                         ranges = <0xa8000000 0xa8000000 0x2000000>;
 128
 129                         dspif@a8000000 {
 130                                 compatible = "sirf,prima2-dspif";
 131                                 reg = <0xa8000000 0x10000>;
 132                                 interrupts = <9>;
 133                         };
 134
 135                         gps@a8010000 {
 136                                 compatible = "sirf,prima2-gps";
 137                                 reg = <0xa8010000 0x10000>;
 138                                 interrupts = <7>;
 139                                 clocks = <&clks 9>;
 140                         };
 141
 142                         dsp@a9000000 {
 143                                 compatible = "sirf,prima2-dsp";
 144                                 reg = <0xa9000000 0x1000000>;
 145                                 interrupts = <8>;
 146                                 clocks = <&clks 8>;
 147                         };
 148                 };
 149
 150                 peri-iobg {
 151                         compatible = "simple-bus";
 152                         #address-cells = <1>;
 153                         #size-cells = <1>;
 154                         ranges = <0xb0000000 0xb0000000 0x180000>,
 155                                <0x56000000 0x56000000 0x1b00000>;
 156
 157                         timer@b0020000 {
 158                                 compatible = "sirf,prima2-tick";
 159                                 reg = <0xb0020000 0x1000>;
 160                                 interrupts = <0>;
 161                         };
 162
 163                         nand@b0030000 {
 164                                 compatible = "sirf,prima2-nand";
 165                                 reg = <0xb0030000 0x10000>;
 166                                 interrupts = <41>;
 167                                 clocks = <&clks 26>;
 168                         };
 169
 170                         audio@b0040000 {
 171                                 compatible = "sirf,prima2-audio";
 172                                 reg = <0xb0040000 0x10000>;
 173                                 interrupts = <35>;
 174                                 clocks = <&clks 27>;
 175                         };
 176
 177                         uart0: uart@b0050000 {
 178                                 cell-index = <0>;
 179                                 compatible = "sirf,prima2-uart";
 180                                 reg = <0xb0050000 0x1000>;
 181                                 interrupts = <17>;
 182                                 fifosize = <128>;
 183                                 clocks = <&clks 13>;
 184                                 sirf,uart-dma-rx-channel = <21>;
 185                                 sirf,uart-dma-tx-channel = <2>;
 186                         };
 187
 188                         uart1: uart@b0060000 {
 189                                 cell-index = <1>;
 190                                 compatible = "sirf,prima2-uart";
 191                                 reg = <0xb0060000 0x1000>;
 192                                 interrupts = <18>;
 193                                 fifosize = <32>;
 194                                 clocks = <&clks 14>;
 195                         };
 196
 197                         uart2: uart@b0070000 {
 198                                 cell-index = <2>;
 199                                 compatible = "sirf,prima2-uart";
 200                                 reg = <0xb0070000 0x1000>;
 201                                 interrupts = <19>;
 202                                 fifosize = <128>;
 203                                 clocks = <&clks 15>;
 204                                 sirf,uart-dma-rx-channel = <6>;
 205                                 sirf,uart-dma-tx-channel = <7>;
 206                         };
 207
 208                         usp0: usp@b0080000 {
 209                                 cell-index = <0>;
 210                                 compatible = "sirf,prima2-usp";
 211                                 reg = <0xb0080000 0x10000>;
 212                                 interrupts = <20>;
 213                                 fifosize = <128>;
 214                                 clocks = <&clks 28>;
 215                                 sirf,usp-dma-rx-channel = <17>;
 216                                 sirf,usp-dma-tx-channel = <18>;
 217                         };
 218
 219                         usp1: usp@b0090000 {
 220                                 cell-index = <1>;
 221                                 compatible = "sirf,prima2-usp";
 222                                 reg = <0xb0090000 0x10000>;
 223                                 interrupts = <21>;
 224                                 fifosize = <128>;
 225                                 clocks = <&clks 29>;
 226                                 sirf,usp-dma-rx-channel = <14>;
 227                                 sirf,usp-dma-tx-channel = <15>;
 228                         };
 229
 230                         dmac0: dma-controller@b00b0000 {
 231                                 cell-index = <0>;
 232                                 compatible = "sirf,prima2-dmac";
 233                                 reg = <0xb00b0000 0x10000>;
 234                                 interrupts = <12>;
 235                                 clocks = <&clks 24>;
 236                         };
 237
 238                         dmac1: dma-controller@b0160000 {
 239                                 cell-index = <1>;
 240                                 compatible = "sirf,prima2-dmac";
 241                                 reg = <0xb0160000 0x10000>;
 242                                 interrupts = <13>;
 243                                 clocks = <&clks 25>;
 244                         };
 245
 246                         vip@b00C0000 {
 247                                 compatible = "sirf,prima2-vip";
 248                                 reg = <0xb00C0000 0x10000>;
 249                                 clocks = <&clks 31>;
 250                         };
 251
 252                         spi0: spi@b00d0000 {
 253                                 cell-index = <0>;
 254                                 compatible = "sirf,prima2-spi";
 255                                 reg = <0xb00d0000 0x10000>;
 256                                 interrupts = <15>;
 257                                 sirf,spi-num-chipselects = <1>;
 258                                 cs-gpios = <&gpio 0 0>;
 259                                 sirf,spi-dma-rx-channel = <25>;
 260                                 sirf,spi-dma-tx-channel = <20>;
 261                                 #address-cells = <1>;
 262                                 #size-cells = <0>;
 263                                 clocks = <&clks 19>;
 264                                 status = "disabled";
 265                         };
 266
 267                         spi1: spi@b0170000 {
 268                                 cell-index = <1>;
 269                                 compatible = "sirf,prima2-spi";
 270                                 reg = <0xb0170000 0x10000>;
 271                                 interrupts = <16>;
 272                                 clocks = <&clks 20>;
 273                                 status = "disabled";
 274                         };
 275
 276                         i2c0: i2c@b00e0000 {
 277                                 cell-index = <0>;
 278                                 compatible = "sirf,prima2-i2c";
 279                                 reg = <0xb00e0000 0x10000>;
 280                                 interrupts = <24>;
 281                                 #address-cells = <1>;
 282                                 #size-cells = <0>;
 283                                 clocks = <&clks 17>;
 284                         };
 285
 286                         i2c1: i2c@b00f0000 {
 287                                 cell-index = <1>;
 288                                 compatible = "sirf,prima2-i2c";
 289                                 reg = <0xb00f0000 0x10000>;
 290                                 interrupts = <25>;
 291                                 #address-cells = <1>;
 292                                 #size-cells = <0>;
 293                                 clocks = <&clks 18>;
 294                         };
 295
 296                         tsc@b0110000 {
 297                                 compatible = "sirf,prima2-tsc";
 298                                 reg = <0xb0110000 0x10000>;
 299                                 interrupts = <33>;
 300                                 clocks = <&clks 16>;
 301                         };
 302
 303                         gpio: pinctrl@b0120000 {
 304                                 #gpio-cells = <2>;
 305                                 #interrupt-cells = <2>;
 306                                 compatible = "sirf,atlas6-pinctrl";
 307                                 reg = <0xb0120000 0x10000>;
 308                                 interrupts = <43 44 45 46 47>;
 309                                 gpio-controller;
 310                                 interrupt-controller;
 311
 312                                 lcd_16pins_a: lcd0@0 {
 313                                         lcd {
 314                                                 sirf,pins = "lcd_16bitsgrp";
 315                                                 sirf,function = "lcd_16bits";
 316                                         };
 317                                 };
 318                                 lcd_18pins_a: lcd0@1 {
 319                                         lcd {
 320                                                 sirf,pins = "lcd_18bitsgrp";
 321                                                 sirf,function = "lcd_18bits";
 322                                         };
 323                                 };
 324                                 lcd_24pins_a: lcd0@2 {
 325                                         lcd {
 326                                                 sirf,pins = "lcd_24bitsgrp";
 327                                                 sirf,function = "lcd_24bits";
 328                                         };
 329                                 };
 330                                 lcdrom_pins_a: lcdrom0@0 {
 331                                         lcd {
 332                                                 sirf,pins = "lcdromgrp";
 333                                                 sirf,function = "lcdrom";
 334                                         };
 335                                 };
 336                                 uart0_pins_a: uart0@0 {
 337                                         uart {
 338                                                 sirf,pins = "uart0grp";
 339                                                 sirf,function = "uart0";
 340                                         };
 341                                 };
 342                                 uart0_noflow_pins_a: uart0@1 {
 343                                         uart {
 344                                                 sirf,pins = "uart0_nostreamctrlgrp";
 345                                                 sirf,function = "uart0_nostreamctrl";
 346                                         };
 347                                 };
 348                                 uart1_pins_a: uart1@0 {
 349                                         uart {
 350                                                 sirf,pins = "uart1grp";
 351                                                 sirf,function = "uart1";
 352                                         };
 353                                 };
 354                                 uart2_pins_a: uart2@0 {
 355                                         uart {
 356                                                 sirf,pins = "uart2grp";
 357                                                 sirf,function = "uart2";
 358                                         };
 359                                 };
 360                                 uart2_noflow_pins_a: uart2@1 {
 361                                         uart {
 362                                                 sirf,pins = "uart2_nostreamctrlgrp";
 363                                                 sirf,function = "uart2_nostreamctrl";
 364                                         };
 365                                 };
 366                                 spi0_pins_a: spi0@0 {
 367                                         spi {
 368                                                 sirf,pins = "spi0grp";
 369                                                 sirf,function = "spi0";
 370                                         };
 371                                 };
 372                                 spi1_pins_a: spi1@0 {
 373                                         spi {
 374                                                 sirf,pins = "spi1grp";
 375                                                 sirf,function = "spi1";
 376                                         };
 377                                 };
 378                                 i2c0_pins_a: i2c0@0 {
 379                                         i2c {
 380                                                 sirf,pins = "i2c0grp";
 381                                                 sirf,function = "i2c0";
 382                                         };
 383                                 };
 384                                 i2c1_pins_a: i2c1@0 {
 385                                         i2c {
 386                                                 sirf,pins = "i2c1grp";
 387                                                 sirf,function = "i2c1";
 388                                         };
 389                                 };
 390                                 pwm0_pins_a: pwm0@0 {
 391                                         pwm {
 392                                                 sirf,pins = "pwm0grp";
 393                                                 sirf,function = "pwm0";
 394                                         };
 395                                 };
 396                                 pwm1_pins_a: pwm1@0 {
 397                                         pwm {
 398                                                 sirf,pins = "pwm1grp";
 399                                                 sirf,function = "pwm1";
 400                                         };
 401                                 };
 402                                 pwm2_pins_a: pwm2@0 {
 403                                         pwm {
 404                                                 sirf,pins = "pwm2grp";
 405                                                 sirf,function = "pwm2";
 406                                         };
 407                                 };
 408                                 pwm3_pins_a: pwm3@0 {
 409                                         pwm {
 410                                                 sirf,pins = "pwm3grp";
 411                                                 sirf,function = "pwm3";
 412                                         };
 413                                 };
 414                                 pwm4_pins_a: pwm4@0 {
 415                                         pwm {
 416                                                 sirf,pins = "pwm4grp";
 417                                                 sirf,function = "pwm4";
 418                                         };
 419                                 };
 420                                 gps_pins_a: gps@0 {
 421                                         gps {
 422                                                 sirf,pins = "gpsgrp";
 423                                                 sirf,function = "gps";
 424                                         };
 425                                 };
 426                                 vip_pins_a: vip@0 {
 427                                         vip {
 428                                                 sirf,pins = "vipgrp";
 429                                                 sirf,function = "vip";
 430                                         };
 431                                 };
 432                                 sdmmc0_pins_a: sdmmc0@0 {
 433                                         sdmmc0 {
 434                                                 sirf,pins = "sdmmc0grp";
 435                                                 sirf,function = "sdmmc0";
 436                                         };
 437                                 };
 438                                 sdmmc1_pins_a: sdmmc1@0 {
 439                                         sdmmc1 {
 440                                                 sirf,pins = "sdmmc1grp";
 441                                                 sirf,function = "sdmmc1";
 442                                         };
 443                                 };
 444                                 sdmmc2_pins_a: sdmmc2@0 {
 445                                         sdmmc2 {
 446                                                 sirf,pins = "sdmmc2grp";
 447                                                 sirf,function = "sdmmc2";
 448                                         };
 449                                 };
 450                                 sdmmc2_nowp_pins_a: sdmmc2_nowp@0 {
 451                                         sdmmc2_nowp {
 452                                                 sirf,pins = "sdmmc2_nowpgrp";
 453                                                 sirf,function = "sdmmc2_nowp";
 454                                         };
 455                                 };
 456                                 sdmmc3_pins_a: sdmmc3@0 {
 457                                         sdmmc3 {
 458                                                 sirf,pins = "sdmmc3grp";
 459                                                 sirf,function = "sdmmc3";
 460                                         };
 461                                 };
 462                                 sdmmc5_pins_a: sdmmc5@0 {
 463                                         sdmmc5 {
 464                                                 sirf,pins = "sdmmc5grp";
 465                                                 sirf,function = "sdmmc5";
 466                                         };
 467                                 };
 468                                 i2s_pins_a: i2s@0 {
 469                                         i2s {
 470                                                 sirf,pins = "i2sgrp";
 471                                                 sirf,function = "i2s";
 472                                         };
 473                                 };
 474                                 i2s_no_din_pins_a: i2s_no_din@0 {
 475                                         i2s_no_din {
 476                                                 sirf,pins = "i2s_no_dingrp";
 477                                                 sirf,function = "i2s_no_din";
 478                                         };
 479                                 };
 480                                 i2s_6chn_pins_a: i2s_6chn@0 {
 481                                         i2s_6chn {
 482                                                 sirf,pins = "i2s_6chngrp";
 483                                                 sirf,function = "i2s_6chn";
 484                                         };
 485                                 };
 486                                 ac97_pins_a: ac97@0 {
 487                                         ac97 {
 488                                                 sirf,pins = "ac97grp";
 489                                                 sirf,function = "ac97";
 490                                         };
 491                                 };
 492                                 nand_pins_a: nand@0 {
 493                                         nand {
 494                                                 sirf,pins = "nandgrp";
 495                                                 sirf,function = "nand";
 496                                         };
 497                                 };
 498                                 usp0_pins_a: usp0@0 {
 499                                         usp0 {
 500                                                 sirf,pins = "usp0grp";
 501                                                 sirf,function = "usp0";
 502                                         };
 503                                 };
 504                                 usp0_uart_nostreamctrl_pins_a: usp0@1 {
 505                                         usp0 {
 506                                                 sirf,pins = "usp0_uart_nostreamctrl_grp";
 507                                                 sirf,function = "usp0_uart_nostreamctrl";
 508                                         };
 509                                 };
 510                                 usp1_pins_a: usp1@0 {
 511                                         usp1 {
 512                                                 sirf,pins = "usp1grp";
 513                                                 sirf,function = "usp1";
 514                                         };
 515                                 };
 516                                 usb0_upli_drvbus_pins_a: usb0_upli_drvbus@0 {
 517                                         usb0_upli_drvbus {
 518                                                 sirf,pins = "usb0_upli_drvbusgrp";
 519                                                 sirf,function = "usb0_upli_drvbus";
 520                                         };
 521                                 };
 522                                 usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 {
 523                                         usb1_utmi_drvbus {
 524                                                 sirf,pins = "usb1_utmi_drvbusgrp";
 525                                                 sirf,function = "usb1_utmi_drvbus";
 526                                         };
 527                                 };
 528                                 warm_rst_pins_a: warm_rst@0 {
 529                                         warm_rst {
 530                                                 sirf,pins = "warm_rstgrp";
 531                                                 sirf,function = "warm_rst";
 532                                         };
 533                                 };
 534                                 pulse_count_pins_a: pulse_count@0 {
 535                                         pulse_count {
 536                                                 sirf,pins = "pulse_countgrp";
 537                                                 sirf,function = "pulse_count";
 538                                         };
 539                                 };
 540                                 cko0_pins_a: cko0@0 {
 541                                         cko0 {
 542                                                 sirf,pins = "cko0grp";
 543                                                 sirf,function = "cko0";
 544                                         };
 545                                 };
 546                                 cko1_pins_a: cko1@0 {
 547                                         cko1 {
 548                                                 sirf,pins = "cko1grp";
 549                                                 sirf,function = "cko1";
 550                                         };
 551                                 };
 552                         };
 553
 554                         pwm@b0130000 {
 555                                 compatible = "sirf,prima2-pwm";
 556                                 reg = <0xb0130000 0x10000>;
 557                                 clocks = <&clks 21>;
 558                         };
 559
 560                         efusesys@b0140000 {
 561                                 compatible = "sirf,prima2-efuse";
 562                                 reg = <0xb0140000 0x10000>;
 563                                 clocks = <&clks 22>;
 564                         };
 565
 566                         pulsec@b0150000 {
 567                                 compatible = "sirf,prima2-pulsec";
 568                                 reg = <0xb0150000 0x10000>;
 569                                 interrupts = <48>;
 570                                 clocks = <&clks 23>;
 571                         };
 572
 573                         pci-iobg {
 574                                 compatible = "sirf,prima2-pciiobg", "simple-bus";
 575                                 #address-cells = <1>;
 576                                 #size-cells = <1>;
 577                                 ranges = <0x56000000 0x56000000 0x1b00000>;
 578
 579                                 sd0: sdhci@56000000 {
 580                                         cell-index = <0>;
 581                                         compatible = "sirf,prima2-sdhc";
 582                                         reg = <0x56000000 0x100000>;
 583                                         interrupts = <38>;
 584                                         bus-width = <8>;
 585                                         clocks = <&clks 36>;
 586                                 };
 587
 588                                 sd1: sdhci@56100000 {
 589                                         cell-index = <1>;
 590                                         compatible = "sirf,prima2-sdhc";
 591                                         reg = <0x56100000 0x100000>;
 592                                         interrupts = <38>;
 593                                         status = "disabled";
 594                                         clocks = <&clks 36>;
 595                                 };
 596
 597                                 sd2: sdhci@56200000 {
 598                                         cell-index = <2>;
 599                                         compatible = "sirf,prima2-sdhc";
 600                                         reg = <0x56200000 0x100000>;
 601                                         interrupts = <23>;
 602                                         status = "disabled";
 603                                         clocks = <&clks 37>;
 604                                 };
 605
 606                                 sd3: sdhci@56300000 {
 607                                         cell-index = <3>;
 608                                         compatible = "sirf,prima2-sdhc";
 609                                         reg = <0x56300000 0x100000>;
 610                                         interrupts = <23>;
 611                                         status = "disabled";
 612                                         clocks = <&clks 37>;
 613                                 };
 614
 615                                 sd5: sdhci@56500000 {
 616                                         cell-index = <5>;
 617                                         compatible = "sirf,prima2-sdhc";
 618                                         reg = <0x56500000 0x100000>;
 619                                         interrupts = <39>;
 620                                         status = "disabled";
 621                                         clocks = <&clks 38>;
 622                                 };
 623
 624                                 pci-copy@57900000 {
 625                                         compatible = "sirf,prima2-pcicp";
 626                                         reg = <0x57900000 0x100000>;
 627                                         interrupts = <40>;
 628                                 };
 629
 630                                 rom-interface@57a00000 {
 631                                         compatible = "sirf,prima2-romif";
 632                                         reg = <0x57a00000 0x100000>;
 633                                 };
 634                         };
 635                 };
 636
 637                 rtc-iobg {
 638                         compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus";
 639                         #address-cells = <1>;
 640                         #size-cells = <1>;
 641                         reg = <0x80030000 0x10000>;
 642
 643                         gpsrtc@1000 {
 644                                 compatible = "sirf,prima2-gpsrtc";
 645                                 reg = <0x1000 0x1000>;
 646                                 interrupts = <55 56 57>;
 647                         };
 648
 649                         sysrtc@2000 {
 650                                 compatible = "sirf,prima2-sysrtc";
 651                                 reg = <0x2000 0x1000>;
 652                                 interrupts = <52 53 54>;
 653                         };
 654
 655                         pwrc@3000 {
 656                                 compatible = "sirf,prima2-pwrc";
 657                                 reg = <0x3000 0x1000>;
 658                                 interrupts = <32>;
 659                         };
 660                 };
 661
 662                 uus-iobg {
 663                         compatible = "simple-bus";
 664                         #address-cells = <1>;
 665                         #size-cells = <1>;
 666                         ranges = <0xb8000000 0xb8000000 0x40000>;
 667
 668                         usb0: usb@b00e0000 {
 669                                 compatible = "chipidea,ci13611a-prima2";
 670                                 reg = <0xb8000000 0x10000>;
 671                                 interrupts = <10>;
 672                                 clocks = <&clks 40>;
 673                         };
 674
 675                         usb1: usb@b00f0000 {
 676                                 compatible = "chipidea,ci13611a-prima2";
 677                                 reg = <0xb8010000 0x10000>;
 678                                 interrupts = <11>;
 679                                 clocks = <&clks 41>;
 680                         };
 681
 682                         security@b00f0000 {
 683                                 compatible = "sirf,prima2-security";
 684                                 reg = <0xb8030000 0x10000>;
 685                                 interrupts = <42>;
 686                                 clocks = <&clks 7>;
 687                         };
 688                 };
 689         };
 690 };