2 * DTS file for CSR SiRFatlas6 SoC
4 * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
6 * Licensed under GPLv2 or later.
9 /include/ "skeleton.dtsi"
11 compatible = "sirf,atlas6";
14 interrupt-parent = <&intc>;
22 d-cache-line-size = <32>;
23 i-cache-line-size = <32>;
24 d-cache-size = <32768>;
25 i-cache-size = <32768>;
27 timebase-frequency = <0>;
29 clock-frequency = <0>;
34 compatible = "simple-bus";
37 ranges = <0x40000000 0x40000000 0x80000000>;
39 intc: interrupt-controller@80020000 {
40 #interrupt-cells = <1>;
42 compatible = "sirf,prima2-intc";
43 reg = <0x80020000 0x1000>;
47 compatible = "simple-bus";
50 ranges = <0x88000000 0x88000000 0x40000>;
52 clks: clock-controller@88000000 {
53 compatible = "sirf,atlas6-clkc";
54 reg = <0x88000000 0x1000>;
59 reset-controller@88010000 {
60 compatible = "sirf,prima2-rstc";
61 reg = <0x88010000 0x1000>;
64 rsc-controller@88020000 {
65 compatible = "sirf,prima2-rsc";
66 reg = <0x88020000 0x1000>;
70 compatible = "sirf,prima2-cphifbg";
71 reg = <0x88030000 0x1000>;
76 compatible = "simple-bus";
79 ranges = <0x90000000 0x90000000 0x10000>;
81 memory-controller@90000000 {
82 compatible = "sirf,prima2-memc";
83 reg = <0x90000000 0x2000>;
89 compatible = "sirf,prima2-memcmon";
90 reg = <0x90002000 0x200>;
97 compatible = "simple-bus";
100 ranges = <0x90010000 0x90010000 0x30000>;
103 compatible = "sirf,prima2-lcd";
104 reg = <0x90010000 0x20000>;
108 /* later transfer to pwm */
109 bl-gpio = <&gpio 7 0>;
110 default-panel = <&panel0>;
114 compatible = "sirf,prima2-vpp";
115 reg = <0x90020000 0x10000>;
122 compatible = "simple-bus";
123 #address-cells = <1>;
125 ranges = <0x98000000 0x98000000 0x8000000>;
128 compatible = "powervr,sgx510";
129 reg = <0x98000000 0x8000000>;
136 compatible = "simple-bus";
137 #address-cells = <1>;
139 ranges = <0xa0000000 0xa0000000 0x8000000>;
142 compatible = "sirf,atlas6-ble";
143 reg = <0xa0000000 0x2000>;
150 compatible = "simple-bus";
151 #address-cells = <1>;
153 ranges = <0xa8000000 0xa8000000 0x2000000>;
156 compatible = "sirf,prima2-dspif";
157 reg = <0xa8000000 0x10000>;
162 compatible = "sirf,prima2-gps";
163 reg = <0xa8010000 0x10000>;
169 compatible = "sirf,prima2-dsp";
170 reg = <0xa9000000 0x1000000>;
177 compatible = "simple-bus";
178 #address-cells = <1>;
180 ranges = <0xb0000000 0xb0000000 0x180000>,
181 <0x56000000 0x56000000 0x1b00000>;
184 compatible = "sirf,prima2-tick";
185 reg = <0xb0020000 0x1000>;
190 compatible = "sirf,prima2-nand";
191 reg = <0xb0030000 0x10000>;
197 compatible = "sirf,prima2-audio";
198 reg = <0xb0040000 0x10000>;
203 uart0: uart@b0050000 {
205 compatible = "sirf,prima2-uart";
206 reg = <0xb0050000 0x1000>;
210 sirf,uart-dma-rx-channel = <21>;
211 sirf,uart-dma-tx-channel = <2>;
214 uart1: uart@b0060000 {
216 compatible = "sirf,prima2-uart";
217 reg = <0xb0060000 0x1000>;
223 uart2: uart@b0070000 {
225 compatible = "sirf,prima2-uart";
226 reg = <0xb0070000 0x1000>;
230 sirf,uart-dma-rx-channel = <6>;
231 sirf,uart-dma-tx-channel = <7>;
236 compatible = "sirf,prima2-usp";
237 reg = <0xb0080000 0x10000>;
241 sirf,usp-dma-rx-channel = <17>;
242 sirf,usp-dma-tx-channel = <18>;
247 compatible = "sirf,prima2-usp";
248 reg = <0xb0090000 0x10000>;
252 sirf,usp-dma-rx-channel = <14>;
253 sirf,usp-dma-tx-channel = <15>;
256 dmac0: dma-controller@b00b0000 {
258 compatible = "sirf,prima2-dmac";
259 reg = <0xb00b0000 0x10000>;
264 dmac1: dma-controller@b0160000 {
266 compatible = "sirf,prima2-dmac";
267 reg = <0xb0160000 0x10000>;
273 compatible = "sirf,prima2-vip";
274 reg = <0xb00C0000 0x10000>;
277 sirf,vip-dma-rx-channel = <16>;
282 compatible = "sirf,prima2-spi";
283 reg = <0xb00d0000 0x10000>;
285 sirf,spi-num-chipselects = <1>;
286 cs-gpios = <&gpio 0 0>;
287 sirf,spi-dma-rx-channel = <25>;
288 sirf,spi-dma-tx-channel = <20>;
289 #address-cells = <1>;
297 compatible = "sirf,prima2-spi";
298 reg = <0xb0170000 0x10000>;
300 sirf,spi-num-chipselects = <1>;
301 sirf,spi-dma-rx-channel = <12>;
302 sirf,spi-dma-tx-channel = <13>;
303 #address-cells = <1>;
311 compatible = "sirf,prima2-i2c";
312 reg = <0xb00e0000 0x10000>;
314 #address-cells = <1>;
321 compatible = "sirf,prima2-i2c";
322 reg = <0xb00f0000 0x10000>;
324 #address-cells = <1>;
330 compatible = "sirf,prima2-tsc";
331 reg = <0xb0110000 0x10000>;
336 gpio: pinctrl@b0120000 {
338 #interrupt-cells = <2>;
339 compatible = "sirf,atlas6-pinctrl";
340 reg = <0xb0120000 0x10000>;
341 interrupts = <43 44 45 46 47>;
343 interrupt-controller;
345 lcd_16pins_a: lcd0@0 {
347 sirf,pins = "lcd_16bitsgrp";
348 sirf,function = "lcd_16bits";
351 lcd_18pins_a: lcd0@1 {
353 sirf,pins = "lcd_18bitsgrp";
354 sirf,function = "lcd_18bits";
357 lcd_24pins_a: lcd0@2 {
359 sirf,pins = "lcd_24bitsgrp";
360 sirf,function = "lcd_24bits";
363 lcdrom_pins_a: lcdrom0@0 {
365 sirf,pins = "lcdromgrp";
366 sirf,function = "lcdrom";
369 uart0_pins_a: uart0@0 {
371 sirf,pins = "uart0grp";
372 sirf,function = "uart0";
375 uart0_noflow_pins_a: uart0@1 {
377 sirf,pins = "uart0_nostreamctrlgrp";
378 sirf,function = "uart0_nostreamctrl";
381 uart1_pins_a: uart1@0 {
383 sirf,pins = "uart1grp";
384 sirf,function = "uart1";
387 uart2_pins_a: uart2@0 {
389 sirf,pins = "uart2grp";
390 sirf,function = "uart2";
393 uart2_noflow_pins_a: uart2@1 {
395 sirf,pins = "uart2_nostreamctrlgrp";
396 sirf,function = "uart2_nostreamctrl";
399 spi0_pins_a: spi0@0 {
401 sirf,pins = "spi0grp";
402 sirf,function = "spi0";
405 spi1_pins_a: spi1@0 {
407 sirf,pins = "spi1grp";
408 sirf,function = "spi1";
411 i2c0_pins_a: i2c0@0 {
413 sirf,pins = "i2c0grp";
414 sirf,function = "i2c0";
417 i2c1_pins_a: i2c1@0 {
419 sirf,pins = "i2c1grp";
420 sirf,function = "i2c1";
423 pwm0_pins_a: pwm0@0 {
425 sirf,pins = "pwm0grp";
426 sirf,function = "pwm0";
429 pwm1_pins_a: pwm1@0 {
431 sirf,pins = "pwm1grp";
432 sirf,function = "pwm1";
435 pwm2_pins_a: pwm2@0 {
437 sirf,pins = "pwm2grp";
438 sirf,function = "pwm2";
441 pwm3_pins_a: pwm3@0 {
443 sirf,pins = "pwm3grp";
444 sirf,function = "pwm3";
447 pwm4_pins_a: pwm4@0 {
449 sirf,pins = "pwm4grp";
450 sirf,function = "pwm4";
455 sirf,pins = "gpsgrp";
456 sirf,function = "gps";
461 sirf,pins = "vipgrp";
462 sirf,function = "vip";
465 sdmmc0_pins_a: sdmmc0@0 {
467 sirf,pins = "sdmmc0grp";
468 sirf,function = "sdmmc0";
471 sdmmc1_pins_a: sdmmc1@0 {
473 sirf,pins = "sdmmc1grp";
474 sirf,function = "sdmmc1";
477 sdmmc2_pins_a: sdmmc2@0 {
479 sirf,pins = "sdmmc2grp";
480 sirf,function = "sdmmc2";
483 sdmmc2_nowp_pins_a: sdmmc2_nowp@0 {
485 sirf,pins = "sdmmc2_nowpgrp";
486 sirf,function = "sdmmc2_nowp";
489 sdmmc3_pins_a: sdmmc3@0 {
491 sirf,pins = "sdmmc3grp";
492 sirf,function = "sdmmc3";
495 sdmmc5_pins_a: sdmmc5@0 {
497 sirf,pins = "sdmmc5grp";
498 sirf,function = "sdmmc5";
503 sirf,pins = "i2sgrp";
504 sirf,function = "i2s";
507 i2s_no_din_pins_a: i2s_no_din@0 {
509 sirf,pins = "i2s_no_dingrp";
510 sirf,function = "i2s_no_din";
513 i2s_6chn_pins_a: i2s_6chn@0 {
515 sirf,pins = "i2s_6chngrp";
516 sirf,function = "i2s_6chn";
519 ac97_pins_a: ac97@0 {
521 sirf,pins = "ac97grp";
522 sirf,function = "ac97";
525 nand_pins_a: nand@0 {
527 sirf,pins = "nandgrp";
528 sirf,function = "nand";
531 usp0_pins_a: usp0@0 {
533 sirf,pins = "usp0grp";
534 sirf,function = "usp0";
537 usp0_uart_nostreamctrl_pins_a: usp0@1 {
539 sirf,pins = "usp0_uart_nostreamctrl_grp";
540 sirf,function = "usp0_uart_nostreamctrl";
543 usp1_pins_a: usp1@0 {
545 sirf,pins = "usp1grp";
546 sirf,function = "usp1";
549 usb0_upli_drvbus_pins_a: usb0_upli_drvbus@0 {
551 sirf,pins = "usb0_upli_drvbusgrp";
552 sirf,function = "usb0_upli_drvbus";
555 usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 {
557 sirf,pins = "usb1_utmi_drvbusgrp";
558 sirf,function = "usb1_utmi_drvbus";
561 usb1_dp_dn_pins_a: usb1_dp_dn@0 {
563 sirf,pins = "usb1_dp_dngrp";
564 sirf,function = "usb1_dp_dn";
567 uart1_route_io_usb1_pins_a: uart1_route_io_usb1@0 {
568 uart1_route_io_usb1 {
569 sirf,pins = "uart1_route_io_usb1grp";
570 sirf,function = "uart1_route_io_usb1";
573 warm_rst_pins_a: warm_rst@0 {
575 sirf,pins = "warm_rstgrp";
576 sirf,function = "warm_rst";
579 pulse_count_pins_a: pulse_count@0 {
581 sirf,pins = "pulse_countgrp";
582 sirf,function = "pulse_count";
585 cko0_pins_a: cko0@0 {
587 sirf,pins = "cko0grp";
588 sirf,function = "cko0";
591 cko1_pins_a: cko1@0 {
593 sirf,pins = "cko1grp";
594 sirf,function = "cko1";
600 compatible = "sirf,prima2-pwm";
601 reg = <0xb0130000 0x10000>;
606 compatible = "sirf,prima2-efuse";
607 reg = <0xb0140000 0x10000>;
612 compatible = "sirf,prima2-pulsec";
613 reg = <0xb0150000 0x10000>;
619 compatible = "sirf,prima2-pciiobg", "simple-bus";
620 #address-cells = <1>;
622 ranges = <0x56000000 0x56000000 0x1b00000>;
624 sd0: sdhci@56000000 {
626 compatible = "sirf,prima2-sdhc";
627 reg = <0x56000000 0x100000>;
633 sd1: sdhci@56100000 {
635 compatible = "sirf,prima2-sdhc";
636 reg = <0x56100000 0x100000>;
642 sd2: sdhci@56200000 {
644 compatible = "sirf,prima2-sdhc";
645 reg = <0x56200000 0x100000>;
651 sd3: sdhci@56300000 {
653 compatible = "sirf,prima2-sdhc";
654 reg = <0x56300000 0x100000>;
660 sd5: sdhci@56500000 {
662 compatible = "sirf,prima2-sdhc";
663 reg = <0x56500000 0x100000>;
670 compatible = "sirf,prima2-pcicp";
671 reg = <0x57900000 0x100000>;
675 rom-interface@57a00000 {
676 compatible = "sirf,prima2-romif";
677 reg = <0x57a00000 0x100000>;
683 compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus";
684 #address-cells = <1>;
686 reg = <0x80030000 0x10000>;
689 compatible = "sirf,prima2-gpsrtc";
690 reg = <0x1000 0x1000>;
691 interrupts = <55 56 57>;
695 compatible = "sirf,prima2-sysrtc";
696 reg = <0x2000 0x1000>;
697 interrupts = <52 53 54>;
701 compatible = "sirf,prima2-pwrc";
702 reg = <0x3000 0x1000>;
708 compatible = "simple-bus";
709 #address-cells = <1>;
711 ranges = <0xb8000000 0xb8000000 0x40000>;
714 compatible = "chipidea,ci13611a-prima2";
715 reg = <0xb8000000 0x10000>;
721 compatible = "chipidea,ci13611a-prima2";
722 reg = <0xb8010000 0x10000>;
728 compatible = "sirf,prima2-security";
729 reg = <0xb8030000 0x10000>;