arch/arm/boot/dts/bcm-cygnus.dtsi

   1 /*
   2  *  BSD LICENSE
   3  *
   4  *  Copyright(c) 2014 Broadcom Corporation.  All rights reserved.
   5  *
   6  *  Redistribution and use in source and binary forms, with or without
   7  *  modification, are permitted provided that the following conditions
   8  *  are met:
   9  *
  10  *    * Redistributions of source code must retain the above copyright
  11  *      notice, this list of conditions and the following disclaimer.
  12  *    * Redistributions in binary form must reproduce the above copyright
  13  *      notice, this list of conditions and the following disclaimer in
  14  *      the documentation and/or other materials provided with the
  15  *      distribution.
  16  *    * Neither the name of Broadcom Corporation nor the names of its
  17  *      contributors may be used to endorse or promote products derived
  18  *      from this software without specific prior written permission.
  19  *
  20  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <dt-bindings/interrupt-controller/arm-gic.h>
  34 #include <dt-bindings/interrupt-controller/irq.h>
  35 #include <dt-bindings/clock/bcm-cygnus.h>
  36
  37 #include "skeleton.dtsi"
  38
  39 / {
  40         compatible = "brcm,cygnus";
  41         model = "Broadcom Cygnus SoC";
  42         interrupt-parent = <&gic>;
  43
  44         aliases {
  45                 serial0 = &uart3;
  46         };
  47
  48         cpus {
  49                 #address-cells = <1>;
  50                 #size-cells = <0>;
  51
  52                 cpu@0 {
  53                         device_type = "cpu";
  54                         compatible = "arm,cortex-a9";
  55                         next-level-cache = <&L2>;
  56                         reg = <0x0>;
  57                 };
  58         };
  59
  60         /include/ "bcm-cygnus-clock.dtsi"
  61
  62         core {
  63                 compatible = "simple-bus";
  64                 ranges = <0x00000000 0x19000000 0x1000000>;
  65                 #address-cells = <1>;
  66                 #size-cells = <1>;
  67
  68                 timer@20200 {
  69                         compatible = "arm,cortex-a9-global-timer";
  70                         reg = <0x20200 0x100>;
  71                         interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
  72                         clocks = <&periph_clk>;
  73                 };
  74
  75                 gic: interrupt-controller@21000 {
  76                         compatible = "arm,cortex-a9-gic";
  77                         #interrupt-cells = <3>;
  78                         #address-cells = <0>;
  79                         interrupt-controller;
  80                         reg = <0x21000 0x1000>,
  81                               <0x20100 0x100>;
  82                 };
  83
  84                 L2: l2-cache {
  85                         compatible = "arm,pl310-cache";
  86                         reg = <0x22000 0x1000>;
  87                         cache-unified;
  88                         cache-level = <2>;
  89                 };
  90         };
  91
  92         axi {
  93                 compatible = "simple-bus";
  94                 ranges;
  95                 #address-cells = <1>;
  96                 #size-cells = <1>;
  97
  98                 pinctrl: pinctrl@0x0301d0c8 {
  99                         compatible = "brcm,cygnus-pinmux";
 100                         reg = <0x0301d0c8 0x30>,
 101                               <0x0301d24c 0x2c>;
 102                 };
 103
 104                 gpio_crmu: gpio@03024800 {
 105                         compatible = "brcm,cygnus-crmu-gpio";
 106                         reg = <0x03024800 0x50>,
 107                               <0x03024008 0x18>;
 108                         #gpio-cells = <2>;
 109                         gpio-controller;
 110                 };
 111
 112                 i2c0: i2c@18008000 {
 113                         compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
 114                         reg = <0x18008000 0x100>;
 115                         #address-cells = <1>;
 116                         #size-cells = <0>;
 117                         interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;
 118                         clock-frequency = <100000>;
 119                         status = "disabled";
 120                 };
 121
 122                 wdt0: wdt@18009000 {
 123                         compatible = "arm,sp805" , "arm,primecell";
 124                         reg = <0x18009000 0x1000>;
 125                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 126                         clocks = <&axi81_clk>;
 127                         clock-names = "apb_pclk";
 128                 };
 129
 130                 gpio_ccm: gpio@1800a000 {
 131                         compatible = "brcm,cygnus-ccm-gpio";
 132                         reg = <0x1800a000 0x50>,
 133                               <0x0301d164 0x20>;
 134                         #gpio-cells = <2>;
 135                         gpio-controller;
 136                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 137                         interrupt-controller;
 138                 };
 139
 140                 i2c1: i2c@1800b000 {
 141                         compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
 142                         reg = <0x1800b000 0x100>;
 143                         #address-cells = <1>;
 144                         #size-cells = <0>;
 145                         interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>;
 146                         clock-frequency = <100000>;
 147                         status = "disabled";
 148                 };
 149
 150                 pcie0: pcie@18012000 {
 151                         compatible = "brcm,iproc-pcie";
 152                         reg = <0x18012000 0x1000>;
 153
 154                         #interrupt-cells = <1>;
 155                         interrupt-map-mask = <0 0 0 0>;
 156                         interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;
 157
 158                         linux,pci-domain = <0>;
 159
 160                         bus-range = <0x00 0xff>;
 161
 162                         #address-cells = <3>;
 163                         #size-cells = <2>;
 164                         device_type = "pci";
 165                         ranges = <0x81000000 0 0          0x28000000 0 0x00010000
 166                                   0x82000000 0 0x20000000 0x20000000 0 0x04000000>;
 167
 168                         status = "disabled";
 169                 };
 170
 171                 pcie1: pcie@18013000 {
 172                         compatible = "brcm,iproc-pcie";
 173                         reg = <0x18013000 0x1000>;
 174
 175                         #interrupt-cells = <1>;
 176                         interrupt-map-mask = <0 0 0 0>;
 177                         interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>;
 178
 179                         linux,pci-domain = <1>;
 180
 181                         bus-range = <0x00 0xff>;
 182
 183                         #address-cells = <3>;
 184                         #size-cells = <2>;
 185                         device_type = "pci";
 186                         ranges = <0x81000000 0 0          0x48000000 0 0x00010000
 187                                   0x82000000 0 0x40000000 0x40000000 0 0x04000000>;
 188
 189                         status = "disabled";
 190                 };
 191
 192                 uart0: serial@18020000 {
 193                         compatible = "snps,dw-apb-uart";
 194                         reg = <0x18020000 0x100>;
 195                         reg-shift = <2>;
 196                         reg-io-width = <4>;
 197                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 198                         clocks = <&axi81_clk>;
 199                         clock-frequency = <100000000>;
 200                         status = "disabled";
 201                 };
 202
 203                 uart1: serial@18021000 {
 204                         compatible = "snps,dw-apb-uart";
 205                         reg = <0x18021000 0x100>;
 206                         reg-shift = <2>;
 207                         reg-io-width = <4>;
 208                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 209                         clocks = <&axi81_clk>;
 210                         clock-frequency = <100000000>;
 211                         status = "disabled";
 212                 };
 213
 214                 uart2: serial@18022000 {
 215                         compatible = "snps,dw-apb-uart";
 216                         reg = <0x18020000 0x100>;
 217                         reg-shift = <2>;
 218                         reg-io-width = <4>;
 219                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 220                         clocks = <&axi81_clk>;
 221                         clock-frequency = <100000000>;
 222                         status = "disabled";
 223                 };
 224
 225                 uart3: serial@18023000 {
 226                         compatible = "snps,dw-apb-uart";
 227                         reg = <0x18023000 0x100>;
 228                         reg-shift = <2>;
 229                         reg-io-width = <4>;
 230                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 231                         clocks = <&axi81_clk>;
 232                         clock-frequency = <100000000>;
 233                         status = "disabled";
 234                 };
 235
 236                 nand: nand@18046000 {
 237                         compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1",
 238                                      "brcm,brcmnand";
 239                         reg = <0x18046000 0x600>, <0xf8105408 0x600>,
 240                               <0x18046f00 0x20>;
 241                         reg-names = "nand", "iproc-idm", "iproc-ext";
 242                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 243
 244                         #address-cells = <1>;
 245                         #size-cells = <0>;
 246
 247                         brcm,nand-has-wp;
 248                 };
 249
 250                 gpio_asiu: gpio@180a5000 {
 251                         compatible = "brcm,cygnus-asiu-gpio";
 252                         reg = <0x180a5000 0x668>;
 253                         #gpio-cells = <2>;
 254                         gpio-controller;
 255
 256                         pinmux = <&pinctrl>;
 257
 258                         interrupt-controller;
 259                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
 260                 };
 261
 262                 touchscreen: tsc@180a6000 {
 263                         compatible = "brcm,iproc-touchscreen";
 264                         reg = <0x180a6000 0x40>;
 265                         clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>;
 266                         clock-names = "tsc_clk";
 267                         interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 268                         status = "disabled";
 269                 };
 270         };
 271 };