4 * Copyright(c) 2014 Broadcom Corporation. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
16 * * Neither the name of Broadcom Corporation nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
35 #include <dt-bindings/clock/bcm-cygnus.h>
37 #include "skeleton.dtsi"
40 compatible = "brcm,cygnus";
41 model = "Broadcom Cygnus SoC";
42 interrupt-parent = <&gic>;
50 compatible = "arm,cortex-a9";
51 next-level-cache = <&L2>;
56 /include/ "bcm-cygnus-clock.dtsi"
59 compatible = "simple-bus";
60 ranges = <0x00000000 0x19000000 0x1000000>;
65 compatible = "arm,cortex-a9-global-timer";
66 reg = <0x20200 0x100>;
67 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
68 clocks = <&periph_clk>;
71 gic: interrupt-controller@21000 {
72 compatible = "arm,cortex-a9-gic";
73 #interrupt-cells = <3>;
76 reg = <0x21000 0x1000>,
81 compatible = "arm,pl310-cache";
82 reg = <0x22000 0x1000>;
89 compatible = "simple-bus";
94 pcie_phy: phy@0301d0a0 {
95 compatible = "brcm,cygnus-pcie-phy";
96 reg = <0x0301d0a0 0x14>;
111 pinctrl: pinctrl@0x0301d0c8 {
112 compatible = "brcm,cygnus-pinmux";
113 reg = <0x0301d0c8 0x30>,
117 gpio_crmu: gpio@03024800 {
118 compatible = "brcm,cygnus-crmu-gpio";
119 reg = <0x03024800 0x50>,
127 compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
128 reg = <0x18008000 0x100>;
129 #address-cells = <1>;
131 interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;
132 clock-frequency = <100000>;
137 compatible = "arm,sp805" , "arm,primecell";
138 reg = <0x18009000 0x1000>;
139 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
140 clocks = <&axi81_clk>;
141 clock-names = "apb_pclk";
144 gpio_ccm: gpio@1800a000 {
145 compatible = "brcm,cygnus-ccm-gpio";
146 reg = <0x1800a000 0x50>,
151 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
152 interrupt-controller;
156 compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
157 reg = <0x1800b000 0x100>;
158 #address-cells = <1>;
160 interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>;
161 clock-frequency = <100000>;
165 pcie0: pcie@18012000 {
166 compatible = "brcm,iproc-pcie";
167 reg = <0x18012000 0x1000>;
169 #interrupt-cells = <1>;
170 interrupt-map-mask = <0 0 0 0>;
171 interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;
173 linux,pci-domain = <0>;
175 bus-range = <0x00 0xff>;
177 #address-cells = <3>;
180 ranges = <0x81000000 0 0 0x28000000 0 0x00010000
181 0x82000000 0 0x20000000 0x20000000 0 0x04000000>;
184 phy-names = "pcie-phy";
188 msi-parent = <&msi0>;
190 compatible = "brcm,iproc-msi";
192 interrupt-parent = <&gic>;
193 interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>,
194 <GIC_SPI 97 IRQ_TYPE_NONE>,
195 <GIC_SPI 98 IRQ_TYPE_NONE>,
196 <GIC_SPI 99 IRQ_TYPE_NONE>;
200 pcie1: pcie@18013000 {
201 compatible = "brcm,iproc-pcie";
202 reg = <0x18013000 0x1000>;
204 #interrupt-cells = <1>;
205 interrupt-map-mask = <0 0 0 0>;
206 interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>;
208 linux,pci-domain = <1>;
210 bus-range = <0x00 0xff>;
212 #address-cells = <3>;
215 ranges = <0x81000000 0 0 0x48000000 0 0x00010000
216 0x82000000 0 0x40000000 0x40000000 0 0x04000000>;
219 phy-names = "pcie-phy";
223 msi-parent = <&msi1>;
225 compatible = "brcm,iproc-msi";
227 interrupt-parent = <&gic>;
228 interrupts = <GIC_SPI 102 IRQ_TYPE_NONE>,
229 <GIC_SPI 103 IRQ_TYPE_NONE>,
230 <GIC_SPI 104 IRQ_TYPE_NONE>,
231 <GIC_SPI 105 IRQ_TYPE_NONE>;
235 uart0: serial@18020000 {
236 compatible = "snps,dw-apb-uart";
237 reg = <0x18020000 0x100>;
240 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
241 clocks = <&axi81_clk>;
242 clock-frequency = <100000000>;
246 uart1: serial@18021000 {
247 compatible = "snps,dw-apb-uart";
248 reg = <0x18021000 0x100>;
251 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
252 clocks = <&axi81_clk>;
253 clock-frequency = <100000000>;
257 uart2: serial@18022000 {
258 compatible = "snps,dw-apb-uart";
259 reg = <0x18020000 0x100>;
262 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
263 clocks = <&axi81_clk>;
264 clock-frequency = <100000000>;
268 uart3: serial@18023000 {
269 compatible = "snps,dw-apb-uart";
270 reg = <0x18023000 0x100>;
273 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
274 clocks = <&axi81_clk>;
275 clock-frequency = <100000000>;
279 nand: nand@18046000 {
280 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
281 reg = <0x18046000 0x600>, <0xf8105408 0x600>,
283 reg-names = "nand", "iproc-idm", "iproc-ext";
284 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
286 #address-cells = <1>;
292 gpio_asiu: gpio@180a5000 {
293 compatible = "brcm,cygnus-asiu-gpio";
294 reg = <0x180a5000 0x668>;
299 interrupt-controller;
300 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
301 gpio-ranges = <&pinctrl 0 42 1>,
313 <&pinctrl 24 130 10>,
328 <&pinctrl 70 156 17>,
329 <&pinctrl 87 104 12>,
332 <&pinctrl 105 116 6>,
333 <&pinctrl 111 100 2>,
334 <&pinctrl 113 122 4>,
354 touchscreen: tsc@180a6000 {
355 compatible = "brcm,iproc-touchscreen";
356 reg = <0x180a6000 0x40>;
357 clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>;
358 clock-names = "tsc_clk";
359 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;