4 * Copyright(c) 2015 Broadcom Corporation. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
16 * * Neither the name of Broadcom Corporation nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
35 #include <dt-bindings/clock/bcm-nsp.h>
37 #include "skeleton.dtsi"
40 compatible = "brcm,nsp";
41 model = "Broadcom Northstar Plus SoC";
42 interrupt-parent = <&gic>;
50 compatible = "arm,cortex-a9";
51 next-level-cache = <&L2>;
57 compatible = "arm,cortex-a9";
58 next-level-cache = <&L2>;
59 enable-method = "brcm,bcm-nsp-smp";
60 secondary-boot-reg = <0xffff042c>;
66 compatible = "arm,cortex-a9-pmu";
67 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH
68 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
69 interrupt-affinity = <&cpu0>, <&cpu1>;
73 compatible = "simple-bus";
74 ranges = <0x00000000 0x19000000 0x00023000>;
78 a9pll: arm_clk@00000 {
80 compatible = "brcm,nsp-armpll";
82 reg = <0x00000 0x1000>;
86 compatible = "arm,cortex-a9-global-timer";
87 reg = <0x20200 0x100>;
88 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
89 clocks = <&periph_clk>;
93 compatible = "arm,cortex-a9-twd-timer";
95 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
96 IRQ_TYPE_LEVEL_HIGH)>;
97 clocks = <&periph_clk>;
101 compatible = "arm,cortex-a9-twd-wdt";
102 reg = <0x20620 0x20>;
103 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
104 IRQ_TYPE_LEVEL_HIGH)>;
105 clocks = <&periph_clk>;
108 gic: interrupt-controller@21000 {
109 compatible = "arm,cortex-a9-gic";
110 #interrupt-cells = <3>;
111 #address-cells = <0>;
112 interrupt-controller;
113 reg = <0x21000 0x1000>,
118 compatible = "arm,pl310-cache";
119 reg = <0x22000 0x1000>;
126 #address-cells = <1>;
132 compatible = "fixed-clock";
133 clock-frequency = <25000000>;
138 compatible = "fixed-factor-clock";
139 clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
144 iprocslow: iprocslow {
146 compatible = "fixed-factor-clock";
147 clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
152 periph_clk: periph_clk {
154 compatible = "fixed-factor-clock";
162 compatible = "simple-bus";
163 ranges = <0x00000000 0x18000000 0x0011ba08>;
164 #address-cells = <1>;
168 compatible = "brcm,nsp-gpio-a";
174 interrupt-controller;
175 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
176 gpio-ranges = <&pinctrl 0 0 32>;
180 compatible = "ns16550a";
181 reg = <0x0300 0x100>;
182 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
188 compatible = "ns16550a";
189 reg = <0x0400 0x100>;
190 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
196 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
197 reg = <0x026000 0x600>,
200 reg-names = "nand", "iproc-idm", "iproc-ext";
201 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
203 #address-cells = <1>;
209 ccbtimer0: timer@34000 {
210 compatible = "arm,sp804";
211 reg = <0x34000 0x1000>;
212 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
214 clocks = <&iprocslow>;
215 clock-names = "apb_pclk";
218 ccbtimer1: timer@35000 {
219 compatible = "arm,sp804";
220 reg = <0x35000 0x1000>;
221 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&iprocslow>;
224 clock-names = "apb_pclk";
228 compatible = "brcm,iproc-i2c";
229 reg = <0x38000 0x50>;
230 #address-cells = <1>;
232 interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;
233 clock-frequency = <100000>;
237 compatible = "arm,sp805", "arm,primecell";
238 reg = <0x39000 0x1000>;
239 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
240 clocks = <&iprocslow>, <&iprocslow>;
241 clock-names = "wdogclk", "apb_pclk";
244 lcpll0: lcpll0@3f100 {
246 compatible = "brcm,nsp-lcpll0";
247 reg = <0x3f100 0x14>;
249 clock-output-names = "lcpll0", "pcie_phy", "sdio",
253 genpll: genpll@3f140 {
255 compatible = "brcm,nsp-genpll";
256 reg = <0x3f140 0x24>;
258 clock-output-names = "genpll", "phy", "ethernetclk",
259 "usbclk", "iprocfast", "sata1",
263 pinctrl: pinctrl@3f1c0 {
264 compatible = "brcm,nsp-pinmux";
265 reg = <0x3f1c0 0x04>,
271 pcie0: pcie@18012000 {
272 compatible = "brcm,iproc-pcie";
273 reg = <0x18012000 0x1000>;
275 #interrupt-cells = <1>;
276 interrupt-map-mask = <0 0 0 0>;
277 interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_NONE>;
279 linux,pci-domain = <0>;
281 bus-range = <0x00 0xff>;
283 #address-cells = <3>;
287 /* Note: The HW does not support I/O resources. So,
288 * only the memory resource range is being specified.
290 ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
295 pcie1: pcie@18013000 {
296 compatible = "brcm,iproc-pcie";
297 reg = <0x18013000 0x1000>;
299 #interrupt-cells = <1>;
300 interrupt-map-mask = <0 0 0 0>;
301 interrupt-map = <0 0 0 0 &gic GIC_SPI 137 IRQ_TYPE_NONE>;
303 linux,pci-domain = <1>;
305 bus-range = <0x00 0xff>;
307 #address-cells = <3>;
311 /* Note: The HW does not support I/O resources. So,
312 * only the memory resource range is being specified.
314 ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
319 pcie2: pcie@18014000 {
320 compatible = "brcm,iproc-pcie";
321 reg = <0x18014000 0x1000>;
323 #interrupt-cells = <1>;
324 interrupt-map-mask = <0 0 0 0>;
325 interrupt-map = <0 0 0 0 &gic GIC_SPI 143 IRQ_TYPE_NONE>;
327 linux,pci-domain = <2>;
329 bus-range = <0x00 0xff>;
331 #address-cells = <3>;
335 /* Note: The HW does not support I/O resources. So,
336 * only the memory resource range is being specified.
338 ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>;