arch/arm/boot/dts/bcm283x.dtsi

   1 #include <dt-bindings/pinctrl/bcm2835.h>
   2 #include <dt-bindings/clock/bcm2835.h>
   3 #include <dt-bindings/clock/bcm2835-aux.h>
   4 #include <dt-bindings/gpio/gpio.h>
   5
   6 /* This include file covers the common peripherals and configuration between
   7  * bcm2835 and bcm2836 implementations, leaving the CPU configuration to
   8  * bcm2835.dtsi and bcm2836.dtsi.
   9  */
  10
  11 / {
  12         compatible = "brcm,bcm2835";
  13         model = "BCM2835";
  14         interrupt-parent = <&intc>;
  15         #address-cells = <1>;
  16         #size-cells = <1>;
  17
  18         chosen {
  19                 bootargs = "earlyprintk console=ttyAMA0";
  20         };
  21
  22         soc {
  23                 compatible = "simple-bus";
  24                 #address-cells = <1>;
  25                 #size-cells = <1>;
  26
  27                 timer@7e003000 {
  28                         compatible = "brcm,bcm2835-system-timer";
  29                         reg = <0x7e003000 0x1000>;
  30                         interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
  31                         /* This could be a reference to BCM2835_CLOCK_TIMER,
  32                          * but we don't have the driver using the common clock
  33                          * support yet.
  34                          */
  35                         clock-frequency = <1000000>;
  36                 };
  37
  38                 dma: dma@7e007000 {
  39                         compatible = "brcm,bcm2835-dma";
  40                         reg = <0x7e007000 0xf00>;
  41                         interrupts = <1 16>,
  42                                      <1 17>,
  43                                      <1 18>,
  44                                      <1 19>,
  45                                      <1 20>,
  46                                      <1 21>,
  47                                      <1 22>,
  48                                      <1 23>,
  49                                      <1 24>,
  50                                      <1 25>,
  51                                      <1 26>,
  52                                      /* dma channel 11-14 share one irq */
  53                                      <1 27>,
  54                                      <1 27>,
  55                                      <1 27>,
  56                                      <1 27>,
  57                                      /* unused shared irq for all channels */
  58                                      <1 28>;
  59                         interrupt-names = "dma0",
  60                                           "dma1",
  61                                           "dma2",
  62                                           "dma3",
  63                                           "dma4",
  64                                           "dma5",
  65                                           "dma6",
  66                                           "dma7",
  67                                           "dma8",
  68                                           "dma9",
  69                                           "dma10",
  70                                           "dma11",
  71                                           "dma12",
  72                                           "dma13",
  73                                           "dma14",
  74                                           "dma-shared-all";
  75                         #dma-cells = <1>;
  76                         brcm,dma-channel-mask = <0x7f35>;
  77                 };
  78
  79                 intc: interrupt-controller@7e00b200 {
  80                         compatible = "brcm,bcm2835-armctrl-ic";
  81                         reg = <0x7e00b200 0x200>;
  82                         interrupt-controller;
  83                         #interrupt-cells = <2>;
  84                 };
  85
  86                 watchdog@7e100000 {
  87                         compatible = "brcm,bcm2835-pm-wdt";
  88                         reg = <0x7e100000 0x28>;
  89                 };
  90
  91                 clocks: cprman@7e101000 {
  92                         compatible = "brcm,bcm2835-cprman";
  93                         #clock-cells = <1>;
  94                         reg = <0x7e101000 0x2000>;
  95
  96                         /* CPRMAN derives almost everything from the
  97                          * platform's oscillator.  However, the DSI
  98                          * pixel clocks come from the DSI analog PHY.
  99                          */
 100                         clocks = <&clk_osc>,
 101                                 <&dsi0 0>, <&dsi0 1>, <&dsi0 2>,
 102                                 <&dsi1 0>, <&dsi1 1>, <&dsi1 2>;
 103                 };
 104
 105                 rng@7e104000 {
 106                         compatible = "brcm,bcm2835-rng";
 107                         reg = <0x7e104000 0x10>;
 108                 };
 109
 110                 mailbox: mailbox@7e00b880 {
 111                         compatible = "brcm,bcm2835-mbox";
 112                         reg = <0x7e00b880 0x40>;
 113                         interrupts = <0 1>;
 114                         #mbox-cells = <0>;
 115                 };
 116
 117                 gpio: gpio@7e200000 {
 118                         compatible = "brcm,bcm2835-gpio";
 119                         reg = <0x7e200000 0xb4>;
 120                         /*
 121                          * The GPIO IP block is designed for 3 banks of GPIOs.
 122                          * Each bank has a GPIO interrupt for itself.
 123                          * There is an overall "any bank" interrupt.
 124                          * In order, these are GIC interrupts 17, 18, 19, 20.
 125                          * Since the BCM2835 only has 2 banks, the 2nd bank
 126                          * interrupt output appears to be mirrored onto the
 127                          * 3rd bank's interrupt signal.
 128                          * So, a bank0 interrupt shows up on 17, 20, and
 129                          * a bank1 interrupt shows up on 18, 19, 20!
 130                          */
 131                         interrupts = <2 17>, <2 18>, <2 19>, <2 20>;
 132
 133                         gpio-controller;
 134                         #gpio-cells = <2>;
 135
 136                         interrupt-controller;
 137                         #interrupt-cells = <2>;
 138
 139                         /* Defines pin muxing groups according to
 140                          * BCM2835-ARM-Peripherals.pdf page 102.
 141                          *
 142                          * While each pin can have its mux selected
 143                          * for various functions individually, some
 144                          * groups only make sense to switch to a
 145                          * particular function together.
 146                          */
 147                         dpi_gpio0: dpi_gpio0 {
 148                                 brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
 149                                              12 13 14 15 16 17 18 19
 150                                              20 21 22 23 24 25 26 27>;
 151                                 brcm,function = <BCM2835_FSEL_ALT2>;
 152                         };
 153                         emmc_gpio22: emmc_gpio22 {
 154                                 brcm,pins = <22 23 24 25 26 27>;
 155                                 brcm,function = <BCM2835_FSEL_ALT3>;
 156                         };
 157                         emmc_gpio34: emmc_gpio34 {
 158                                 brcm,pins = <34 35 36 37 38 39>;
 159                                 brcm,function = <BCM2835_FSEL_ALT3>;
 160                                 brcm,pull = <BCM2835_PUD_OFF
 161                                              BCM2835_PUD_UP
 162                                              BCM2835_PUD_UP
 163                                              BCM2835_PUD_UP
 164                                              BCM2835_PUD_UP
 165                                              BCM2835_PUD_UP>;
 166                         };
 167                         emmc_gpio48: emmc_gpio48 {
 168                                 brcm,pins = <48 49 50 51 52 53>;
 169                                 brcm,function = <BCM2835_FSEL_ALT3>;
 170                         };
 171
 172                         gpclk0_gpio4: gpclk0_gpio4 {
 173                                 brcm,pins = <4>;
 174                                 brcm,function = <BCM2835_FSEL_ALT0>;
 175                         };
 176                         gpclk1_gpio5: gpclk1_gpio5 {
 177                                 brcm,pins = <5>;
 178                                 brcm,function = <BCM2835_FSEL_ALT0>;
 179                         };
 180                         gpclk1_gpio42: gpclk1_gpio42 {
 181                                 brcm,pins = <42>;
 182                                 brcm,function = <BCM2835_FSEL_ALT0>;
 183                         };
 184                         gpclk1_gpio44: gpclk1_gpio44 {
 185                                 brcm,pins = <44>;
 186                                 brcm,function = <BCM2835_FSEL_ALT0>;
 187                         };
 188                         gpclk2_gpio6: gpclk2_gpio6 {
 189                                 brcm,pins = <6>;
 190                                 brcm,function = <BCM2835_FSEL_ALT0>;
 191                         };
 192                         gpclk2_gpio43: gpclk2_gpio43 {
 193                                 brcm,pins = <43>;
 194                                 brcm,function = <BCM2835_FSEL_ALT0>;
 195                         };
 196
 197                         i2c0_gpio0: i2c0_gpio0 {
 198                                 brcm,pins = <0 1>;
 199                                 brcm,function = <BCM2835_FSEL_ALT0>;
 200                         };
 201                         i2c0_gpio28: i2c0_gpio28 {
 202                                 brcm,pins = <28 29>;
 203                                 brcm,function = <BCM2835_FSEL_ALT0>;
 204                         };
 205                         i2c0_gpio44: i2c0_gpio44 {
 206                                 brcm,pins = <44 45>;
 207                                 brcm,function = <BCM2835_FSEL_ALT1>;
 208                         };
 209                         i2c1_gpio2: i2c1_gpio2 {
 210                                 brcm,pins = <2 3>;
 211                                 brcm,function = <BCM2835_FSEL_ALT0>;
 212                         };
 213                         i2c1_gpio44: i2c1_gpio44 {
 214                                 brcm,pins = <44 45>;
 215                                 brcm,function = <BCM2835_FSEL_ALT2>;
 216                         };
 217                         i2c_slave_gpio18: i2c_slave_gpio18 {
 218                                 brcm,pins = <18 19 20 21>;
 219                                 brcm,function = <BCM2835_FSEL_ALT3>;
 220                         };
 221
 222                         jtag_gpio4: jtag_gpio4 {
 223                                 brcm,pins = <4 5 6 12 13>;
 224                                 brcm,function = <BCM2835_FSEL_ALT4>;
 225                         };
 226                         jtag_gpio22: jtag_gpio22 {
 227                                 brcm,pins = <22 23 24 25 26 27>;
 228                                 brcm,function = <BCM2835_FSEL_ALT4>;
 229                         };
 230
 231                         pcm_gpio18: pcm_gpio18 {
 232                                 brcm,pins = <18 19 20 21>;
 233                                 brcm,function = <BCM2835_FSEL_ALT0>;
 234                         };
 235                         pcm_gpio28: pcm_gpio28 {
 236                                 brcm,pins = <28 29 30 31>;
 237                                 brcm,function = <BCM2835_FSEL_ALT2>;
 238                         };
 239
 240                         pwm0_gpio12: pwm0_gpio12 {
 241                                 brcm,pins = <12>;
 242                                 brcm,function = <BCM2835_FSEL_ALT0>;
 243                         };
 244                         pwm0_gpio18: pwm0_gpio18 {
 245                                 brcm,pins = <18>;
 246                                 brcm,function = <BCM2835_FSEL_ALT5>;
 247                         };
 248                         pwm0_gpio40: pwm0_gpio40 {
 249                                 brcm,pins = <40>;
 250                                 brcm,function = <BCM2835_FSEL_ALT0>;
 251                         };
 252                         pwm1_gpio13: pwm1_gpio13 {
 253                                 brcm,pins = <13>;
 254                                 brcm,function = <BCM2835_FSEL_ALT0>;
 255                         };
 256                         pwm1_gpio19: pwm1_gpio19 {
 257                                 brcm,pins = <19>;
 258                                 brcm,function = <BCM2835_FSEL_ALT5>;
 259                         };
 260                         pwm1_gpio41: pwm1_gpio41 {
 261                                 brcm,pins = <41>;
 262                                 brcm,function = <BCM2835_FSEL_ALT0>;
 263                         };
 264                         pwm1_gpio45: pwm1_gpio45 {
 265                                 brcm,pins = <45>;
 266                                 brcm,function = <BCM2835_FSEL_ALT0>;
 267                         };
 268
 269                         sdhost_gpio48: sdhost_gpio48 {
 270                                 brcm,pins = <48 49 50 51 52 53>;
 271                                 brcm,function = <BCM2835_FSEL_ALT0>;
 272                         };
 273
 274                         spi0_gpio7: spi0_gpio7 {
 275                                 brcm,pins = <7 8 9 10 11>;
 276                                 brcm,function = <BCM2835_FSEL_ALT0>;
 277                         };
 278                         spi0_gpio35: spi0_gpio35 {
 279                                 brcm,pins = <35 36 37 38 39>;
 280                                 brcm,function = <BCM2835_FSEL_ALT0>;
 281                         };
 282                         spi1_gpio16: spi1_gpio16 {
 283                                 brcm,pins = <16 17 18 19 20 21>;
 284                                 brcm,function = <BCM2835_FSEL_ALT4>;
 285                         };
 286                         spi2_gpio40: spi2_gpio40 {
 287                                 brcm,pins = <40 41 42 43 44 45>;
 288                                 brcm,function = <BCM2835_FSEL_ALT4>;
 289                         };
 290
 291                         uart0_gpio14: uart0_gpio14 {
 292                                 brcm,pins = <14 15>;
 293                                 brcm,function = <BCM2835_FSEL_ALT0>;
 294                         };
 295                         /* Separate from the uart0_gpio14 group
 296                          * because it conflicts with spi1_gpio16, and
 297                          * people often run uart0 on the two pins
 298                          * without flow control.
 299                          */
 300                         uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 {
 301                                 brcm,pins = <16 17>;
 302                                 brcm,function = <BCM2835_FSEL_ALT3>;
 303                         };
 304                         uart0_ctsrts_gpio30: uart0_ctsrts_gpio30 {
 305                                 brcm,pins = <30 31>;
 306                                 brcm,function = <BCM2835_FSEL_ALT3>;
 307                         };
 308                         uart0_gpio32: uart0_gpio32 {
 309                                 brcm,pins = <32 33>;
 310                                 brcm,function = <BCM2835_FSEL_ALT3>;
 311                         };
 312                         uart0_gpio36: uart0_gpio36 {
 313                                 brcm,pins = <36 37>;
 314                                 brcm,function = <BCM2835_FSEL_ALT2>;
 315                         };
 316                         uart0_ctsrts_gpio38: uart0_ctsrts_gpio38 {
 317                                 brcm,pins = <38 39>;
 318                                 brcm,function = <BCM2835_FSEL_ALT2>;
 319                         };
 320
 321                         uart1_gpio14: uart1_gpio14 {
 322                                 brcm,pins = <14 15>;
 323                                 brcm,function = <BCM2835_FSEL_ALT5>;
 324                         };
 325                         uart1_ctsrts_gpio16: uart1_ctsrts_gpio16 {
 326                                 brcm,pins = <16 17>;
 327                                 brcm,function = <BCM2835_FSEL_ALT5>;
 328                         };
 329                         uart1_gpio32: uart1_gpio32 {
 330                                 brcm,pins = <32 33>;
 331                                 brcm,function = <BCM2835_FSEL_ALT5>;
 332                         };
 333                         uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 {
 334                                 brcm,pins = <30 31>;
 335                                 brcm,function = <BCM2835_FSEL_ALT5>;
 336                         };
 337                         uart1_gpio40: uart1_gpio40 {
 338                                 brcm,pins = <40 41>;
 339                                 brcm,function = <BCM2835_FSEL_ALT5>;
 340                         };
 341                         uart1_ctsrts_gpio42: uart1_ctsrts_gpio42 {
 342                                 brcm,pins = <42 43>;
 343                                 brcm,function = <BCM2835_FSEL_ALT5>;
 344                         };
 345                 };
 346
 347                 uart0: serial@7e201000 {
 348                         compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
 349                         reg = <0x7e201000 0x1000>;
 350                         interrupts = <2 25>;
 351                         clocks = <&clocks BCM2835_CLOCK_UART>,
 352                                  <&clocks BCM2835_CLOCK_VPU>;
 353                         clock-names = "uartclk", "apb_pclk";
 354                         arm,primecell-periphid = <0x00241011>;
 355                 };
 356
 357                 sdhost: mmc@7e202000 {
 358                         compatible = "brcm,bcm2835-sdhost";
 359                         reg = <0x7e202000 0x100>;
 360                         interrupts = <2 24>;
 361                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 362                         dmas = <&dma 13>;
 363                         dma-names = "rx-tx";
 364                         status = "disabled";
 365                 };
 366
 367                 i2s: i2s@7e203000 {
 368                         compatible = "brcm,bcm2835-i2s";
 369                         reg = <0x7e203000 0x20>,
 370                               <0x7e101098 0x02>;
 371
 372                         dmas = <&dma 2>,
 373                                <&dma 3>;
 374                         dma-names = "tx", "rx";
 375                         status = "disabled";
 376                 };
 377
 378                 spi: spi@7e204000 {
 379                         compatible = "brcm,bcm2835-spi";
 380                         reg = <0x7e204000 0x1000>;
 381                         interrupts = <2 22>;
 382                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 383                         #address-cells = <1>;
 384                         #size-cells = <0>;
 385                         status = "disabled";
 386                 };
 387
 388                 i2c0: i2c@7e205000 {
 389                         compatible = "brcm,bcm2835-i2c";
 390                         reg = <0x7e205000 0x1000>;
 391                         interrupts = <2 21>;
 392                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 393                         #address-cells = <1>;
 394                         #size-cells = <0>;
 395                         status = "disabled";
 396                 };
 397
 398                 pixelvalve@7e206000 {
 399                         compatible = "brcm,bcm2835-pixelvalve0";
 400                         reg = <0x7e206000 0x100>;
 401                         interrupts = <2 13>; /* pwa0 */
 402                 };
 403
 404                 pixelvalve@7e207000 {
 405                         compatible = "brcm,bcm2835-pixelvalve1";
 406                         reg = <0x7e207000 0x100>;
 407                         interrupts = <2 14>; /* pwa1 */
 408                 };
 409
 410                 dsi0: dsi@7e209000 {
 411                         compatible = "brcm,bcm2835-dsi0";
 412                         reg = <0x7e209000 0x78>;
 413                         interrupts = <2 4>;
 414                         #address-cells = <1>;
 415                         #size-cells = <0>;
 416                         #clock-cells = <1>;
 417
 418                         clocks = <&clocks BCM2835_PLLA_DSI0>,
 419                                  <&clocks BCM2835_CLOCK_DSI0E>,
 420                                  <&clocks BCM2835_CLOCK_DSI0P>;
 421                         clock-names = "phy", "escape", "pixel";
 422
 423                         clock-output-names = "dsi0_byte",
 424                                              "dsi0_ddr2",
 425                                              "dsi0_ddr";
 426
 427                 };
 428
 429                 thermal: thermal@7e212000 {
 430                         compatible = "brcm,bcm2835-thermal";
 431                         reg = <0x7e212000 0x8>;
 432                         clocks = <&clocks BCM2835_CLOCK_TSENS>;
 433                         status = "disabled";
 434                 };
 435
 436                 aux: aux@0x7e215000 {
 437                         compatible = "brcm,bcm2835-aux";
 438                         #clock-cells = <1>;
 439                         reg = <0x7e215000 0x8>;
 440                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 441                 };
 442
 443                 uart1: serial@7e215040 {
 444                         compatible = "brcm,bcm2835-aux-uart";
 445                         reg = <0x7e215040 0x40>;
 446                         interrupts = <1 29>;
 447                         clocks = <&aux BCM2835_AUX_CLOCK_UART>;
 448                         status = "disabled";
 449                 };
 450
 451                 spi1: spi@7e215080 {
 452                         compatible = "brcm,bcm2835-aux-spi";
 453                         reg = <0x7e215080 0x40>;
 454                         interrupts = <1 29>;
 455                         clocks = <&aux BCM2835_AUX_CLOCK_SPI1>;
 456                         #address-cells = <1>;
 457                         #size-cells = <0>;
 458                         status = "disabled";
 459                 };
 460
 461                 spi2: spi@7e2150c0 {
 462                         compatible = "brcm,bcm2835-aux-spi";
 463                         reg = <0x7e2150c0 0x40>;
 464                         interrupts = <1 29>;
 465                         clocks = <&aux BCM2835_AUX_CLOCK_SPI2>;
 466                         #address-cells = <1>;
 467                         #size-cells = <0>;
 468                         status = "disabled";
 469                 };
 470
 471                 pwm: pwm@7e20c000 {
 472                         compatible = "brcm,bcm2835-pwm";
 473                         reg = <0x7e20c000 0x28>;
 474                         clocks = <&clocks BCM2835_CLOCK_PWM>;
 475                         assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
 476                         assigned-clock-rates = <10000000>;
 477                         #pwm-cells = <2>;
 478                         status = "disabled";
 479                 };
 480
 481                 sdhci: sdhci@7e300000 {
 482                         compatible = "brcm,bcm2835-sdhci";
 483                         reg = <0x7e300000 0x100>;
 484                         interrupts = <2 30>;
 485                         clocks = <&clocks BCM2835_CLOCK_EMMC>;
 486                         status = "disabled";
 487                 };
 488
 489                 hvs@7e400000 {
 490                         compatible = "brcm,bcm2835-hvs";
 491                         reg = <0x7e400000 0x6000>;
 492                         interrupts = <2 1>;
 493                 };
 494
 495                 dsi1: dsi@7e700000 {
 496                         compatible = "brcm,bcm2835-dsi1";
 497                         reg = <0x7e700000 0x8c>;
 498                         interrupts = <2 12>;
 499                         #address-cells = <1>;
 500                         #size-cells = <0>;
 501                         #clock-cells = <1>;
 502
 503                         clocks = <&clocks BCM2835_PLLD_DSI1>,
 504                                  <&clocks BCM2835_CLOCK_DSI1E>,
 505                                  <&clocks BCM2835_CLOCK_DSI1P>;
 506                         clock-names = "phy", "escape", "pixel";
 507
 508                         clock-output-names = "dsi1_byte",
 509                                              "dsi1_ddr2",
 510                                              "dsi1_ddr";
 511
 512                         status = "disabled";
 513                 };
 514
 515                 i2c1: i2c@7e804000 {
 516                         compatible = "brcm,bcm2835-i2c";
 517                         reg = <0x7e804000 0x1000>;
 518                         interrupts = <2 21>;
 519                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 520                         #address-cells = <1>;
 521                         #size-cells = <0>;
 522                         status = "disabled";
 523                 };
 524
 525                 i2c2: i2c@7e805000 {
 526                         compatible = "brcm,bcm2835-i2c";
 527                         reg = <0x7e805000 0x1000>;
 528                         interrupts = <2 21>;
 529                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 530                         #address-cells = <1>;
 531                         #size-cells = <0>;
 532                         status = "disabled";
 533                 };
 534
 535                 vec: vec@7e806000 {
 536                         compatible = "brcm,bcm2835-vec";
 537                         reg = <0x7e806000 0x1000>;
 538                         clocks = <&clocks BCM2835_CLOCK_VEC>;
 539                         interrupts = <2 27>;
 540                         status = "disabled";
 541                 };
 542
 543                 pixelvalve@7e807000 {
 544                         compatible = "brcm,bcm2835-pixelvalve2";
 545                         reg = <0x7e807000 0x100>;
 546                         interrupts = <2 10>; /* pixelvalve */
 547                 };
 548
 549                 hdmi: hdmi@7e902000 {
 550                         compatible = "brcm,bcm2835-hdmi";
 551                         reg = <0x7e902000 0x600>,
 552                               <0x7e808000 0x100>;
 553                         interrupts = <2 8>, <2 9>;
 554                         ddc = <&i2c2>;
 555                         clocks = <&clocks BCM2835_PLLH_PIX>,
 556                                  <&clocks BCM2835_CLOCK_HSM>;
 557                         clock-names = "pixel", "hdmi";
 558                         dmas = <&dma 17>;
 559                         dma-names = "audio-rx";
 560                         status = "disabled";
 561                 };
 562
 563                 usb: usb@7e980000 {
 564                         compatible = "brcm,bcm2835-usb";
 565                         reg = <0x7e980000 0x10000>;
 566                         interrupts = <1 9>;
 567                         #address-cells = <1>;
 568                         #size-cells = <0>;
 569                         clocks = <&clk_usb>;
 570                         clock-names = "otg";
 571                 };
 572
 573                 v3d: v3d@7ec00000 {
 574                         compatible = "brcm,bcm2835-v3d";
 575                         reg = <0x7ec00000 0x1000>;
 576                         interrupts = <1 10>;
 577                 };
 578
 579                 vc4: gpu {
 580                         compatible = "brcm,bcm2835-vc4";
 581                 };
 582         };
 583
 584         clocks {
 585                 compatible = "simple-bus";
 586                 #address-cells = <1>;
 587                 #size-cells = <0>;
 588
 589                 /* The oscillator is the root of the clock tree. */
 590                 clk_osc: clock@3 {
 591                         compatible = "fixed-clock";
 592                         reg = <3>;
 593                         #clock-cells = <0>;
 594                         clock-output-names = "osc";
 595                         clock-frequency = <19200000>;
 596                 };
 597
 598                 clk_usb: clock@4 {
 599                         compatible = "fixed-clock";
 600                         reg = <4>;
 601                         #clock-cells = <0>;
 602                         clock-output-names = "otg";
 603                         clock-frequency = <480000000>;
 604                 };
 605         };
 606 };