1 #include <dt-bindings/pinctrl/bcm2835.h>
2 #include <dt-bindings/clock/bcm2835.h>
3 #include <dt-bindings/clock/bcm2835-aux.h>
4 #include <dt-bindings/gpio/gpio.h>
6 /* firmware-provided startup stubs live here, where the secondary CPUs are
9 /memreserve/ 0x00000000 0x00001000;
11 /* This include file covers the common peripherals and configuration between
12 * bcm2835 and bcm2836 implementations, leaving the CPU configuration to
13 * bcm2835.dtsi and bcm2836.dtsi.
17 compatible = "brcm,bcm2835";
19 interrupt-parent = <&intc>;
24 bootargs = "earlyprintk console=ttyAMA0";
28 compatible = "simple-bus";
33 compatible = "brcm,bcm2835-system-timer";
34 reg = <0x7e003000 0x1000>;
35 interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
36 /* This could be a reference to BCM2835_CLOCK_TIMER,
37 * but we don't have the driver using the common clock
40 clock-frequency = <1000000>;
44 compatible = "brcm,bcm2835-dma";
45 reg = <0x7e007000 0xf00>;
57 /* dma channel 11-14 share one irq */
62 /* unused shared irq for all channels */
64 interrupt-names = "dma0",
81 brcm,dma-channel-mask = <0x7f35>;
84 intc: interrupt-controller@7e00b200 {
85 compatible = "brcm,bcm2835-armctrl-ic";
86 reg = <0x7e00b200 0x200>;
88 #interrupt-cells = <2>;
92 compatible = "brcm,bcm2835-pm-wdt";
93 reg = <0x7e100000 0x28>;
96 clocks: cprman@7e101000 {
97 compatible = "brcm,bcm2835-cprman";
99 reg = <0x7e101000 0x2000>;
101 /* CPRMAN derives almost everything from the
102 * platform's oscillator. However, the DSI
103 * pixel clocks come from the DSI analog PHY.
106 <&dsi0 0>, <&dsi0 1>, <&dsi0 2>,
107 <&dsi1 0>, <&dsi1 1>, <&dsi1 2>;
111 compatible = "brcm,bcm2835-rng";
112 reg = <0x7e104000 0x10>;
115 mailbox: mailbox@7e00b880 {
116 compatible = "brcm,bcm2835-mbox";
117 reg = <0x7e00b880 0x40>;
122 gpio: gpio@7e200000 {
123 compatible = "brcm,bcm2835-gpio";
124 reg = <0x7e200000 0xb4>;
126 * The GPIO IP block is designed for 3 banks of GPIOs.
127 * Each bank has a GPIO interrupt for itself.
128 * There is an overall "any bank" interrupt.
129 * In order, these are GIC interrupts 17, 18, 19, 20.
130 * Since the BCM2835 only has 2 banks, the 2nd bank
131 * interrupt output appears to be mirrored onto the
132 * 3rd bank's interrupt signal.
133 * So, a bank0 interrupt shows up on 17, 20, and
134 * a bank1 interrupt shows up on 18, 19, 20!
136 interrupts = <2 17>, <2 18>, <2 19>, <2 20>;
141 interrupt-controller;
142 #interrupt-cells = <2>;
144 /* Defines pin muxing groups according to
145 * BCM2835-ARM-Peripherals.pdf page 102.
147 * While each pin can have its mux selected
148 * for various functions individually, some
149 * groups only make sense to switch to a
150 * particular function together.
152 dpi_gpio0: dpi_gpio0 {
153 brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
154 12 13 14 15 16 17 18 19
155 20 21 22 23 24 25 26 27>;
156 brcm,function = <BCM2835_FSEL_ALT2>;
158 emmc_gpio22: emmc_gpio22 {
159 brcm,pins = <22 23 24 25 26 27>;
160 brcm,function = <BCM2835_FSEL_ALT3>;
162 emmc_gpio34: emmc_gpio34 {
163 brcm,pins = <34 35 36 37 38 39>;
164 brcm,function = <BCM2835_FSEL_ALT3>;
165 brcm,pull = <BCM2835_PUD_OFF
172 emmc_gpio48: emmc_gpio48 {
173 brcm,pins = <48 49 50 51 52 53>;
174 brcm,function = <BCM2835_FSEL_ALT3>;
177 gpclk0_gpio4: gpclk0_gpio4 {
179 brcm,function = <BCM2835_FSEL_ALT0>;
181 gpclk1_gpio5: gpclk1_gpio5 {
183 brcm,function = <BCM2835_FSEL_ALT0>;
185 gpclk1_gpio42: gpclk1_gpio42 {
187 brcm,function = <BCM2835_FSEL_ALT0>;
189 gpclk1_gpio44: gpclk1_gpio44 {
191 brcm,function = <BCM2835_FSEL_ALT0>;
193 gpclk2_gpio6: gpclk2_gpio6 {
195 brcm,function = <BCM2835_FSEL_ALT0>;
197 gpclk2_gpio43: gpclk2_gpio43 {
199 brcm,function = <BCM2835_FSEL_ALT0>;
202 i2c0_gpio0: i2c0_gpio0 {
204 brcm,function = <BCM2835_FSEL_ALT0>;
206 i2c0_gpio28: i2c0_gpio28 {
208 brcm,function = <BCM2835_FSEL_ALT0>;
210 i2c0_gpio44: i2c0_gpio44 {
212 brcm,function = <BCM2835_FSEL_ALT1>;
214 i2c1_gpio2: i2c1_gpio2 {
216 brcm,function = <BCM2835_FSEL_ALT0>;
218 i2c1_gpio44: i2c1_gpio44 {
220 brcm,function = <BCM2835_FSEL_ALT2>;
222 i2c_slave_gpio18: i2c_slave_gpio18 {
223 brcm,pins = <18 19 20 21>;
224 brcm,function = <BCM2835_FSEL_ALT3>;
227 jtag_gpio4: jtag_gpio4 {
228 brcm,pins = <4 5 6 12 13>;
229 brcm,function = <BCM2835_FSEL_ALT4>;
231 jtag_gpio22: jtag_gpio22 {
232 brcm,pins = <22 23 24 25 26 27>;
233 brcm,function = <BCM2835_FSEL_ALT4>;
236 pcm_gpio18: pcm_gpio18 {
237 brcm,pins = <18 19 20 21>;
238 brcm,function = <BCM2835_FSEL_ALT0>;
240 pcm_gpio28: pcm_gpio28 {
241 brcm,pins = <28 29 30 31>;
242 brcm,function = <BCM2835_FSEL_ALT2>;
245 pwm0_gpio12: pwm0_gpio12 {
247 brcm,function = <BCM2835_FSEL_ALT0>;
249 pwm0_gpio18: pwm0_gpio18 {
251 brcm,function = <BCM2835_FSEL_ALT5>;
253 pwm0_gpio40: pwm0_gpio40 {
255 brcm,function = <BCM2835_FSEL_ALT0>;
257 pwm1_gpio13: pwm1_gpio13 {
259 brcm,function = <BCM2835_FSEL_ALT0>;
261 pwm1_gpio19: pwm1_gpio19 {
263 brcm,function = <BCM2835_FSEL_ALT5>;
265 pwm1_gpio41: pwm1_gpio41 {
267 brcm,function = <BCM2835_FSEL_ALT0>;
269 pwm1_gpio45: pwm1_gpio45 {
271 brcm,function = <BCM2835_FSEL_ALT0>;
274 sdhost_gpio48: sdhost_gpio48 {
275 brcm,pins = <48 49 50 51 52 53>;
276 brcm,function = <BCM2835_FSEL_ALT0>;
279 spi0_gpio7: spi0_gpio7 {
280 brcm,pins = <7 8 9 10 11>;
281 brcm,function = <BCM2835_FSEL_ALT0>;
283 spi0_gpio35: spi0_gpio35 {
284 brcm,pins = <35 36 37 38 39>;
285 brcm,function = <BCM2835_FSEL_ALT0>;
287 spi1_gpio16: spi1_gpio16 {
288 brcm,pins = <16 17 18 19 20 21>;
289 brcm,function = <BCM2835_FSEL_ALT4>;
291 spi2_gpio40: spi2_gpio40 {
292 brcm,pins = <40 41 42 43 44 45>;
293 brcm,function = <BCM2835_FSEL_ALT4>;
296 uart0_gpio14: uart0_gpio14 {
298 brcm,function = <BCM2835_FSEL_ALT0>;
300 /* Separate from the uart0_gpio14 group
301 * because it conflicts with spi1_gpio16, and
302 * people often run uart0 on the two pins
303 * without flow control.
305 uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 {
307 brcm,function = <BCM2835_FSEL_ALT3>;
309 uart0_ctsrts_gpio30: uart0_ctsrts_gpio30 {
311 brcm,function = <BCM2835_FSEL_ALT3>;
313 uart0_gpio32: uart0_gpio32 {
315 brcm,function = <BCM2835_FSEL_ALT3>;
317 uart0_gpio36: uart0_gpio36 {
319 brcm,function = <BCM2835_FSEL_ALT2>;
321 uart0_ctsrts_gpio38: uart0_ctsrts_gpio38 {
323 brcm,function = <BCM2835_FSEL_ALT2>;
326 uart1_gpio14: uart1_gpio14 {
328 brcm,function = <BCM2835_FSEL_ALT5>;
330 uart1_ctsrts_gpio16: uart1_ctsrts_gpio16 {
332 brcm,function = <BCM2835_FSEL_ALT5>;
334 uart1_gpio32: uart1_gpio32 {
336 brcm,function = <BCM2835_FSEL_ALT5>;
338 uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 {
340 brcm,function = <BCM2835_FSEL_ALT5>;
342 uart1_gpio40: uart1_gpio40 {
344 brcm,function = <BCM2835_FSEL_ALT5>;
346 uart1_ctsrts_gpio42: uart1_ctsrts_gpio42 {
348 brcm,function = <BCM2835_FSEL_ALT5>;
352 uart0: serial@7e201000 {
353 compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
354 reg = <0x7e201000 0x1000>;
356 clocks = <&clocks BCM2835_CLOCK_UART>,
357 <&clocks BCM2835_CLOCK_VPU>;
358 clock-names = "uartclk", "apb_pclk";
359 arm,primecell-periphid = <0x00241011>;
362 sdhost: mmc@7e202000 {
363 compatible = "brcm,bcm2835-sdhost";
364 reg = <0x7e202000 0x100>;
366 clocks = <&clocks BCM2835_CLOCK_VPU>;
373 compatible = "brcm,bcm2835-i2s";
374 reg = <0x7e203000 0x20>,
379 dma-names = "tx", "rx";
384 compatible = "brcm,bcm2835-spi";
385 reg = <0x7e204000 0x1000>;
387 clocks = <&clocks BCM2835_CLOCK_VPU>;
388 #address-cells = <1>;
394 compatible = "brcm,bcm2835-i2c";
395 reg = <0x7e205000 0x1000>;
397 clocks = <&clocks BCM2835_CLOCK_VPU>;
398 #address-cells = <1>;
403 pixelvalve@7e206000 {
404 compatible = "brcm,bcm2835-pixelvalve0";
405 reg = <0x7e206000 0x100>;
406 interrupts = <2 13>; /* pwa0 */
409 pixelvalve@7e207000 {
410 compatible = "brcm,bcm2835-pixelvalve1";
411 reg = <0x7e207000 0x100>;
412 interrupts = <2 14>; /* pwa1 */
416 compatible = "brcm,bcm2835-dsi0";
417 reg = <0x7e209000 0x78>;
419 #address-cells = <1>;
423 clocks = <&clocks BCM2835_PLLA_DSI0>,
424 <&clocks BCM2835_CLOCK_DSI0E>,
425 <&clocks BCM2835_CLOCK_DSI0P>;
426 clock-names = "phy", "escape", "pixel";
428 clock-output-names = "dsi0_byte",
434 thermal: thermal@7e212000 {
435 compatible = "brcm,bcm2835-thermal";
436 reg = <0x7e212000 0x8>;
437 clocks = <&clocks BCM2835_CLOCK_TSENS>;
441 aux: aux@0x7e215000 {
442 compatible = "brcm,bcm2835-aux";
444 reg = <0x7e215000 0x8>;
445 clocks = <&clocks BCM2835_CLOCK_VPU>;
448 uart1: serial@7e215040 {
449 compatible = "brcm,bcm2835-aux-uart";
450 reg = <0x7e215040 0x40>;
452 clocks = <&aux BCM2835_AUX_CLOCK_UART>;
457 compatible = "brcm,bcm2835-aux-spi";
458 reg = <0x7e215080 0x40>;
460 clocks = <&aux BCM2835_AUX_CLOCK_SPI1>;
461 #address-cells = <1>;
467 compatible = "brcm,bcm2835-aux-spi";
468 reg = <0x7e2150c0 0x40>;
470 clocks = <&aux BCM2835_AUX_CLOCK_SPI2>;
471 #address-cells = <1>;
477 compatible = "brcm,bcm2835-pwm";
478 reg = <0x7e20c000 0x28>;
479 clocks = <&clocks BCM2835_CLOCK_PWM>;
480 assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
481 assigned-clock-rates = <10000000>;
486 sdhci: sdhci@7e300000 {
487 compatible = "brcm,bcm2835-sdhci";
488 reg = <0x7e300000 0x100>;
490 clocks = <&clocks BCM2835_CLOCK_EMMC>;
495 compatible = "brcm,bcm2835-hvs";
496 reg = <0x7e400000 0x6000>;
501 compatible = "brcm,bcm2835-dsi1";
502 reg = <0x7e700000 0x8c>;
504 #address-cells = <1>;
508 clocks = <&clocks BCM2835_PLLD_DSI1>,
509 <&clocks BCM2835_CLOCK_DSI1E>,
510 <&clocks BCM2835_CLOCK_DSI1P>;
511 clock-names = "phy", "escape", "pixel";
513 clock-output-names = "dsi1_byte",
521 compatible = "brcm,bcm2835-i2c";
522 reg = <0x7e804000 0x1000>;
524 clocks = <&clocks BCM2835_CLOCK_VPU>;
525 #address-cells = <1>;
531 compatible = "brcm,bcm2835-i2c";
532 reg = <0x7e805000 0x1000>;
534 clocks = <&clocks BCM2835_CLOCK_VPU>;
535 #address-cells = <1>;
541 compatible = "brcm,bcm2835-vec";
542 reg = <0x7e806000 0x1000>;
543 clocks = <&clocks BCM2835_CLOCK_VEC>;
548 pixelvalve@7e807000 {
549 compatible = "brcm,bcm2835-pixelvalve2";
550 reg = <0x7e807000 0x100>;
551 interrupts = <2 10>; /* pixelvalve */
554 hdmi: hdmi@7e902000 {
555 compatible = "brcm,bcm2835-hdmi";
556 reg = <0x7e902000 0x600>,
558 interrupts = <2 8>, <2 9>;
560 clocks = <&clocks BCM2835_PLLH_PIX>,
561 <&clocks BCM2835_CLOCK_HSM>;
562 clock-names = "pixel", "hdmi";
564 dma-names = "audio-rx";
569 compatible = "brcm,bcm2835-usb";
570 reg = <0x7e980000 0x10000>;
572 #address-cells = <1>;
579 compatible = "brcm,bcm2835-v3d";
580 reg = <0x7ec00000 0x1000>;
585 compatible = "brcm,bcm2835-vc4";
590 compatible = "simple-bus";
591 #address-cells = <1>;
594 /* The oscillator is the root of the clock tree. */
596 compatible = "fixed-clock";
599 clock-output-names = "osc";
600 clock-frequency = <19200000>;
604 compatible = "fixed-clock";
607 clock-output-names = "otg";
608 clock-frequency = <480000000>;