2 * Broadcom BCM470X / BCM5301X ARM platform code.
3 * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015,
4 * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs
6 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
8 * Licensed under the GNU/GPL. See COPYING for details.
11 #include <dt-bindings/clock/bcm-nsp.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include "skeleton.dtsi"
19 interrupt-parent = <&gic>;
22 compatible = "simple-bus";
23 ranges = <0x00000000 0x18000000 0x00001000>;
28 compatible = "ns16550";
30 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
31 clocks = <&iprocslow>;
36 compatible = "ns16550";
38 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
39 clocks = <&iprocslow>;
45 compatible = "simple-bus";
46 ranges = <0x00000000 0x19000000 0x00023000>;
50 a9pll: arm_clk@00000 {
52 compatible = "brcm,nsp-armpll";
54 reg = <0x00000 0x1000>;
58 compatible = "arm,cortex-a9-scu";
59 reg = <0x20000 0x100>;
63 compatible = "arm,cortex-a9-global-timer";
64 reg = <0x20200 0x100>;
65 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
66 clocks = <&periph_clk>;
70 compatible = "arm,cortex-a9-twd-timer";
71 reg = <0x20600 0x100>;
72 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
73 clocks = <&periph_clk>;
76 gic: interrupt-controller@21000 {
77 compatible = "arm,cortex-a9-gic";
78 #interrupt-cells = <3>;
81 reg = <0x21000 0x1000>,
85 L2: cache-controller@22000 {
86 compatible = "arm,pl310-cache";
87 reg = <0x22000 0x1000>;
97 compatible = "arm,cortex-a9-pmu";
99 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
100 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
104 #address-cells = <1>;
110 compatible = "fixed-clock";
111 clock-frequency = <25000000>;
116 compatible = "fixed-factor-clock";
117 clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
122 iprocslow: iprocslow {
124 compatible = "fixed-factor-clock";
125 clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
130 periph_clk: periph_clk {
132 compatible = "fixed-factor-clock";
140 compatible = "brcm,bus-axi";
141 reg = <0x18000000 0x1000>;
142 ranges = <0x00000000 0x18000000 0x00100000>;
143 #address-cells = <1>;
146 #interrupt-cells = <1>;
147 interrupt-map-mask = <0x000fffff 0xffff>;
150 <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
152 /* PCIe Controller 0 */
153 <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
154 <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
155 <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
156 <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
157 <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
158 <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
160 /* PCIe Controller 1 */
161 <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
162 <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
163 <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
164 <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
165 <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
166 <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
168 /* PCIe Controller 2 */
169 <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
170 <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
171 <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
172 <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
173 <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
174 <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
176 /* USB 2.0 Controller */
177 <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
179 /* USB 3.0 Controller */
180 <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
182 /* Ethernet Controller 0 */
183 <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
185 /* Ethernet Controller 1 */
186 <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
188 /* Ethernet Controller 2 */
189 <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
191 /* Ethernet Controller 3 */
192 <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
194 /* NAND Controller */
195 <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
196 <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
197 <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
198 <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
199 <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
200 <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
201 <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
202 <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
204 chipcommon: chipcommon@0 {
205 reg = <0x00000000 0x1000>;
212 lcpll0: lcpll0@1800c100 {
214 compatible = "brcm,nsp-lcpll0";
215 reg = <0x1800c100 0x14>;
217 clock-output-names = "lcpll0", "pcie_phy", "sdio",
221 genpll: genpll@1800c140 {
223 compatible = "brcm,nsp-genpll";
224 reg = <0x1800c140 0x24>;
226 clock-output-names = "genpll", "phy", "ethernetclk",
227 "usbclk", "iprocfast", "sata1",
231 nand: nand@18028000 {
232 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
233 reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
234 reg-names = "nand", "iproc-idm", "iproc-ext";
235 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
237 #address-cells = <1>;