2 * Broadcom BCM63138 DSL SoCs Device Tree
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
8 #include "skeleton.dtsi"
11 compatible = "brcm,bcm63138";
12 model = "Broadcom BCM63138 DSL SoC";
13 interrupt-parent = <&gic>;
26 compatible = "arm,cortex-a9";
27 next-level-cache = <&L2>;
33 compatible = "arm,cortex-a9";
34 next-level-cache = <&L2>;
43 arm_timer_clk: arm_timer_clk {
45 compatible = "fixed-clock";
46 clock-frequency = <500000000>;
49 periph_clk: periph_clk {
51 compatible = "fixed-clock";
52 clock-frequency = <50000000>;
53 clock-output-names = "periph";
59 compatible = "simple-bus";
60 ranges = <0 0x80000000 0x784000>;
64 L2: cache-controller@1d000 {
65 compatible = "arm,pl310-cache";
66 reg = <0x1d000 0x1000>;
69 cache-size = <524288>;
71 cache-line-size = <32>;
72 interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
76 compatible = "arm,cortex-a9-scu";
77 reg = <0x1e000 0x100>;
80 gic: interrupt-controller@1e100 {
81 compatible = "arm,cortex-a9-gic";
84 #interrupt-cells = <3>;
89 global_timer: timer@1e200 {
90 compatible = "arm,cortex-a9-global-timer";
92 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
93 clocks = <&arm_timer_clk>;
96 local_timer: local-timer@1e600 {
97 compatible = "arm,cortex-a9-twd-timer";
99 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
100 clocks = <&arm_timer_clk>;
103 twd_watchdog: watchdog@1e620 {
104 compatible = "arm,cortex-a9-twd-wdt";
105 reg = <0x1e620 0x20>;
106 interrupts = <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>;
110 /* Legacy UBUS base */
112 compatible = "simple-bus";
113 #address-cells = <1>;
115 ranges = <0 0xfffe8000 0x8100>;
117 serial0: serial@600 {
118 compatible = "brcm,bcm6345-uart";
120 interrupts = <GIC_SPI 32 0>;
121 clocks = <&periph_clk>;
122 clock-names = "periph";
126 serial1: serial@620 {
127 compatible = "brcm,bcm6345-uart";
129 interrupts = <GIC_SPI 33 0>;
130 clocks = <&periph_clk>;
131 clock-names = "periph";