2 * Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC
4 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
6 * based on GPL'ed 2.6 kernel sources
7 * (c) Marvell International Ltd.
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include "skeleton.dtsi"
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 model = "Marvell Armada 1500-mini (BG2CD) SoC";
19 compatible = "marvell,berlin2cd", "marvell,berlin";
26 compatible = "arm,cortex-a9";
28 next-level-cache = <&l2>;
35 compatible = "fixed-clock";
37 clock-frequency = <25000000>;
41 compatible = "fixed-clock";
43 clock-frequency = <75000000>;
46 sysclk: system-clock {
47 compatible = "fixed-clock";
49 clock-frequency = <300000000>;
54 compatible = "simple-bus";
57 interrupt-parent = <&gic>;
59 ranges = <0 0xf7000000 0x1000000>;
61 l2: l2-cache-controller@ac0000 {
62 compatible = "arm,pl310-cache";
63 reg = <0xac0000 0x1000>;
68 gic: interrupt-controller@ad1000 {
69 compatible = "arm,cortex-a9-gic";
70 reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
72 #interrupt-cells = <3>;
76 compatible = "arm,cortex-a9-twd-timer";
77 reg = <0xad0600 0x20>;
78 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
83 compatible = "simple-bus";
87 ranges = <0 0xe80000 0x10000>;
88 interrupt-parent = <&aic>;
91 compatible = "snps,dw-apb-timer";
95 clock-names = "timer";
100 compatible = "snps,dw-apb-timer";
104 clock-names = "timer";
109 compatible = "snps,dw-apb-timer";
113 clock-names = "timer";
118 compatible = "snps,dw-apb-timer";
122 clock-names = "timer";
127 compatible = "snps,dw-apb-timer";
131 clock-names = "timer";
136 compatible = "snps,dw-apb-timer";
140 clock-names = "timer";
145 compatible = "snps,dw-apb-timer";
149 clock-names = "timer";
154 compatible = "snps,dw-apb-timer";
158 clock-names = "timer";
162 aic: interrupt-controller@3000 {
163 compatible = "snps,dw-apb-ictl";
164 reg = <0x3000 0xc00>;
165 interrupt-controller;
166 #interrupt-cells = <1>;
167 interrupt-parent = <&gic>;
168 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
173 compatible = "simple-bus";
174 #address-cells = <1>;
177 ranges = <0 0xfc0000 0x10000>;
178 interrupt-parent = <&sic>;
181 compatible = "snps,dw-apb-uart";
182 reg = <0x9000 0x100>;
191 compatible = "snps,dw-apb-uart";
192 reg = <0xa000 0x100>;
200 sic: interrupt-controller@e000 {
201 compatible = "snps,dw-apb-ictl";
202 reg = <0xe000 0x400>;
203 interrupt-controller;
204 #interrupt-cells = <1>;
205 interrupt-parent = <&gic>;
206 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;