arch/arm/boot/dts/berlin2q.dtsi

   1 /*
   2  * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
   3  *
   4  * This file is licensed under the terms of the GNU General Public
   5  * License version 2. This program is licensed "as is" without any
   6  * warranty of any kind, whether express or implied.
   7  */
   8
   9 #include <dt-bindings/clock/berlin2q.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11
  12 #include "skeleton.dtsi"
  13
  14 / {
  15         model = "Marvell Armada 1500 pro (BG2-Q) SoC";
  16         compatible = "marvell,berlin2q", "marvell,berlin";
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21
  22                 cpu@0 {
  23                         compatible = "arm,cortex-a9";
  24                         device_type = "cpu";
  25                         next-level-cache = <&l2>;
  26                         reg = <0>;
  27                 };
  28
  29                 cpu@1 {
  30                         compatible = "arm,cortex-a9";
  31                         device_type = "cpu";
  32                         next-level-cache = <&l2>;
  33                         reg = <1>;
  34                 };
  35
  36                 cpu@2 {
  37                         compatible = "arm,cortex-a9";
  38                         device_type = "cpu";
  39                         next-level-cache = <&l2>;
  40                         reg = <2>;
  41                 };
  42
  43                 cpu@3 {
  44                         compatible = "arm,cortex-a9";
  45                         device_type = "cpu";
  46                         next-level-cache = <&l2>;
  47                         reg = <3>;
  48                 };
  49         };
  50
  51         refclk: oscillator {
  52                 compatible = "fixed-clock";
  53                 #clock-cells = <0>;
  54                 clock-frequency = <25000000>;
  55         };
  56
  57         soc {
  58                 compatible = "simple-bus";
  59                 #address-cells = <1>;
  60                 #size-cells = <1>;
  61
  62                 ranges = <0 0xf7000000 0x1000000>;
  63                 interrupt-parent = <&gic>;
  64
  65                 sdhci0: sdhci@ab0000 {
  66                         compatible = "mrvl,pxav3-mmc";
  67                         reg = <0xab0000 0x200>;
  68                         clocks = <&chip CLKID_SDIO1XIN>;
  69                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
  70                         status = "disabled";
  71                 };
  72
  73                 sdhci1: sdhci@ab0800 {
  74                         compatible = "mrvl,pxav3-mmc";
  75                         reg = <0xab0800 0x200>;
  76                         clocks = <&chip CLKID_SDIO1XIN>;
  77                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
  78                         status = "disabled";
  79                 };
  80
  81                 sdhci2: sdhci@ab1000 {
  82                         compatible = "mrvl,pxav3-mmc";
  83                         reg = <0xab1000 0x200>;
  84                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
  85                         clocks = <&chip CLKID_SDIO1XIN>;
  86                         status = "disabled";
  87                 };
  88
  89                 l2: l2-cache-controller@ac0000 {
  90                         compatible = "arm,pl310-cache";
  91                         reg = <0xac0000 0x1000>;
  92                         cache-level = <2>;
  93                         arm,data-latency = <2 2 2>;
  94                         arm,tag-latency = <2 2 2>;
  95                 };
  96
  97                 scu: snoop-control-unit@ad0000 {
  98                         compatible = "arm,cortex-a9-scu";
  99                         reg = <0xad0000 0x58>;
 100                 };
 101
 102                 local-timer@ad0600 {
 103                         compatible = "arm,cortex-a9-twd-timer";
 104                         reg = <0xad0600 0x20>;
 105                         clocks = <&chip CLKID_TWD>;
 106                         interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
 107                 };
 108
 109                 gic: interrupt-controller@ad1000 {
 110                         compatible = "arm,cortex-a9-gic";
 111                         reg = <0xad1000 0x1000>, <0xad0100 0x100>;
 112                         interrupt-controller;
 113                         #interrupt-cells = <3>;
 114                 };
 115
 116                 apb@e80000 {
 117                         compatible = "simple-bus";
 118                         #address-cells = <1>;
 119                         #size-cells = <1>;
 120
 121                         ranges = <0 0xe80000 0x10000>;
 122                         interrupt-parent = <&aic>;
 123
 124                         gpio0: gpio@0400 {
 125                                 compatible = "snps,dw-apb-gpio";
 126                                 reg = <0x0400 0x400>;
 127                                 #address-cells = <1>;
 128                                 #size-cells = <0>;
 129
 130                                 porta: gpio-port@0 {
 131                                         compatible = "snps,dw-apb-gpio-port";
 132                                         gpio-controller;
 133                                         #gpio-cells = <2>;
 134                                         snps,nr-gpios = <32>;
 135                                         reg = <0>;
 136                                         interrupt-controller;
 137                                         #interrupt-cells = <2>;
 138                                         interrupts = <0>;
 139                                 };
 140                         };
 141
 142                         gpio1: gpio@0800 {
 143                                 compatible = "snps,dw-apb-gpio";
 144                                 reg = <0x0800 0x400>;
 145                                 #address-cells = <1>;
 146                                 #size-cells = <0>;
 147
 148                                 portb: gpio-port@1 {
 149                                         compatible = "snps,dw-apb-gpio-port";
 150                                         gpio-controller;
 151                                         #gpio-cells = <2>;
 152                                         snps,nr-gpios = <32>;
 153                                         reg = <0>;
 154                                         interrupt-controller;
 155                                         #interrupt-cells = <2>;
 156                                         interrupts = <1>;
 157                                 };
 158                         };
 159
 160                         gpio2: gpio@0c00 {
 161                                 compatible = "snps,dw-apb-gpio";
 162                                 reg = <0x0c00 0x400>;
 163                                 #address-cells = <1>;
 164                                 #size-cells = <0>;
 165
 166                                 portc: gpio-port@2 {
 167                                         compatible = "snps,dw-apb-gpio-port";
 168                                         gpio-controller;
 169                                         #gpio-cells = <2>;
 170                                         snps,nr-gpios = <32>;
 171                                         reg = <0>;
 172                                         interrupt-controller;
 173                                         #interrupt-cells = <2>;
 174                                         interrupts = <2>;
 175                                 };
 176                         };
 177
 178                         gpio3: gpio@1000 {
 179                                 compatible = "snps,dw-apb-gpio";
 180                                 reg = <0x1000 0x400>;
 181                                 #address-cells = <1>;
 182                                 #size-cells = <0>;
 183
 184                                 portd: gpio-port@3 {
 185                                         compatible = "snps,dw-apb-gpio-port";
 186                                         gpio-controller;
 187                                         #gpio-cells = <2>;
 188                                         snps,nr-gpios = <32>;
 189                                         reg = <0>;
 190                                         interrupt-controller;
 191                                         #interrupt-cells = <2>;
 192                                         interrupts = <3>;
 193                                 };
 194                         };
 195
 196                         i2c0: i2c@1400 {
 197                                 compatible = "snps,designware-i2c";
 198                                 #address-cells = <1>;
 199                                 #size-cells = <0>;
 200                                 reg = <0x1400 0x100>;
 201                                 interrupt-parent = <&aic>;
 202                                 interrupts = <4>;
 203                                 clocks = <&chip CLKID_CFG>;
 204                                 pinctrl-0 = <&twsi0_pmux>;
 205                                 pinctrl-names = "default";
 206                                 status = "disabled";
 207                         };
 208
 209                         i2c1: i2c@1800 {
 210                                 compatible = "snps,designware-i2c";
 211                                 #address-cells = <1>;
 212                                 #size-cells = <0>;
 213                                 reg = <0x1800 0x100>;
 214                                 interrupt-parent = <&aic>;
 215                                 interrupts = <5>;
 216                                 clocks = <&chip CLKID_CFG>;
 217                                 pinctrl-0 = <&twsi1_pmux>;
 218                                 pinctrl-names = "default";
 219                                 status = "disabled";
 220                         };
 221
 222                         timer0: timer@2c00 {
 223                                 compatible = "snps,dw-apb-timer";
 224                                 reg = <0x2c00 0x14>;
 225                                 clocks = <&chip CLKID_CFG>;
 226                                 clock-names = "timer";
 227                                 interrupts = <8>;
 228                         };
 229
 230                         timer1: timer@2c14 {
 231                                 compatible = "snps,dw-apb-timer";
 232                                 reg = <0x2c14 0x14>;
 233                                 clocks = <&chip CLKID_CFG>;
 234                                 clock-names = "timer";
 235                                 status = "disabled";
 236                         };
 237
 238                         timer2: timer@2c28 {
 239                                 compatible = "snps,dw-apb-timer";
 240                                 reg = <0x2c28 0x14>;
 241                                 clocks = <&chip CLKID_CFG>;
 242                                 clock-names = "timer";
 243                                 status = "disabled";
 244                         };
 245
 246                         timer3: timer@2c3c {
 247                                 compatible = "snps,dw-apb-timer";
 248                                 reg = <0x2c3c 0x14>;
 249                                 clocks = <&chip CLKID_CFG>;
 250                                 clock-names = "timer";
 251                                 status = "disabled";
 252                         };
 253
 254                         timer4: timer@2c50 {
 255                                 compatible = "snps,dw-apb-timer";
 256                                 reg = <0x2c50 0x14>;
 257                                 clocks = <&chip CLKID_CFG>;
 258                                 clock-names = "timer";
 259                                 status = "disabled";
 260                         };
 261
 262                         timer5: timer@2c64 {
 263                                 compatible = "snps,dw-apb-timer";
 264                                 reg = <0x2c64 0x14>;
 265                                 clocks = <&chip CLKID_CFG>;
 266                                 clock-names = "timer";
 267                                 status = "disabled";
 268                         };
 269
 270                         timer6: timer@2c78 {
 271                                 compatible = "snps,dw-apb-timer";
 272                                 reg = <0x2c78 0x14>;
 273                                 clocks = <&chip CLKID_CFG>;
 274                                 clock-names = "timer";
 275                                 status = "disabled";
 276                         };
 277
 278                         timer7: timer@2c8c {
 279                                 compatible = "snps,dw-apb-timer";
 280                                 reg = <0x2c8c 0x14>;
 281                                 clocks = <&chip CLKID_CFG>;
 282                                 clock-names = "timer";
 283                                 status = "disabled";
 284                         };
 285
 286                         aic: interrupt-controller@3800 {
 287                                 compatible = "snps,dw-apb-ictl";
 288                                 reg = <0x3800 0x30>;
 289                                 interrupt-controller;
 290                                 #interrupt-cells = <1>;
 291                                 interrupt-parent = <&gic>;
 292                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 293                         };
 294
 295                         gpio4: gpio@5000 {
 296                                 compatible = "snps,dw-apb-gpio";
 297                                 reg = <0x5000 0x400>;
 298                                 #address-cells = <1>;
 299                                 #size-cells = <0>;
 300
 301                                 porte: gpio-port@4 {
 302                                         compatible = "snps,dw-apb-gpio-port";
 303                                         gpio-controller;
 304                                         #gpio-cells = <2>;
 305                                         snps,nr-gpios = <32>;
 306                                         reg = <0>;
 307                                 };
 308                         };
 309
 310                         gpio5: gpio@c000 {
 311                                 compatible = "snps,dw-apb-gpio";
 312                                 reg = <0xc000 0x400>;
 313                                 #address-cells = <1>;
 314                                 #size-cells = <0>;
 315
 316                                 portf: gpio-port@5 {
 317                                         compatible = "snps,dw-apb-gpio-port";
 318                                         gpio-controller;
 319                                         #gpio-cells = <2>;
 320                                         snps,nr-gpios = <32>;
 321                                         reg = <0>;
 322                                 };
 323                         };
 324                 };
 325
 326                 chip: chip-control@ea0000 {
 327                         compatible = "marvell,berlin2q-chip-ctrl";
 328                         #clock-cells = <1>;
 329                         reg = <0xea0000 0x400>, <0xdd0170 0x10>;
 330                         clocks = <&refclk>;
 331                         clock-names = "refclk";
 332
 333                         twsi0_pmux: twsi0-pmux {
 334                                 groups = "G6";
 335                                 function = "twsi0";
 336                         };
 337
 338                         twsi1_pmux: twsi1-pmux {
 339                                 groups = "G7";
 340                                 function = "twsi1";
 341                         };
 342                 };
 343
 344                 apb@fc0000 {
 345                         compatible = "simple-bus";
 346                         #address-cells = <1>;
 347                         #size-cells = <1>;
 348
 349                         ranges = <0 0xfc0000 0x10000>;
 350                         interrupt-parent = <&sic>;
 351
 352                         i2c2: i2c@7000 {
 353                                 compatible = "snps,designware-i2c";
 354                                 #address-cells = <1>;
 355                                 #size-cells = <0>;
 356                                 reg = <0x7000 0x100>;
 357                                 interrupt-parent = <&sic>;
 358                                 interrupts = <6>;
 359                                 clocks = <&refclk>;
 360                                 pinctrl-0 = <&twsi2_pmux>;
 361                                 pinctrl-names = "default";
 362                                 status = "disabled";
 363                         };
 364
 365                         i2c3: i2c@8000 {
 366                                 compatible = "snps,designware-i2c";
 367                                 #address-cells = <1>;
 368                                 #size-cells = <0>;
 369                                 reg = <0x8000 0x100>;
 370                                 interrupt-parent = <&sic>;
 371                                 interrupts = <7>;
 372                                 clocks = <&refclk>;
 373                                 pinctrl-0 = <&twsi3_pmux>;
 374                                 pinctrl-names = "default";
 375                                 status = "disabled";
 376                         };
 377
 378                         uart0: uart@9000 {
 379                                 compatible = "snps,dw-apb-uart";
 380                                 reg = <0x9000 0x100>;
 381                                 interrupt-parent = <&sic>;
 382                                 interrupts = <8>;
 383                                 clocks = <&refclk>;
 384                                 reg-shift = <2>;
 385                                 pinctrl-0 = <&uart0_pmux>;
 386                                 pinctrl-names = "default";
 387                                 status = "disabled";
 388                         };
 389
 390                         uart1: uart@a000 {
 391                                 compatible = "snps,dw-apb-uart";
 392                                 reg = <0xa000 0x100>;
 393                                 interrupt-parent = <&sic>;
 394                                 interrupts = <9>;
 395                                 clocks = <&refclk>;
 396                                 reg-shift = <2>;
 397                                 pinctrl-0 = <&uart1_pmux>;
 398                                 pinctrl-names = "default";
 399                                 status = "disabled";
 400                         };
 401
 402                         sysctrl: pin-controller@d000 {
 403                                 compatible = "marvell,berlin2q-system-ctrl";
 404                                 reg = <0xd000 0x100>;
 405
 406                                 uart0_pmux: uart0-pmux {
 407                                         groups = "GSM12";
 408                                         function = "uart0";
 409                                 };
 410
 411                                 uart1_pmux: uart1-pmux {
 412                                         groups = "GSM14";
 413                                         function = "uart1";
 414                                 };
 415
 416                                 twsi2_pmux: twsi2-pmux {
 417                                         groups = "GSM13";
 418                                         function = "twsi2";
 419                                 };
 420
 421                                 twsi3_pmux: twsi3-pmux {
 422                                         groups = "GSM14";
 423                                         function = "twsi3";
 424                                 };
 425                         };
 426
 427                         sic: interrupt-controller@e000 {
 428                                 compatible = "snps,dw-apb-ictl";
 429                                 reg = <0xe000 0x30>;
 430                                 interrupt-controller;
 431                                 #interrupt-cells = <1>;
 432                                 interrupt-parent = <&gic>;
 433                                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 434                         };
 435                 };
 436         };
 437 };