1 /include/ "skeleton.dtsi"
3 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
6 compatible = "marvell,dove";
7 model = "Marvell Armada 88AP510 SoC";
8 interrupt-parent = <&intc>;
21 compatible = "marvell,pj4a", "marvell,sheeva-v7";
23 next-level-cache = <&l2>;
29 compatible = "marvell,tauros2-cache";
30 marvell,tauros2-cache-features = <0>;
34 compatible = "marvell,dove-mbus", "marvell,mbus", "simple-bus";
37 controller = <&mbusc>;
38 pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256M MEM space */
39 pcie-io-aperture = <0xf2000000 0x00200000>; /* 2M I/O space */
41 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x0100000 /* MBUS regs 1M */
42 MBUS_ID(0xf0, 0x02) 0 0xf1800000 0x1000000 /* AXI regs 16M */
43 MBUS_ID(0x01, 0xfd) 0 0xf8000000 0x8000000 /* BootROM 128M */
44 MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000 /* CESA SRAM 1M */
45 MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU SRAM 1M */
48 compatible = "simple-bus";
51 ranges = <0x00000000 MBUS_ID(0xf0, 0x01) 0 0x0100000 /* MBUS regs 1M */
52 0x00800000 MBUS_ID(0xf0, 0x02) 0 0x1000000 /* AXI regs 16M */
53 0xffffe000 MBUS_ID(0x03, 0x01) 0 0x0000800 /* CESA SRAM 2k */
54 0xfffff000 MBUS_ID(0x0d, 0x00) 0 0x0000800>; /* PMU SRAM 2k */
56 mbusc: mbus-ctrl@20000 {
57 compatible = "marvell,mbus-controller";
58 reg = <0x20000 0x80>, <0x800100 0x8>;
62 compatible = "marvell,orion-timer";
64 interrupt-parent = <&bridge_intc>;
65 interrupts = <1>, <2>;
66 clocks = <&core_clk 0>;
69 intc: main-interrupt-ctrl@20200 {
70 compatible = "marvell,orion-intc";
72 #interrupt-cells = <1>;
73 reg = <0x20200 0x10>, <0x20210 0x10>;
76 bridge_intc: bridge-interrupt-ctrl@20110 {
77 compatible = "marvell,orion-bridge-intc";
79 #interrupt-cells = <1>;
82 marvell,#interrupts = <5>;
85 core_clk: core-clocks@d0214 {
86 compatible = "marvell,dove-core-clock";
91 gate_clk: clock-gating-ctrl@d0038 {
92 compatible = "marvell,dove-gating-clock";
94 clocks = <&core_clk 0>;
98 thermal: thermal-diode@d001c {
99 compatible = "marvell,dove-thermal";
100 reg = <0xd001c 0x0c>, <0xd005c 0x08>;
103 uart0: serial@12000 {
104 compatible = "ns16550a";
105 reg = <0x12000 0x100>;
108 clocks = <&core_clk 0>;
112 uart1: serial@12100 {
113 compatible = "ns16550a";
114 reg = <0x12100 0x100>;
117 clocks = <&core_clk 0>;
118 pinctrl-0 = <&pmx_uart1>;
119 pinctrl-names = "default";
123 uart2: serial@12200 {
124 compatible = "ns16550a";
125 reg = <0x12000 0x100>;
128 clocks = <&core_clk 0>;
132 uart3: serial@12300 {
133 compatible = "ns16550a";
134 reg = <0x12100 0x100>;
137 clocks = <&core_clk 0>;
141 gpio0: gpio-ctrl@d0400 {
142 compatible = "marvell,orion-gpio";
145 reg = <0xd0400 0x20>;
147 interrupt-controller;
148 #interrupt-cells = <2>;
149 interrupts = <12>, <13>, <14>, <60>;
152 gpio1: gpio-ctrl@d0420 {
153 compatible = "marvell,orion-gpio";
156 reg = <0xd0420 0x20>;
158 interrupt-controller;
159 #interrupt-cells = <2>;
163 gpio2: gpio-ctrl@e8400 {
164 compatible = "marvell,orion-gpio";
167 reg = <0xe8400 0x0c>;
171 pinctrl: pin-ctrl@d0200 {
172 compatible = "marvell,dove-pinctrl";
173 reg = <0xd0200 0x10>;
174 clocks = <&gate_clk 22>;
176 pmx_gpio_0: pmx-gpio-0 {
177 marvell,pins = "mpp0";
178 marvell,function = "gpio";
181 pmx_gpio_1: pmx-gpio-1 {
182 marvell,pins = "mpp1";
183 marvell,function = "gpio";
186 pmx_gpio_2: pmx-gpio-2 {
187 marvell,pins = "mpp2";
188 marvell,function = "gpio";
191 pmx_gpio_3: pmx-gpio-3 {
192 marvell,pins = "mpp3";
193 marvell,function = "gpio";
196 pmx_gpio_4: pmx-gpio-4 {
197 marvell,pins = "mpp4";
198 marvell,function = "gpio";
201 pmx_gpio_5: pmx-gpio-5 {
202 marvell,pins = "mpp5";
203 marvell,function = "gpio";
206 pmx_gpio_6: pmx-gpio-6 {
207 marvell,pins = "mpp6";
208 marvell,function = "gpio";
211 pmx_gpio_7: pmx-gpio-7 {
212 marvell,pins = "mpp7";
213 marvell,function = "gpio";
216 pmx_gpio_8: pmx-gpio-8 {
217 marvell,pins = "mpp8";
218 marvell,function = "gpio";
221 pmx_gpio_9: pmx-gpio-9 {
222 marvell,pins = "mpp9";
223 marvell,function = "gpio";
226 pmx_gpio_10: pmx-gpio-10 {
227 marvell,pins = "mpp10";
228 marvell,function = "gpio";
231 pmx_gpio_11: pmx-gpio-11 {
232 marvell,pins = "mpp11";
233 marvell,function = "gpio";
236 pmx_gpio_12: pmx-gpio-12 {
237 marvell,pins = "mpp12";
238 marvell,function = "gpio";
241 pmx_gpio_13: pmx-gpio-13 {
242 marvell,pins = "mpp13";
243 marvell,function = "gpio";
246 pmx_gpio_14: pmx-gpio-14 {
247 marvell,pins = "mpp14";
248 marvell,function = "gpio";
251 pmx_gpio_15: pmx-gpio-15 {
252 marvell,pins = "mpp15";
253 marvell,function = "gpio";
256 pmx_gpio_16: pmx-gpio-16 {
257 marvell,pins = "mpp16";
258 marvell,function = "gpio";
261 pmx_gpio_17: pmx-gpio-17 {
262 marvell,pins = "mpp17";
263 marvell,function = "gpio";
266 pmx_gpio_18: pmx-gpio-18 {
267 marvell,pins = "mpp18";
268 marvell,function = "gpio";
271 pmx_gpio_19: pmx-gpio-19 {
272 marvell,pins = "mpp19";
273 marvell,function = "gpio";
276 pmx_gpio_20: pmx-gpio-20 {
277 marvell,pins = "mpp20";
278 marvell,function = "gpio";
281 pmx_gpio_21: pmx-gpio-21 {
282 marvell,pins = "mpp21";
283 marvell,function = "gpio";
286 pmx_camera: pmx-camera {
287 marvell,pins = "mpp_camera";
288 marvell,function = "camera";
291 pmx_camera_gpio: pmx-camera-gpio {
292 marvell,pins = "mpp_camera";
293 marvell,function = "gpio";
296 pmx_sdio0: pmx-sdio0 {
297 marvell,pins = "mpp_sdio0";
298 marvell,function = "sdio0";
301 pmx_sdio0_gpio: pmx-sdio0-gpio {
302 marvell,pins = "mpp_sdio0";
303 marvell,function = "gpio";
306 pmx_sdio1: pmx-sdio1 {
307 marvell,pins = "mpp_sdio1";
308 marvell,function = "sdio1";
311 pmx_sdio1_gpio: pmx-sdio1-gpio {
312 marvell,pins = "mpp_sdio1";
313 marvell,function = "gpio";
316 pmx_audio1_gpio: pmx-audio1-gpio {
317 marvell,pins = "mpp_audio1";
318 marvell,function = "gpio";
322 marvell,pins = "mpp_spi0";
323 marvell,function = "spi0";
326 pmx_spi0_gpio: pmx-spi0-gpio {
327 marvell,pins = "mpp_spi0";
328 marvell,function = "gpio";
331 pmx_uart1: pmx-uart1 {
332 marvell,pins = "mpp_uart1";
333 marvell,function = "uart1";
336 pmx_uart1_gpio: pmx-uart1-gpio {
337 marvell,pins = "mpp_uart1";
338 marvell,function = "gpio";
342 marvell,pins = "mpp_nand";
343 marvell,function = "nand";
346 pmx_nand_gpo: pmx-nand-gpo {
347 marvell,pins = "mpp_nand";
348 marvell,function = "gpo";
352 spi0: spi-ctrl@10600 {
353 compatible = "marvell,orion-spi";
354 #address-cells = <1>;
358 reg = <0x10600 0x28>;
359 clocks = <&core_clk 0>;
360 pinctrl-0 = <&pmx_spi0>;
361 pinctrl-names = "default";
365 spi1: spi-ctrl@14600 {
366 compatible = "marvell,orion-spi";
367 #address-cells = <1>;
371 reg = <0x14600 0x28>;
372 clocks = <&core_clk 0>;
376 i2c0: i2c-ctrl@11000 {
377 compatible = "marvell,mv64xxx-i2c";
378 reg = <0x11000 0x20>;
379 #address-cells = <1>;
382 clock-frequency = <400000>;
384 clocks = <&core_clk 0>;
388 ehci0: usb-host@50000 {
389 compatible = "marvell,orion-ehci";
390 reg = <0x50000 0x1000>;
392 clocks = <&gate_clk 0>;
396 ehci1: usb-host@51000 {
397 compatible = "marvell,orion-ehci";
398 reg = <0x51000 0x1000>;
400 clocks = <&gate_clk 1>;
404 sdio0: sdio-host@92000 {
405 compatible = "marvell,dove-sdhci";
406 reg = <0x92000 0x100>;
407 interrupts = <35>, <37>;
408 clocks = <&gate_clk 8>;
409 pinctrl-0 = <&pmx_sdio0>;
410 pinctrl-names = "default";
414 sdio1: sdio-host@90000 {
415 compatible = "marvell,dove-sdhci";
416 reg = <0x90000 0x100>;
417 interrupts = <36>, <38>;
418 clocks = <&gate_clk 9>;
419 pinctrl-0 = <&pmx_sdio1>;
420 pinctrl-names = "default";
424 sata0: sata-host@a0000 {
425 compatible = "marvell,orion-sata";
426 reg = <0xa0000 0x2400>;
428 clocks = <&gate_clk 3>;
433 rtc: real-time-clock@d8500 {
434 compatible = "marvell,orion-rtc";
435 reg = <0xd8500 0x20>;
438 crypto: crypto-engine@30000 {
439 compatible = "marvell,orion-crypto";
440 reg = <0x30000 0x10000>,
442 reg-names = "regs", "sram";
444 clocks = <&gate_clk 15>;
448 xor0: dma-engine@60800 {
449 compatible = "marvell,orion-xor";
452 clocks = <&gate_clk 23>;
468 xor1: dma-engine@60900 {
469 compatible = "marvell,orion-xor";
472 clocks = <&gate_clk 24>;
488 mdio: mdio-bus@72004 {
489 compatible = "marvell,orion-mdio";
490 #address-cells = <1>;
492 reg = <0x72004 0x84>;
494 clocks = <&gate_clk 2>;
497 ethphy: ethernet-phy {
498 device-type = "ethernet-phy";
499 /* set phy address in board file */
503 eth: ethernet-ctrl@72000 {
504 compatible = "marvell,orion-eth";
505 #address-cells = <1>;
507 reg = <0x72000 0x4000>;
508 clocks = <&gate_clk 2>;
509 marvell,tx-checksum-limit = <1600>;
513 device_type = "network";
514 compatible = "marvell,orion-eth-port";
517 /* overwrite MAC address in bootloader */
518 local-mac-address = [00 00 00 00 00 00];
519 phy-handle = <ðphy>;