1 /include/ "skeleton.dtsi"
3 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
6 compatible = "marvell,dove";
7 model = "Marvell Armada 88AP510 SoC";
8 interrupt-parent = <&intc>;
21 compatible = "marvell,pj4a", "marvell,sheeva-v7";
23 next-level-cache = <&l2>;
29 compatible = "marvell,tauros2-cache";
30 marvell,tauros2-cache-features = <0>;
34 compatible = "marvell,dove-mbus", "marvell,mbus", "simple-bus";
37 controller = <&mbusc>;
38 pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256M MEM space */
39 pcie-io-aperture = <0xf2000000 0x00200000>; /* 2M I/O space */
41 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x0100000 /* MBUS regs 1M */
42 MBUS_ID(0xf0, 0x02) 0 0xf1800000 0x1000000 /* AXI regs 16M */
43 MBUS_ID(0x01, 0xfd) 0 0xf8000000 0x8000000 /* BootROM 128M */
44 MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000 /* CESA SRAM 1M */
45 MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU SRAM 1M */
47 pcie: pcie-controller {
48 compatible = "marvell,dove-pcie";
55 bus-range = <0x00 0xff>;
57 ranges = <0x82000000 0x0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x2000
58 0x82000000 0x0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x2000
59 0x82000000 0x1 0x0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 Mem */
60 0x81000000 0x1 0x0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 I/O */
61 0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 Mem */
62 0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */
67 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
68 reg = <0x0800 0 0 0 0>;
69 clocks = <&gate_clk 4>;
70 marvell,pcie-port = <0>;
74 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
75 0x81000000 0 0 0x81000000 0x1 0 1 0>;
77 #interrupt-cells = <1>;
78 interrupt-map-mask = <0 0 0 0>;
79 interrupt-map = <0 0 0 0 &intc 16>;
85 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
86 reg = <0x1000 0 0 0 0>;
87 clocks = <&gate_clk 5>;
88 marvell,pcie-port = <1>;
92 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
93 0x81000000 0 0 0x81000000 0x2 0 1 0>;
95 #interrupt-cells = <1>;
96 interrupt-map-mask = <0 0 0 0>;
97 interrupt-map = <0 0 0 0 &intc 18>;
102 compatible = "simple-bus";
103 #address-cells = <1>;
105 ranges = <0x00000000 MBUS_ID(0xf0, 0x01) 0 0x0100000 /* MBUS regs 1M */
106 0x00800000 MBUS_ID(0xf0, 0x02) 0 0x1000000 /* AXI regs 16M */
107 0xffffe000 MBUS_ID(0x03, 0x01) 0 0x0000800 /* CESA SRAM 2k */
108 0xfffff000 MBUS_ID(0x0d, 0x00) 0 0x0000800>; /* PMU SRAM 2k */
110 mbusc: mbus-ctrl@20000 {
111 compatible = "marvell,mbus-controller";
112 reg = <0x20000 0x80>, <0x800100 0x8>;
116 compatible = "marvell,orion-timer";
117 reg = <0x20300 0x20>;
118 interrupt-parent = <&bridge_intc>;
119 interrupts = <1>, <2>;
120 clocks = <&core_clk 0>;
123 intc: main-interrupt-ctrl@20200 {
124 compatible = "marvell,orion-intc";
125 interrupt-controller;
126 #interrupt-cells = <1>;
127 reg = <0x20200 0x10>, <0x20210 0x10>;
130 bridge_intc: bridge-interrupt-ctrl@20110 {
131 compatible = "marvell,orion-bridge-intc";
132 interrupt-controller;
133 #interrupt-cells = <1>;
136 marvell,#interrupts = <5>;
139 core_clk: core-clocks@d0214 {
140 compatible = "marvell,dove-core-clock";
145 gate_clk: clock-gating-ctrl@d0038 {
146 compatible = "marvell,dove-gating-clock";
148 clocks = <&core_clk 0>;
152 thermal: thermal-diode@d001c {
153 compatible = "marvell,dove-thermal";
154 reg = <0xd001c 0x0c>, <0xd005c 0x08>;
157 uart0: serial@12000 {
158 compatible = "ns16550a";
159 reg = <0x12000 0x100>;
162 clocks = <&core_clk 0>;
166 uart1: serial@12100 {
167 compatible = "ns16550a";
168 reg = <0x12100 0x100>;
171 clocks = <&core_clk 0>;
172 pinctrl-0 = <&pmx_uart1>;
173 pinctrl-names = "default";
177 uart2: serial@12200 {
178 compatible = "ns16550a";
179 reg = <0x12000 0x100>;
182 clocks = <&core_clk 0>;
186 uart3: serial@12300 {
187 compatible = "ns16550a";
188 reg = <0x12100 0x100>;
191 clocks = <&core_clk 0>;
195 gpio0: gpio-ctrl@d0400 {
196 compatible = "marvell,orion-gpio";
199 reg = <0xd0400 0x20>;
201 interrupt-controller;
202 #interrupt-cells = <2>;
203 interrupts = <12>, <13>, <14>, <60>;
206 gpio1: gpio-ctrl@d0420 {
207 compatible = "marvell,orion-gpio";
210 reg = <0xd0420 0x20>;
212 interrupt-controller;
213 #interrupt-cells = <2>;
217 gpio2: gpio-ctrl@e8400 {
218 compatible = "marvell,orion-gpio";
221 reg = <0xe8400 0x0c>;
225 pinctrl: pin-ctrl@d0200 {
226 compatible = "marvell,dove-pinctrl";
227 reg = <0xd0200 0x10>;
228 clocks = <&gate_clk 22>;
230 pmx_gpio_0: pmx-gpio-0 {
231 marvell,pins = "mpp0";
232 marvell,function = "gpio";
235 pmx_gpio_1: pmx-gpio-1 {
236 marvell,pins = "mpp1";
237 marvell,function = "gpio";
240 pmx_gpio_2: pmx-gpio-2 {
241 marvell,pins = "mpp2";
242 marvell,function = "gpio";
245 pmx_gpio_3: pmx-gpio-3 {
246 marvell,pins = "mpp3";
247 marvell,function = "gpio";
250 pmx_gpio_4: pmx-gpio-4 {
251 marvell,pins = "mpp4";
252 marvell,function = "gpio";
255 pmx_gpio_5: pmx-gpio-5 {
256 marvell,pins = "mpp5";
257 marvell,function = "gpio";
260 pmx_gpio_6: pmx-gpio-6 {
261 marvell,pins = "mpp6";
262 marvell,function = "gpio";
265 pmx_gpio_7: pmx-gpio-7 {
266 marvell,pins = "mpp7";
267 marvell,function = "gpio";
270 pmx_gpio_8: pmx-gpio-8 {
271 marvell,pins = "mpp8";
272 marvell,function = "gpio";
275 pmx_gpio_9: pmx-gpio-9 {
276 marvell,pins = "mpp9";
277 marvell,function = "gpio";
280 pmx_gpio_10: pmx-gpio-10 {
281 marvell,pins = "mpp10";
282 marvell,function = "gpio";
285 pmx_gpio_11: pmx-gpio-11 {
286 marvell,pins = "mpp11";
287 marvell,function = "gpio";
290 pmx_gpio_12: pmx-gpio-12 {
291 marvell,pins = "mpp12";
292 marvell,function = "gpio";
295 pmx_gpio_13: pmx-gpio-13 {
296 marvell,pins = "mpp13";
297 marvell,function = "gpio";
300 pmx_gpio_14: pmx-gpio-14 {
301 marvell,pins = "mpp14";
302 marvell,function = "gpio";
305 pmx_gpio_15: pmx-gpio-15 {
306 marvell,pins = "mpp15";
307 marvell,function = "gpio";
310 pmx_gpio_16: pmx-gpio-16 {
311 marvell,pins = "mpp16";
312 marvell,function = "gpio";
315 pmx_gpio_17: pmx-gpio-17 {
316 marvell,pins = "mpp17";
317 marvell,function = "gpio";
320 pmx_gpio_18: pmx-gpio-18 {
321 marvell,pins = "mpp18";
322 marvell,function = "gpio";
325 pmx_gpio_19: pmx-gpio-19 {
326 marvell,pins = "mpp19";
327 marvell,function = "gpio";
330 pmx_gpio_20: pmx-gpio-20 {
331 marvell,pins = "mpp20";
332 marvell,function = "gpio";
335 pmx_gpio_21: pmx-gpio-21 {
336 marvell,pins = "mpp21";
337 marvell,function = "gpio";
340 pmx_camera: pmx-camera {
341 marvell,pins = "mpp_camera";
342 marvell,function = "camera";
345 pmx_camera_gpio: pmx-camera-gpio {
346 marvell,pins = "mpp_camera";
347 marvell,function = "gpio";
350 pmx_sdio0: pmx-sdio0 {
351 marvell,pins = "mpp_sdio0";
352 marvell,function = "sdio0";
355 pmx_sdio0_gpio: pmx-sdio0-gpio {
356 marvell,pins = "mpp_sdio0";
357 marvell,function = "gpio";
360 pmx_sdio1: pmx-sdio1 {
361 marvell,pins = "mpp_sdio1";
362 marvell,function = "sdio1";
365 pmx_sdio1_gpio: pmx-sdio1-gpio {
366 marvell,pins = "mpp_sdio1";
367 marvell,function = "gpio";
370 pmx_audio1_gpio: pmx-audio1-gpio {
371 marvell,pins = "mpp_audio1";
372 marvell,function = "gpio";
376 marvell,pins = "mpp_spi0";
377 marvell,function = "spi0";
380 pmx_spi0_gpio: pmx-spi0-gpio {
381 marvell,pins = "mpp_spi0";
382 marvell,function = "gpio";
385 pmx_uart1: pmx-uart1 {
386 marvell,pins = "mpp_uart1";
387 marvell,function = "uart1";
390 pmx_uart1_gpio: pmx-uart1-gpio {
391 marvell,pins = "mpp_uart1";
392 marvell,function = "gpio";
396 marvell,pins = "mpp_nand";
397 marvell,function = "nand";
400 pmx_nand_gpo: pmx-nand-gpo {
401 marvell,pins = "mpp_nand";
402 marvell,function = "gpo";
406 spi0: spi-ctrl@10600 {
407 compatible = "marvell,orion-spi";
408 #address-cells = <1>;
412 reg = <0x10600 0x28>;
413 clocks = <&core_clk 0>;
414 pinctrl-0 = <&pmx_spi0>;
415 pinctrl-names = "default";
419 spi1: spi-ctrl@14600 {
420 compatible = "marvell,orion-spi";
421 #address-cells = <1>;
425 reg = <0x14600 0x28>;
426 clocks = <&core_clk 0>;
430 i2c0: i2c-ctrl@11000 {
431 compatible = "marvell,mv64xxx-i2c";
432 reg = <0x11000 0x20>;
433 #address-cells = <1>;
436 clock-frequency = <400000>;
438 clocks = <&core_clk 0>;
442 ehci0: usb-host@50000 {
443 compatible = "marvell,orion-ehci";
444 reg = <0x50000 0x1000>;
446 clocks = <&gate_clk 0>;
450 ehci1: usb-host@51000 {
451 compatible = "marvell,orion-ehci";
452 reg = <0x51000 0x1000>;
454 clocks = <&gate_clk 1>;
458 sdio0: sdio-host@92000 {
459 compatible = "marvell,dove-sdhci";
460 reg = <0x92000 0x100>;
461 interrupts = <35>, <37>;
462 clocks = <&gate_clk 8>;
463 pinctrl-0 = <&pmx_sdio0>;
464 pinctrl-names = "default";
468 sdio1: sdio-host@90000 {
469 compatible = "marvell,dove-sdhci";
470 reg = <0x90000 0x100>;
471 interrupts = <36>, <38>;
472 clocks = <&gate_clk 9>;
473 pinctrl-0 = <&pmx_sdio1>;
474 pinctrl-names = "default";
478 sata0: sata-host@a0000 {
479 compatible = "marvell,orion-sata";
480 reg = <0xa0000 0x2400>;
482 clocks = <&gate_clk 3>;
487 rtc: real-time-clock@d8500 {
488 compatible = "marvell,orion-rtc";
489 reg = <0xd8500 0x20>;
492 crypto: crypto-engine@30000 {
493 compatible = "marvell,orion-crypto";
494 reg = <0x30000 0x10000>,
496 reg-names = "regs", "sram";
498 clocks = <&gate_clk 15>;
502 xor0: dma-engine@60800 {
503 compatible = "marvell,orion-xor";
506 clocks = <&gate_clk 23>;
522 xor1: dma-engine@60900 {
523 compatible = "marvell,orion-xor";
526 clocks = <&gate_clk 24>;
542 mdio: mdio-bus@72004 {
543 compatible = "marvell,orion-mdio";
544 #address-cells = <1>;
546 reg = <0x72004 0x84>;
548 clocks = <&gate_clk 2>;
551 ethphy: ethernet-phy {
552 device-type = "ethernet-phy";
553 /* set phy address in board file */
557 eth: ethernet-ctrl@72000 {
558 compatible = "marvell,orion-eth";
559 #address-cells = <1>;
561 reg = <0x72000 0x4000>;
562 clocks = <&gate_clk 2>;
563 marvell,tx-checksum-limit = <1600>;
567 device_type = "network";
568 compatible = "marvell,orion-eth-port";
571 /* overwrite MAC address in bootloader */
572 local-mac-address = [00 00 00 00 00 00];
573 phy-handle = <ðphy>;