2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h>
13 #include "skeleton.dtsi"
15 #define MAX_SOURCES 400
16 #define DIRECT_IRQ(irq) (MAX_SOURCES + irq)
22 compatible = "ti,dra7xx";
23 interrupt-parent = <&gic>;
41 ethernet0 = &cpsw_emac0;
42 ethernet1 = &cpsw_emac1;
48 compatible = "arm,armv7-timer";
49 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
50 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
51 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
52 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
55 gic: interrupt-controller@48211000 {
56 compatible = "arm,cortex-a15-gic";
58 #interrupt-cells = <3>;
59 arm,routable-irqs = <192>;
60 reg = <0x48211000 0x1000>,
64 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
68 * The soc node represents the soc top level view. It is used for IPs
69 * that are not memory mapped in the MPU view or for the MPU itself.
72 compatible = "ti,omap-infra";
74 compatible = "ti,omap5-mpu";
80 * XXX: Use a flat representation of the SOC interconnect.
81 * The real OMAP interconnect network is quite complex.
82 * Since it will not bring real advantage to represent that in DT for
83 * the moment, just use a fake OCP bus entry to represent the whole bus
87 compatible = "ti,dra7-l3-noc", "simple-bus";
91 ti,hwmods = "l3_main_1", "l3_main_2";
92 reg = <0x44000000 0x1000000>,
94 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
95 <GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH>;
98 compatible = "ti,dra7-prm";
99 reg = <0x4ae06000 0x3000>;
100 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
103 #address-cells = <1>;
107 prm_clockdomains: clockdomains {
112 compatible = "simple-bus";
114 #address-cells = <1>;
115 ranges = <0x51000000 0x51000000 0x3000
116 0x0 0x20000000 0x10000000>;
118 compatible = "ti,dra7-pcie";
119 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
120 reg-names = "rc_dbics", "ti_conf", "config";
121 interrupts = <0 232 0x4>, <0 233 0x4>;
122 #address-cells = <3>;
125 ranges = <0x81000000 0 0 0x03000 0 0x00010000
126 0x82000000 0 0x20013000 0x13000 0 0xffed000>;
127 #interrupt-cells = <1>;
131 phy-names = "pcie-phy0";
132 interrupt-map-mask = <0 0 0 7>;
133 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
134 <0 0 0 2 &pcie1_intc 2>,
135 <0 0 0 3 &pcie1_intc 3>,
136 <0 0 0 4 &pcie1_intc 4>;
137 pcie1_intc: interrupt-controller {
138 interrupt-controller;
139 #address-cells = <0>;
140 #interrupt-cells = <1>;
146 compatible = "simple-bus";
148 #address-cells = <1>;
149 ranges = <0x51800000 0x51800000 0x3000
150 0x0 0x30000000 0x10000000>;
153 compatible = "ti,dra7-pcie";
154 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
155 reg-names = "rc_dbics", "ti_conf", "config";
156 interrupts = <0 355 0x4>, <0 356 0x4>;
157 #address-cells = <3>;
160 ranges = <0x81000000 0 0 0x03000 0 0x00010000
161 0x82000000 0 0x30013000 0x13000 0 0xffed000>;
162 #interrupt-cells = <1>;
166 phy-names = "pcie-phy0";
167 interrupt-map-mask = <0 0 0 7>;
168 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
169 <0 0 0 2 &pcie2_intc 2>,
170 <0 0 0 3 &pcie2_intc 3>,
171 <0 0 0 4 &pcie2_intc 4>;
172 pcie2_intc: interrupt-controller {
173 interrupt-controller;
174 #address-cells = <0>;
175 #interrupt-cells = <1>;
180 cm_core_aon: cm_core_aon@4a005000 {
181 compatible = "ti,dra7-cm-core-aon";
182 reg = <0x4a005000 0x2000>;
184 cm_core_aon_clocks: clocks {
185 #address-cells = <1>;
189 cm_core_aon_clockdomains: clockdomains {
193 cm_core: cm_core@4a008000 {
194 compatible = "ti,dra7-cm-core";
195 reg = <0x4a008000 0x3000>;
197 cm_core_clocks: clocks {
198 #address-cells = <1>;
202 cm_core_clockdomains: clockdomains {
206 counter32k: counter@4ae04000 {
207 compatible = "ti,omap-counter32k";
208 reg = <0x4ae04000 0x40>;
209 ti,hwmods = "counter_32k";
212 dra7_ctrl_core: ctrl_core@4a002000 {
213 compatible = "syscon";
214 reg = <0x4a002000 0x6d0>;
217 dra7_ctrl_general: tisyscon@4a002e00 {
218 compatible = "syscon";
219 reg = <0x4a002e00 0x7c>;
222 pbias_regulator: pbias_regulator {
223 compatible = "ti,pbias-omap";
225 syscon = <&dra7_ctrl_general>;
226 pbias_mmc_reg: pbias_mmc_omap5 {
227 regulator-name = "pbias_mmc_omap5";
228 regulator-min-microvolt = <1800000>;
229 regulator-max-microvolt = <3000000>;
233 dra7_pmx_core: pinmux@4a003400 {
234 compatible = "ti,dra7-padconf", "pinctrl-single";
235 reg = <0x4a003400 0x0464>;
236 #address-cells = <1>;
238 #interrupt-cells = <1>;
239 interrupt-controller;
240 pinctrl-single,register-width = <32>;
241 pinctrl-single,function-mask = <0x3fffffff>;
244 sdma: dma-controller@4a056000 {
245 compatible = "ti,omap4430-sdma";
246 reg = <0x4a056000 0x1000>;
247 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
248 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
249 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
253 dma-requests = <127>;
256 gpio1: gpio@4ae10000 {
257 compatible = "ti,omap4-gpio";
258 reg = <0x4ae10000 0x200>;
259 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
263 interrupt-controller;
264 #interrupt-cells = <2>;
267 gpio2: gpio@48055000 {
268 compatible = "ti,omap4-gpio";
269 reg = <0x48055000 0x200>;
270 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
274 interrupt-controller;
275 #interrupt-cells = <2>;
278 gpio3: gpio@48057000 {
279 compatible = "ti,omap4-gpio";
280 reg = <0x48057000 0x200>;
281 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
285 interrupt-controller;
286 #interrupt-cells = <2>;
289 gpio4: gpio@48059000 {
290 compatible = "ti,omap4-gpio";
291 reg = <0x48059000 0x200>;
292 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
296 interrupt-controller;
297 #interrupt-cells = <2>;
300 gpio5: gpio@4805b000 {
301 compatible = "ti,omap4-gpio";
302 reg = <0x4805b000 0x200>;
303 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
307 interrupt-controller;
308 #interrupt-cells = <2>;
311 gpio6: gpio@4805d000 {
312 compatible = "ti,omap4-gpio";
313 reg = <0x4805d000 0x200>;
314 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
318 interrupt-controller;
319 #interrupt-cells = <2>;
322 gpio7: gpio@48051000 {
323 compatible = "ti,omap4-gpio";
324 reg = <0x48051000 0x200>;
325 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
329 interrupt-controller;
330 #interrupt-cells = <2>;
333 gpio8: gpio@48053000 {
334 compatible = "ti,omap4-gpio";
335 reg = <0x48053000 0x200>;
336 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
340 interrupt-controller;
341 #interrupt-cells = <2>;
344 uart1: serial@4806a000 {
345 compatible = "ti,omap4-uart";
346 reg = <0x4806a000 0x100>;
347 interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
349 clock-frequency = <48000000>;
351 dmas = <&sdma 49>, <&sdma 50>;
352 dma-names = "tx", "rx";
355 uart2: serial@4806c000 {
356 compatible = "ti,omap4-uart";
357 reg = <0x4806c000 0x100>;
358 interrupts-extended = <&gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
360 clock-frequency = <48000000>;
362 dmas = <&sdma 51>, <&sdma 52>;
363 dma-names = "tx", "rx";
366 uart3: serial@48020000 {
367 compatible = "ti,omap4-uart";
368 reg = <0x48020000 0x100>;
369 interrupts-extended = <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
371 clock-frequency = <48000000>;
373 dmas = <&sdma 53>, <&sdma 54>;
374 dma-names = "tx", "rx";
377 uart4: serial@4806e000 {
378 compatible = "ti,omap4-uart";
379 reg = <0x4806e000 0x100>;
380 interrupts-extended = <&gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
382 clock-frequency = <48000000>;
384 dmas = <&sdma 55>, <&sdma 56>;
385 dma-names = "tx", "rx";
388 uart5: serial@48066000 {
389 compatible = "ti,omap4-uart";
390 reg = <0x48066000 0x100>;
391 interrupts-extended = <&gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
393 clock-frequency = <48000000>;
395 dmas = <&sdma 63>, <&sdma 64>;
396 dma-names = "tx", "rx";
399 uart6: serial@48068000 {
400 compatible = "ti,omap4-uart";
401 reg = <0x48068000 0x100>;
402 interrupts-extended = <&gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
404 clock-frequency = <48000000>;
406 dmas = <&sdma 79>, <&sdma 80>;
407 dma-names = "tx", "rx";
410 uart7: serial@48420000 {
411 compatible = "ti,omap4-uart";
412 reg = <0x48420000 0x100>;
413 interrupts-extended = <&gic GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
415 clock-frequency = <48000000>;
419 uart8: serial@48422000 {
420 compatible = "ti,omap4-uart";
421 reg = <0x48422000 0x100>;
422 interrupts-extended = <&gic GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
424 clock-frequency = <48000000>;
428 uart9: serial@48424000 {
429 compatible = "ti,omap4-uart";
430 reg = <0x48424000 0x100>;
431 interrupts-extended = <&gic GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
433 clock-frequency = <48000000>;
437 uart10: serial@4ae2b000 {
438 compatible = "ti,omap4-uart";
439 reg = <0x4ae2b000 0x100>;
440 interrupts-extended = <&gic GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
441 ti,hwmods = "uart10";
442 clock-frequency = <48000000>;
446 mailbox1: mailbox@4a0f4000 {
447 compatible = "ti,omap4-mailbox";
448 reg = <0x4a0f4000 0x200>;
449 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
450 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
451 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
452 ti,hwmods = "mailbox1";
454 ti,mbox-num-users = <3>;
455 ti,mbox-num-fifos = <8>;
459 mailbox2: mailbox@4883a000 {
460 compatible = "ti,omap4-mailbox";
461 reg = <0x4883a000 0x200>;
462 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
463 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
464 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
465 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
466 ti,hwmods = "mailbox2";
468 ti,mbox-num-users = <4>;
469 ti,mbox-num-fifos = <12>;
473 mailbox3: mailbox@4883c000 {
474 compatible = "ti,omap4-mailbox";
475 reg = <0x4883c000 0x200>;
476 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
477 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
478 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
479 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
480 ti,hwmods = "mailbox3";
482 ti,mbox-num-users = <4>;
483 ti,mbox-num-fifos = <12>;
487 mailbox4: mailbox@4883e000 {
488 compatible = "ti,omap4-mailbox";
489 reg = <0x4883e000 0x200>;
490 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
491 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
492 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
493 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
494 ti,hwmods = "mailbox4";
496 ti,mbox-num-users = <4>;
497 ti,mbox-num-fifos = <12>;
501 mailbox5: mailbox@48840000 {
502 compatible = "ti,omap4-mailbox";
503 reg = <0x48840000 0x200>;
504 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
505 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
506 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
507 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
508 ti,hwmods = "mailbox5";
510 ti,mbox-num-users = <4>;
511 ti,mbox-num-fifos = <12>;
515 mailbox6: mailbox@48842000 {
516 compatible = "ti,omap4-mailbox";
517 reg = <0x48842000 0x200>;
518 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
519 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
520 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
521 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
522 ti,hwmods = "mailbox6";
524 ti,mbox-num-users = <4>;
525 ti,mbox-num-fifos = <12>;
529 mailbox7: mailbox@48844000 {
530 compatible = "ti,omap4-mailbox";
531 reg = <0x48844000 0x200>;
532 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
533 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
534 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
535 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
536 ti,hwmods = "mailbox7";
538 ti,mbox-num-users = <4>;
539 ti,mbox-num-fifos = <12>;
543 mailbox8: mailbox@48846000 {
544 compatible = "ti,omap4-mailbox";
545 reg = <0x48846000 0x200>;
546 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
547 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
548 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
549 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
550 ti,hwmods = "mailbox8";
552 ti,mbox-num-users = <4>;
553 ti,mbox-num-fifos = <12>;
557 mailbox9: mailbox@4885e000 {
558 compatible = "ti,omap4-mailbox";
559 reg = <0x4885e000 0x200>;
560 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
561 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
562 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
563 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
564 ti,hwmods = "mailbox9";
566 ti,mbox-num-users = <4>;
567 ti,mbox-num-fifos = <12>;
571 mailbox10: mailbox@48860000 {
572 compatible = "ti,omap4-mailbox";
573 reg = <0x48860000 0x200>;
574 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
575 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
576 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
577 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
578 ti,hwmods = "mailbox10";
580 ti,mbox-num-users = <4>;
581 ti,mbox-num-fifos = <12>;
585 mailbox11: mailbox@48862000 {
586 compatible = "ti,omap4-mailbox";
587 reg = <0x48862000 0x200>;
588 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
589 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
590 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
591 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
592 ti,hwmods = "mailbox11";
594 ti,mbox-num-users = <4>;
595 ti,mbox-num-fifos = <12>;
599 mailbox12: mailbox@48864000 {
600 compatible = "ti,omap4-mailbox";
601 reg = <0x48864000 0x200>;
602 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
603 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
604 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
605 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
606 ti,hwmods = "mailbox12";
608 ti,mbox-num-users = <4>;
609 ti,mbox-num-fifos = <12>;
613 mailbox13: mailbox@48802000 {
614 compatible = "ti,omap4-mailbox";
615 reg = <0x48802000 0x200>;
616 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
617 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
618 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
619 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
620 ti,hwmods = "mailbox13";
622 ti,mbox-num-users = <4>;
623 ti,mbox-num-fifos = <12>;
627 timer1: timer@4ae18000 {
628 compatible = "ti,omap5430-timer";
629 reg = <0x4ae18000 0x80>;
630 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
631 ti,hwmods = "timer1";
635 timer2: timer@48032000 {
636 compatible = "ti,omap5430-timer";
637 reg = <0x48032000 0x80>;
638 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
639 ti,hwmods = "timer2";
642 timer3: timer@48034000 {
643 compatible = "ti,omap5430-timer";
644 reg = <0x48034000 0x80>;
645 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
646 ti,hwmods = "timer3";
649 timer4: timer@48036000 {
650 compatible = "ti,omap5430-timer";
651 reg = <0x48036000 0x80>;
652 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
653 ti,hwmods = "timer4";
656 timer5: timer@48820000 {
657 compatible = "ti,omap5430-timer";
658 reg = <0x48820000 0x80>;
659 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
660 ti,hwmods = "timer5";
663 timer6: timer@48822000 {
664 compatible = "ti,omap5430-timer";
665 reg = <0x48822000 0x80>;
666 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
667 ti,hwmods = "timer6";
670 timer7: timer@48824000 {
671 compatible = "ti,omap5430-timer";
672 reg = <0x48824000 0x80>;
673 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
674 ti,hwmods = "timer7";
677 timer8: timer@48826000 {
678 compatible = "ti,omap5430-timer";
679 reg = <0x48826000 0x80>;
680 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
681 ti,hwmods = "timer8";
684 timer9: timer@4803e000 {
685 compatible = "ti,omap5430-timer";
686 reg = <0x4803e000 0x80>;
687 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
688 ti,hwmods = "timer9";
691 timer10: timer@48086000 {
692 compatible = "ti,omap5430-timer";
693 reg = <0x48086000 0x80>;
694 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
695 ti,hwmods = "timer10";
698 timer11: timer@48088000 {
699 compatible = "ti,omap5430-timer";
700 reg = <0x48088000 0x80>;
701 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
702 ti,hwmods = "timer11";
705 timer13: timer@48828000 {
706 compatible = "ti,omap5430-timer";
707 reg = <0x48828000 0x80>;
708 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
709 ti,hwmods = "timer13";
713 timer14: timer@4882a000 {
714 compatible = "ti,omap5430-timer";
715 reg = <0x4882a000 0x80>;
716 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
717 ti,hwmods = "timer14";
721 timer15: timer@4882c000 {
722 compatible = "ti,omap5430-timer";
723 reg = <0x4882c000 0x80>;
724 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
725 ti,hwmods = "timer15";
729 timer16: timer@4882e000 {
730 compatible = "ti,omap5430-timer";
731 reg = <0x4882e000 0x80>;
732 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
733 ti,hwmods = "timer16";
738 compatible = "ti,omap3-wdt";
739 reg = <0x4ae14000 0x80>;
740 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
741 ti,hwmods = "wd_timer2";
744 hwspinlock: spinlock@4a0f6000 {
745 compatible = "ti,omap4-hwspinlock";
746 reg = <0x4a0f6000 0x1000>;
747 ti,hwmods = "spinlock";
752 compatible = "ti,omap5-dmm";
753 reg = <0x4e000000 0x800>;
754 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
759 compatible = "ti,omap4-i2c";
760 reg = <0x48070000 0x100>;
761 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
762 #address-cells = <1>;
769 compatible = "ti,omap4-i2c";
770 reg = <0x48072000 0x100>;
771 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
772 #address-cells = <1>;
779 compatible = "ti,omap4-i2c";
780 reg = <0x48060000 0x100>;
781 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
782 #address-cells = <1>;
789 compatible = "ti,omap4-i2c";
790 reg = <0x4807a000 0x100>;
791 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
792 #address-cells = <1>;
799 compatible = "ti,omap4-i2c";
800 reg = <0x4807c000 0x100>;
801 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
802 #address-cells = <1>;
809 compatible = "ti,omap4-hsmmc";
810 reg = <0x4809c000 0x400>;
811 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
814 ti,needs-special-reset;
815 dmas = <&sdma 61>, <&sdma 62>;
816 dma-names = "tx", "rx";
818 pbias-supply = <&pbias_mmc_reg>;
822 compatible = "ti,omap4-hsmmc";
823 reg = <0x480b4000 0x400>;
824 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
826 ti,needs-special-reset;
827 dmas = <&sdma 47>, <&sdma 48>;
828 dma-names = "tx", "rx";
833 compatible = "ti,omap4-hsmmc";
834 reg = <0x480ad000 0x400>;
835 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
837 ti,needs-special-reset;
838 dmas = <&sdma 77>, <&sdma 78>;
839 dma-names = "tx", "rx";
844 compatible = "ti,omap4-hsmmc";
845 reg = <0x480d1000 0x400>;
846 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
848 ti,needs-special-reset;
849 dmas = <&sdma 57>, <&sdma 58>;
850 dma-names = "tx", "rx";
854 abb_mpu: regulator-abb-mpu {
855 compatible = "ti,abb-v3";
856 regulator-name = "abb_mpu";
857 #address-cells = <0>;
859 clocks = <&sys_clkin1>;
860 ti,settling-time = <50>;
861 ti,clock-cycles = <16>;
863 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
864 <0x4ae06014 0x4>, <0x4a003b20 0x8>,
866 reg-names = "setup-address", "control-address",
867 "int-address", "efuse-address",
869 ti,tranxdone-status-mask = <0x80>;
870 /* LDOVBBMPU_FBB_MUX_CTRL */
871 ti,ldovbb-override-mask = <0x400>;
872 /* LDOVBBMPU_FBB_VSET_OUT */
873 ti,ldovbb-vset-mask = <0x1F>;
876 * NOTE: only FBB mode used but actual vset will
877 * determine final biasing
880 /*uV ABB efuse rbb_m fbb_m vset_m*/
881 1060000 0 0x0 0 0x02000000 0x01F00000
882 1160000 0 0x4 0 0x02000000 0x01F00000
883 1210000 0 0x8 0 0x02000000 0x01F00000
887 abb_ivahd: regulator-abb-ivahd {
888 compatible = "ti,abb-v3";
889 regulator-name = "abb_ivahd";
890 #address-cells = <0>;
892 clocks = <&sys_clkin1>;
893 ti,settling-time = <50>;
894 ti,clock-cycles = <16>;
896 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
897 <0x4ae06010 0x4>, <0x4a0025cc 0x8>,
899 reg-names = "setup-address", "control-address",
900 "int-address", "efuse-address",
902 ti,tranxdone-status-mask = <0x40000000>;
903 /* LDOVBBIVA_FBB_MUX_CTRL */
904 ti,ldovbb-override-mask = <0x400>;
905 /* LDOVBBIVA_FBB_VSET_OUT */
906 ti,ldovbb-vset-mask = <0x1F>;
909 * NOTE: only FBB mode used but actual vset will
910 * determine final biasing
913 /*uV ABB efuse rbb_m fbb_m vset_m*/
914 1055000 0 0x0 0 0x02000000 0x01F00000
915 1150000 0 0x4 0 0x02000000 0x01F00000
916 1250000 0 0x8 0 0x02000000 0x01F00000
920 abb_dspeve: regulator-abb-dspeve {
921 compatible = "ti,abb-v3";
922 regulator-name = "abb_dspeve";
923 #address-cells = <0>;
925 clocks = <&sys_clkin1>;
926 ti,settling-time = <50>;
927 ti,clock-cycles = <16>;
929 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
930 <0x4ae06010 0x4>, <0x4a0025e0 0x8>,
932 reg-names = "setup-address", "control-address",
933 "int-address", "efuse-address",
935 ti,tranxdone-status-mask = <0x20000000>;
936 /* LDOVBBDSPEVE_FBB_MUX_CTRL */
937 ti,ldovbb-override-mask = <0x400>;
938 /* LDOVBBDSPEVE_FBB_VSET_OUT */
939 ti,ldovbb-vset-mask = <0x1F>;
942 * NOTE: only FBB mode used but actual vset will
943 * determine final biasing
946 /*uV ABB efuse rbb_m fbb_m vset_m*/
947 1055000 0 0x0 0 0x02000000 0x01F00000
948 1150000 0 0x4 0 0x02000000 0x01F00000
949 1250000 0 0x8 0 0x02000000 0x01F00000
953 abb_gpu: regulator-abb-gpu {
954 compatible = "ti,abb-v3";
955 regulator-name = "abb_gpu";
956 #address-cells = <0>;
958 clocks = <&sys_clkin1>;
959 ti,settling-time = <50>;
960 ti,clock-cycles = <16>;
962 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
963 <0x4ae06010 0x4>, <0x4a003b08 0x8>,
965 reg-names = "setup-address", "control-address",
966 "int-address", "efuse-address",
968 ti,tranxdone-status-mask = <0x10000000>;
969 /* LDOVBBGPU_FBB_MUX_CTRL */
970 ti,ldovbb-override-mask = <0x400>;
971 /* LDOVBBGPU_FBB_VSET_OUT */
972 ti,ldovbb-vset-mask = <0x1F>;
975 * NOTE: only FBB mode used but actual vset will
976 * determine final biasing
979 /*uV ABB efuse rbb_m fbb_m vset_m*/
980 1090000 0 0x0 0 0x02000000 0x01F00000
981 1210000 0 0x4 0 0x02000000 0x01F00000
982 1280000 0 0x8 0 0x02000000 0x01F00000
986 mcspi1: spi@48098000 {
987 compatible = "ti,omap4-mcspi";
988 reg = <0x48098000 0x200>;
989 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
990 #address-cells = <1>;
992 ti,hwmods = "mcspi1";
1002 dma-names = "tx0", "rx0", "tx1", "rx1",
1003 "tx2", "rx2", "tx3", "rx3";
1004 status = "disabled";
1007 mcspi2: spi@4809a000 {
1008 compatible = "ti,omap4-mcspi";
1009 reg = <0x4809a000 0x200>;
1010 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1011 #address-cells = <1>;
1013 ti,hwmods = "mcspi2";
1014 ti,spi-num-cs = <2>;
1019 dma-names = "tx0", "rx0", "tx1", "rx1";
1020 status = "disabled";
1023 mcspi3: spi@480b8000 {
1024 compatible = "ti,omap4-mcspi";
1025 reg = <0x480b8000 0x200>;
1026 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1027 #address-cells = <1>;
1029 ti,hwmods = "mcspi3";
1030 ti,spi-num-cs = <2>;
1031 dmas = <&sdma 15>, <&sdma 16>;
1032 dma-names = "tx0", "rx0";
1033 status = "disabled";
1036 mcspi4: spi@480ba000 {
1037 compatible = "ti,omap4-mcspi";
1038 reg = <0x480ba000 0x200>;
1039 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1040 #address-cells = <1>;
1042 ti,hwmods = "mcspi4";
1043 ti,spi-num-cs = <1>;
1044 dmas = <&sdma 70>, <&sdma 71>;
1045 dma-names = "tx0", "rx0";
1046 status = "disabled";
1049 qspi: qspi@4b300000 {
1050 compatible = "ti,dra7xxx-qspi";
1051 reg = <0x4b300000 0x100>;
1052 reg-names = "qspi_base";
1053 #address-cells = <1>;
1056 clocks = <&qspi_gfclk_div>;
1057 clock-names = "fck";
1059 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
1060 status = "disabled";
1063 omap_control_sata: control-phy@4a002374 {
1064 compatible = "ti,control-phy-pipe3";
1065 reg = <0x4a002374 0x4>;
1066 reg-names = "power";
1067 clocks = <&sys_clkin1>;
1068 clock-names = "sysclk";
1073 compatible = "ti,omap-ocp2scp";
1074 #address-cells = <1>;
1077 reg = <0x4a090000 0x20>;
1078 ti,hwmods = "ocp2scp3";
1079 sata_phy: phy@4A096000 {
1080 compatible = "ti,phy-pipe3-sata";
1081 reg = <0x4A096000 0x80>, /* phy_rx */
1082 <0x4A096400 0x64>, /* phy_tx */
1083 <0x4A096800 0x40>; /* pll_ctrl */
1084 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1085 ctrl-module = <&omap_control_sata>;
1086 clocks = <&sys_clkin1>, <&sata_ref_clk>;
1087 clock-names = "sysclk", "refclk";
1091 pcie1_phy: pciephy@4a094000 {
1092 compatible = "ti,phy-pipe3-pcie";
1093 reg = <0x4a094000 0x80>, /* phy_rx */
1094 <0x4a094400 0x64>; /* phy_tx */
1095 reg-names = "phy_rx", "phy_tx";
1096 ctrl-module = <&omap_control_pcie1phy>;
1097 clocks = <&dpll_pcie_ref_ck>,
1098 <&dpll_pcie_ref_m2ldo_ck>,
1099 <&optfclk_pciephy1_32khz>,
1100 <&optfclk_pciephy1_clk>,
1101 <&optfclk_pciephy1_div_clk>,
1102 <&optfclk_pciephy_div>;
1103 clock-names = "dpll_ref", "dpll_ref_m2",
1104 "wkupclk", "refclk",
1105 "div-clk", "phy-div";
1109 pcie2_phy: pciephy@4a095000 {
1110 compatible = "ti,phy-pipe3-pcie";
1111 reg = <0x4a095000 0x80>, /* phy_rx */
1112 <0x4a095400 0x64>; /* phy_tx */
1113 reg-names = "phy_rx", "phy_tx";
1114 ctrl-module = <&omap_control_pcie2phy>;
1115 clocks = <&dpll_pcie_ref_ck>,
1116 <&dpll_pcie_ref_m2ldo_ck>,
1117 <&optfclk_pciephy2_32khz>,
1118 <&optfclk_pciephy2_clk>,
1119 <&optfclk_pciephy2_div_clk>,
1120 <&optfclk_pciephy_div>;
1121 clock-names = "dpll_ref", "dpll_ref_m2",
1122 "wkupclk", "refclk",
1123 "div-clk", "phy-div";
1125 status = "disabled";
1129 sata: sata@4a141100 {
1130 compatible = "snps,dwc-ahci";
1131 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
1132 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1134 phy-names = "sata-phy";
1135 clocks = <&sata_ref_clk>;
1139 omap_control_pcie1phy: control-phy@0x4a003c40 {
1140 compatible = "ti,control-phy-pcie";
1141 reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
1142 reg-names = "power", "control_sma", "pcie_pcs";
1143 clocks = <&sys_clkin1>;
1144 clock-names = "sysclk";
1147 omap_control_pcie2phy: control-pcie@0x4a003c44 {
1148 compatible = "ti,control-phy-pcie";
1149 reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
1150 reg-names = "power", "control_sma", "pcie_pcs";
1151 clocks = <&sys_clkin1>;
1152 clock-names = "sysclk";
1153 status = "disabled";
1157 compatible = "ti,am3352-rtc";
1158 reg = <0x48838000 0x100>;
1159 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1160 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1161 ti,hwmods = "rtcss";
1162 clocks = <&sys_32k_ck>;
1165 omap_control_usb2phy1: control-phy@4a002300 {
1166 compatible = "ti,control-phy-usb2";
1167 reg = <0x4a002300 0x4>;
1168 reg-names = "power";
1171 omap_control_usb3phy1: control-phy@4a002370 {
1172 compatible = "ti,control-phy-pipe3";
1173 reg = <0x4a002370 0x4>;
1174 reg-names = "power";
1177 omap_control_usb2phy2: control-phy@0x4a002e74 {
1178 compatible = "ti,control-phy-usb2-dra7";
1179 reg = <0x4a002e74 0x4>;
1180 reg-names = "power";
1185 compatible = "ti,omap-ocp2scp";
1186 #address-cells = <1>;
1189 reg = <0x4a080000 0x20>;
1190 ti,hwmods = "ocp2scp1";
1192 usb2_phy1: phy@4a084000 {
1193 compatible = "ti,omap-usb2";
1194 reg = <0x4a084000 0x400>;
1195 ctrl-module = <&omap_control_usb2phy1>;
1196 clocks = <&usb_phy1_always_on_clk32k>,
1197 <&usb_otg_ss1_refclk960m>;
1198 clock-names = "wkupclk",
1203 usb2_phy2: phy@4a085000 {
1204 compatible = "ti,omap-usb2";
1205 reg = <0x4a085000 0x400>;
1206 ctrl-module = <&omap_control_usb2phy2>;
1207 clocks = <&usb_phy2_always_on_clk32k>,
1208 <&usb_otg_ss2_refclk960m>;
1209 clock-names = "wkupclk",
1214 usb3_phy1: phy@4a084400 {
1215 compatible = "ti,omap-usb3";
1216 reg = <0x4a084400 0x80>,
1219 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1220 ctrl-module = <&omap_control_usb3phy1>;
1221 clocks = <&usb_phy3_always_on_clk32k>,
1223 <&usb_otg_ss1_refclk960m>;
1224 clock-names = "wkupclk",
1231 omap_dwc3_1: omap_dwc3_1@48880000 {
1232 compatible = "ti,dwc3";
1233 ti,hwmods = "usb_otg_ss1";
1234 reg = <0x48880000 0x10000>;
1235 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1236 #address-cells = <1>;
1240 usb1: usb@48890000 {
1241 compatible = "snps,dwc3";
1242 reg = <0x48890000 0x17000>;
1243 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1244 phys = <&usb2_phy1>, <&usb3_phy1>;
1245 phy-names = "usb2-phy", "usb3-phy";
1247 maximum-speed = "super-speed";
1249 snps,dis_u3_susphy_quirk;
1250 snps,dis_u2_susphy_quirk;
1254 omap_dwc3_2: omap_dwc3_2@488c0000 {
1255 compatible = "ti,dwc3";
1256 ti,hwmods = "usb_otg_ss2";
1257 reg = <0x488c0000 0x10000>;
1258 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1259 #address-cells = <1>;
1263 usb2: usb@488d0000 {
1264 compatible = "snps,dwc3";
1265 reg = <0x488d0000 0x17000>;
1266 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1267 phys = <&usb2_phy2>;
1268 phy-names = "usb2-phy";
1270 maximum-speed = "high-speed";
1272 snps,dis_u3_susphy_quirk;
1273 snps,dis_u2_susphy_quirk;
1277 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
1278 omap_dwc3_3: omap_dwc3_3@48900000 {
1279 compatible = "ti,dwc3";
1280 ti,hwmods = "usb_otg_ss3";
1281 reg = <0x48900000 0x10000>;
1282 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1283 #address-cells = <1>;
1287 status = "disabled";
1288 usb3: usb@48910000 {
1289 compatible = "snps,dwc3";
1290 reg = <0x48910000 0x17000>;
1291 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1293 maximum-speed = "high-speed";
1295 snps,dis_u3_susphy_quirk;
1296 snps,dis_u2_susphy_quirk;
1301 compatible = "ti,am3352-elm";
1302 reg = <0x48078000 0xfc0>; /* device IO registers */
1303 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1305 status = "disabled";
1308 gpmc: gpmc@50000000 {
1309 compatible = "ti,am3352-gpmc";
1311 reg = <0x50000000 0x37c>; /* device IO registers */
1312 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1314 gpmc,num-waitpins = <2>;
1315 #address-cells = <2>;
1317 status = "disabled";
1321 compatible = "ti,dra7-atl";
1322 reg = <0x4843c000 0x3ff>;
1324 ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
1325 <&atl_clkin2_ck>, <&atl_clkin3_ck>;
1326 clocks = <&atl_gfclk_mux>;
1327 clock-names = "fck";
1328 status = "disabled";
1331 crossbar_mpu: crossbar@4a020000 {
1332 compatible = "ti,irq-crossbar";
1333 reg = <0x4a002a48 0x130>;
1334 ti,max-irqs = <160>;
1335 ti,max-crossbar-sources = <MAX_SOURCES>;
1337 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
1338 ti,irqs-skip = <10 133 139 140>;
1339 ti,irqs-safe-map = <0>;
1342 mac: ethernet@4a100000 {
1343 compatible = "ti,cpsw";
1345 clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>;
1346 clock-names = "fck", "cpts";
1347 cpdma_channels = <8>;
1348 ale_entries = <1024>;
1349 bd_ram_size = <0x2000>;
1352 mac_control = <0x20>;
1355 cpts_clock_mult = <0x80000000>;
1356 cpts_clock_shift = <29>;
1357 reg = <0x48484000 0x1000
1359 #address-cells = <1>;
1367 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1368 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1369 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1370 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
1372 status = "disabled";
1374 davinci_mdio: mdio@48485000 {
1375 compatible = "ti,davinci_mdio";
1376 #address-cells = <1>;
1378 ti,hwmods = "davinci_mdio";
1379 bus_freq = <1000000>;
1380 reg = <0x48485000 0x100>;
1383 cpsw_emac0: slave@48480200 {
1384 /* Filled in by U-Boot */
1385 mac-address = [ 00 00 00 00 00 00 ];
1388 cpsw_emac1: slave@48480300 {
1389 /* Filled in by U-Boot */
1390 mac-address = [ 00 00 00 00 00 00 ];
1393 phy_sel: cpsw-phy-sel@4a002554 {
1394 compatible = "ti,dra7xx-cpsw-phy-sel";
1395 reg= <0x4a002554 0x4>;
1396 reg-names = "gmii-sel";
1400 dcan1: can@481cc000 {
1401 compatible = "ti,dra7-d_can";
1402 ti,hwmods = "dcan1";
1403 reg = <0x4ae3c000 0x2000>;
1404 syscon-raminit = <&dra7_ctrl_core 0x558 0>;
1405 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1406 clocks = <&dcan1_sys_clk_mux>;
1407 status = "disabled";
1410 dcan2: can@481d0000 {
1411 compatible = "ti,dra7-d_can";
1412 ti,hwmods = "dcan2";
1413 reg = <0x48480000 0x2000>;
1414 syscon-raminit = <&dra7_ctrl_core 0x558 1>;
1415 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1416 clocks = <&sys_clkin1>;
1417 status = "disabled";
1422 /include/ "dra7xx-clocks.dtsi"