arch/arm/boot/dts/dra7.dtsi

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/pinctrl/dra.h>
  12
  13 #include "skeleton.dtsi"
  14
  15 / {
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18
  19         compatible = "ti,dra7xx";
  20         interrupt-parent = <&gic>;
  21
  22         aliases {
  23                 serial0 = &uart1;
  24                 serial1 = &uart2;
  25                 serial2 = &uart3;
  26                 serial3 = &uart4;
  27                 serial4 = &uart5;
  28                 serial5 = &uart6;
  29         };
  30
  31         cpus {
  32                 #address-cells = <1>;
  33                 #size-cells = <0>;
  34
  35                 cpu@0 {
  36                         device_type = "cpu";
  37                         compatible = "arm,cortex-a15";
  38                         reg = <0>;
  39                 };
  40                 cpu@1 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a15";
  43                         reg = <1>;
  44                 };
  45         };
  46
  47         timer {
  48                 compatible = "arm,armv7-timer";
  49                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  50                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  51                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  52                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  53         };
  54
  55         gic: interrupt-controller@48211000 {
  56                 compatible = "arm,cortex-a15-gic";
  57                 interrupt-controller;
  58                 #interrupt-cells = <3>;
  59                 reg = <0x48211000 0x1000>,
  60                       <0x48212000 0x1000>,
  61                       <0x48214000 0x2000>,
  62                       <0x48216000 0x2000>;
  63                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  64         };
  65
  66         /*
  67          * The soc node represents the soc top level view. It is uses for IPs
  68          * that are not memory mapped in the MPU view or for the MPU itself.
  69          */
  70         soc {
  71                 compatible = "ti,omap-infra";
  72                 mpu {
  73                         compatible = "ti,omap5-mpu";
  74                         ti,hwmods = "mpu";
  75                 };
  76         };
  77
  78         /*
  79          * XXX: Use a flat representation of the SOC interconnect.
  80          * The real OMAP interconnect network is quite complex.
  81          * Since that will not bring real advantage to represent that in DT for
  82          * the moment, just use a fake OCP bus entry to represent the whole bus
  83          * hierarchy.
  84          */
  85         ocp {
  86                 compatible = "ti,omap4-l3-noc", "simple-bus";
  87                 #address-cells = <1>;
  88                 #size-cells = <1>;
  89                 ranges;
  90                 ti,hwmods = "l3_main_1", "l3_main_2";
  91                 reg = <0x44000000 0x2000>,
  92                       <0x44800000 0x3000>;
  93                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
  94                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
  95
  96                 counter32k: counter@4ae04000 {
  97                         compatible = "ti,omap-counter32k";
  98                         reg = <0x4ae04000 0x40>;
  99                         ti,hwmods = "counter_32k";
 100                 };
 101
 102                 dra7_pmx_core: pinmux@4a003400 {
 103                         compatible = "pinctrl-single";
 104                         reg = <0x4a003400 0x0464>;
 105                         #address-cells = <1>;
 106                         #size-cells = <0>;
 107                         pinctrl-single,register-width = <32>;
 108                         pinctrl-single,function-mask = <0x3fffffff>;
 109                 };
 110
 111                 sdma: dma-controller@4a056000 {
 112                         compatible = "ti,omap4430-sdma";
 113                         reg = <0x4a056000 0x1000>;
 114                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 115                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 116                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 117                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 118                         #dma-cells = <1>;
 119                         #dma-channels = <32>;
 120                         #dma-requests = <127>;
 121                 };
 122
 123                 gpio1: gpio@4ae10000 {
 124                         compatible = "ti,omap4-gpio";
 125                         reg = <0x4ae10000 0x200>;
 126                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 127                         ti,hwmods = "gpio1";
 128                         gpio-controller;
 129                         #gpio-cells = <2>;
 130                         interrupt-controller;
 131                         #interrupt-cells = <1>;
 132                 };
 133
 134                 gpio2: gpio@48055000 {
 135                         compatible = "ti,omap4-gpio";
 136                         reg = <0x48055000 0x200>;
 137                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 138                         ti,hwmods = "gpio2";
 139                         gpio-controller;
 140                         #gpio-cells = <2>;
 141                         interrupt-controller;
 142                         #interrupt-cells = <1>;
 143                 };
 144
 145                 gpio3: gpio@48057000 {
 146                         compatible = "ti,omap4-gpio";
 147                         reg = <0x48057000 0x200>;
 148                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 149                         ti,hwmods = "gpio3";
 150                         gpio-controller;
 151                         #gpio-cells = <2>;
 152                         interrupt-controller;
 153                         #interrupt-cells = <1>;
 154                 };
 155
 156                 gpio4: gpio@48059000 {
 157                         compatible = "ti,omap4-gpio";
 158                         reg = <0x48059000 0x200>;
 159                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 160                         ti,hwmods = "gpio4";
 161                         gpio-controller;
 162                         #gpio-cells = <2>;
 163                         interrupt-controller;
 164                         #interrupt-cells = <1>;
 165                 };
 166
 167                 gpio5: gpio@4805b000 {
 168                         compatible = "ti,omap4-gpio";
 169                         reg = <0x4805b000 0x200>;
 170                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 171                         ti,hwmods = "gpio5";
 172                         gpio-controller;
 173                         #gpio-cells = <2>;
 174                         interrupt-controller;
 175                         #interrupt-cells = <1>;
 176                 };
 177
 178                 gpio6: gpio@4805d000 {
 179                         compatible = "ti,omap4-gpio";
 180                         reg = <0x4805d000 0x200>;
 181                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 182                         ti,hwmods = "gpio6";
 183                         gpio-controller;
 184                         #gpio-cells = <2>;
 185                         interrupt-controller;
 186                         #interrupt-cells = <1>;
 187                 };
 188
 189                 gpio7: gpio@48051000 {
 190                         compatible = "ti,omap4-gpio";
 191                         reg = <0x48051000 0x200>;
 192                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 193                         ti,hwmods = "gpio7";
 194                         gpio-controller;
 195                         #gpio-cells = <2>;
 196                         interrupt-controller;
 197                         #interrupt-cells = <1>;
 198                 };
 199
 200                 gpio8: gpio@48053000 {
 201                         compatible = "ti,omap4-gpio";
 202                         reg = <0x48053000 0x200>;
 203                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 204                         ti,hwmods = "gpio8";
 205                         gpio-controller;
 206                         #gpio-cells = <2>;
 207                         interrupt-controller;
 208                         #interrupt-cells = <1>;
 209                 };
 210
 211                 uart1: serial@4806a000 {
 212                         compatible = "ti,omap4-uart";
 213                         reg = <0x4806a000 0x100>;
 214                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 215                         ti,hwmods = "uart1";
 216                         clock-frequency = <48000000>;
 217                         status = "disabled";
 218                 };
 219
 220                 uart2: serial@4806c000 {
 221                         compatible = "ti,omap4-uart";
 222                         reg = <0x4806c000 0x100>;
 223                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 224                         ti,hwmods = "uart2";
 225                         clock-frequency = <48000000>;
 226                         status = "disabled";
 227                 };
 228
 229                 uart3: serial@48020000 {
 230                         compatible = "ti,omap4-uart";
 231                         reg = <0x48020000 0x100>;
 232                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 233                         ti,hwmods = "uart3";
 234                         clock-frequency = <48000000>;
 235                         status = "disabled";
 236                 };
 237
 238                 uart4: serial@4806e000 {
 239                         compatible = "ti,omap4-uart";
 240                         reg = <0x4806e000 0x100>;
 241                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 242                         ti,hwmods = "uart4";
 243                         clock-frequency = <48000000>;
 244                         status = "disabled";
 245                 };
 246
 247                 uart5: serial@48066000 {
 248                         compatible = "ti,omap4-uart";
 249                         reg = <0x48066000 0x100>;
 250                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 251                         ti,hwmods = "uart5";
 252                         clock-frequency = <48000000>;
 253                         status = "disabled";
 254                 };
 255
 256                 uart6: serial@48068000 {
 257                         compatible = "ti,omap4-uart";
 258                         reg = <0x48068000 0x100>;
 259                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 260                         ti,hwmods = "uart6";
 261                         clock-frequency = <48000000>;
 262                         status = "disabled";
 263                 };
 264
 265                 uart7: serial@48420000 {
 266                         compatible = "ti,omap4-uart";
 267                         reg = <0x48420000 0x100>;
 268                         ti,hwmods = "uart7";
 269                         clock-frequency = <48000000>;
 270                         status = "disabled";
 271                 };
 272
 273                 uart8: serial@48422000 {
 274                         compatible = "ti,omap4-uart";
 275                         reg = <0x48422000 0x100>;
 276                         ti,hwmods = "uart8";
 277                         clock-frequency = <48000000>;
 278                         status = "disabled";
 279                 };
 280
 281                 uart9: serial@48424000 {
 282                         compatible = "ti,omap4-uart";
 283                         reg = <0x48424000 0x100>;
 284                         ti,hwmods = "uart9";
 285                         clock-frequency = <48000000>;
 286                         status = "disabled";
 287                 };
 288
 289                 uart10: serial@4ae2b000 {
 290                         compatible = "ti,omap4-uart";
 291                         reg = <0x4ae2b000 0x100>;
 292                         ti,hwmods = "uart10";
 293                         clock-frequency = <48000000>;
 294                         status = "disabled";
 295                 };
 296
 297                 timer1: timer@4ae18000 {
 298                         compatible = "ti,omap5430-timer";
 299                         reg = <0x4ae18000 0x80>;
 300                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 301                         ti,hwmods = "timer1";
 302                         ti,timer-alwon;
 303                 };
 304
 305                 timer2: timer@48032000 {
 306                         compatible = "ti,omap5430-timer";
 307                         reg = <0x48032000 0x80>;
 308                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 309                         ti,hwmods = "timer2";
 310                 };
 311
 312                 timer3: timer@48034000 {
 313                         compatible = "ti,omap5430-timer";
 314                         reg = <0x48034000 0x80>;
 315                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 316                         ti,hwmods = "timer3";
 317                 };
 318
 319                 timer4: timer@48036000 {
 320                         compatible = "ti,omap5430-timer";
 321                         reg = <0x48036000 0x80>;
 322                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 323                         ti,hwmods = "timer4";
 324                 };
 325
 326                 timer5: timer@48820000 {
 327                         compatible = "ti,omap5430-timer";
 328                         reg = <0x48820000 0x80>;
 329                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 330                         ti,hwmods = "timer5";
 331                         ti,timer-dsp;
 332                 };
 333
 334                 timer6: timer@48822000 {
 335                         compatible = "ti,omap5430-timer";
 336                         reg = <0x48822000 0x80>;
 337                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 338                         ti,hwmods = "timer6";
 339                         ti,timer-dsp;
 340                         ti,timer-pwm;
 341                 };
 342
 343                 timer7: timer@48824000 {
 344                         compatible = "ti,omap5430-timer";
 345                         reg = <0x48824000 0x80>;
 346                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 347                         ti,hwmods = "timer7";
 348                         ti,timer-dsp;
 349                 };
 350
 351                 timer8: timer@48826000 {
 352                         compatible = "ti,omap5430-timer";
 353                         reg = <0x48826000 0x80>;
 354                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 355                         ti,hwmods = "timer8";
 356                         ti,timer-dsp;
 357                         ti,timer-pwm;
 358                 };
 359
 360                 timer9: timer@4803e000 {
 361                         compatible = "ti,omap5430-timer";
 362                         reg = <0x4803e000 0x80>;
 363                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 364                         ti,hwmods = "timer9";
 365                 };
 366
 367                 timer10: timer@48086000 {
 368                         compatible = "ti,omap5430-timer";
 369                         reg = <0x48086000 0x80>;
 370                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 371                         ti,hwmods = "timer10";
 372                 };
 373
 374                 timer11: timer@48088000 {
 375                         compatible = "ti,omap5430-timer";
 376                         reg = <0x48088000 0x80>;
 377                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 378                         ti,hwmods = "timer11";
 379                         ti,timer-pwm;
 380                 };
 381
 382                 timer13: timer@48828000 {
 383                         compatible = "ti,omap5430-timer";
 384                         reg = <0x48828000 0x80>;
 385                         ti,hwmods = "timer13";
 386                         status = "disabled";
 387                 };
 388
 389                 timer14: timer@4882a000 {
 390                         compatible = "ti,omap5430-timer";
 391                         reg = <0x4882a000 0x80>;
 392                         ti,hwmods = "timer14";
 393                         status = "disabled";
 394                 };
 395
 396                 timer15: timer@4882c000 {
 397                         compatible = "ti,omap5430-timer";
 398                         reg = <0x4882c000 0x80>;
 399                         ti,hwmods = "timer15";
 400                         status = "disabled";
 401                 };
 402
 403                 timer16: timer@4882e000 {
 404                         compatible = "ti,omap5430-timer";
 405                         reg = <0x4882e000 0x80>;
 406                         ti,hwmods = "timer16";
 407                         status = "disabled";
 408                 };
 409
 410                 wdt2: wdt@4ae14000 {
 411                         compatible = "ti,omap4-wdt";
 412                         reg = <0x4ae14000 0x80>;
 413                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 414                         ti,hwmods = "wd_timer2";
 415                 };
 416
 417                 i2c1: i2c@48070000 {
 418                         compatible = "ti,omap4-i2c";
 419                         reg = <0x48070000 0x100>;
 420                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 421                         #address-cells = <1>;
 422                         #size-cells = <0>;
 423                         ti,hwmods = "i2c1";
 424                         status = "disabled";
 425                 };
 426
 427                 i2c2: i2c@48072000 {
 428                         compatible = "ti,omap4-i2c";
 429                         reg = <0x48072000 0x100>;
 430                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 431                         #address-cells = <1>;
 432                         #size-cells = <0>;
 433                         ti,hwmods = "i2c2";
 434                         status = "disabled";
 435                 };
 436
 437                 i2c3: i2c@48060000 {
 438                         compatible = "ti,omap4-i2c";
 439                         reg = <0x48060000 0x100>;
 440                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 441                         #address-cells = <1>;
 442                         #size-cells = <0>;
 443                         ti,hwmods = "i2c3";
 444                         status = "disabled";
 445                 };
 446
 447                 i2c4: i2c@4807a000 {
 448                         compatible = "ti,omap4-i2c";
 449                         reg = <0x4807a000 0x100>;
 450                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 451                         #address-cells = <1>;
 452                         #size-cells = <0>;
 453                         ti,hwmods = "i2c4";
 454                         status = "disabled";
 455                 };
 456
 457                 i2c5: i2c@4807c000 {
 458                         compatible = "ti,omap4-i2c";
 459                         reg = <0x4807c000 0x100>;
 460                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 461                         #address-cells = <1>;
 462                         #size-cells = <0>;
 463                         ti,hwmods = "i2c5";
 464                         status = "disabled";
 465                 };
 466
 467                 mmc1: mmc@4809c000 {
 468                         compatible = "ti,omap4-hsmmc";
 469                         reg = <0x4809c000 0x400>;
 470                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 471                         ti,hwmods = "mmc1";
 472                         ti,dual-volt;
 473                         ti,needs-special-reset;
 474                         dmas = <&sdma 61>, <&sdma 62>;
 475                         dma-names = "tx", "rx";
 476                         status = "disabled";
 477                 };
 478
 479                 mmc2: mmc@480b4000 {
 480                         compatible = "ti,omap4-hsmmc";
 481                         reg = <0x480b4000 0x400>;
 482                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 483                         ti,hwmods = "mmc2";
 484                         ti,needs-special-reset;
 485                         dmas = <&sdma 47>, <&sdma 48>;
 486                         dma-names = "tx", "rx";
 487                         status = "disabled";
 488                 };
 489
 490                 mmc3: mmc@480ad000 {
 491                         compatible = "ti,omap4-hsmmc";
 492                         reg = <0x480ad000 0x400>;
 493                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 494                         ti,hwmods = "mmc3";
 495                         ti,needs-special-reset;
 496                         dmas = <&sdma 77>, <&sdma 78>;
 497                         dma-names = "tx", "rx";
 498                         status = "disabled";
 499                 };
 500
 501                 mmc4: mmc@480d1000 {
 502                         compatible = "ti,omap4-hsmmc";
 503                         reg = <0x480d1000 0x400>;
 504                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 505                         ti,hwmods = "mmc4";
 506                         ti,needs-special-reset;
 507                         dmas = <&sdma 57>, <&sdma 58>;
 508                         dma-names = "tx", "rx";
 509                         status = "disabled";
 510                 };
 511
 512                 mcspi1: spi@48098000 {
 513                         compatible = "ti,omap4-mcspi";
 514                         reg = <0x48098000 0x200>;
 515                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 516                         #address-cells = <1>;
 517                         #size-cells = <0>;
 518                         ti,hwmods = "mcspi1";
 519                         ti,spi-num-cs = <4>;
 520                         dmas = <&sdma 35>,
 521                                <&sdma 36>,
 522                                <&sdma 37>,
 523                                <&sdma 38>,
 524                                <&sdma 39>,
 525                                <&sdma 40>,
 526                                <&sdma 41>,
 527                                <&sdma 42>;
 528                         dma-names = "tx0", "rx0", "tx1", "rx1",
 529                                     "tx2", "rx2", "tx3", "rx3";
 530                         status = "disabled";
 531                 };
 532
 533                 mcspi2: spi@4809a000 {
 534                         compatible = "ti,omap4-mcspi";
 535                         reg = <0x4809a000 0x200>;
 536                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 537                         #address-cells = <1>;
 538                         #size-cells = <0>;
 539                         ti,hwmods = "mcspi2";
 540                         ti,spi-num-cs = <2>;
 541                         dmas = <&sdma 43>,
 542                                <&sdma 44>,
 543                                <&sdma 45>,
 544                                <&sdma 46>;
 545                         dma-names = "tx0", "rx0", "tx1", "rx1";
 546                         status = "disabled";
 547                 };
 548
 549                 mcspi3: spi@480b8000 {
 550                         compatible = "ti,omap4-mcspi";
 551                         reg = <0x480b8000 0x200>;
 552                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 553                         #address-cells = <1>;
 554                         #size-cells = <0>;
 555                         ti,hwmods = "mcspi3";
 556                         ti,spi-num-cs = <2>;
 557                         dmas = <&sdma 15>, <&sdma 16>;
 558                         dma-names = "tx0", "rx0";
 559                         status = "disabled";
 560                 };
 561
 562                 mcspi4: spi@480ba000 {
 563                         compatible = "ti,omap4-mcspi";
 564                         reg = <0x480ba000 0x200>;
 565                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 566                         #address-cells = <1>;
 567                         #size-cells = <0>;
 568                         ti,hwmods = "mcspi4";
 569                         ti,spi-num-cs = <1>;
 570                         dmas = <&sdma 70>, <&sdma 71>;
 571                         dma-names = "tx0", "rx0";
 572                         status = "disabled";
 573                 };
 574         };
 575 };