2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h>
13 #include "skeleton.dtsi"
19 compatible = "ti,dra7xx";
20 interrupt-parent = <&gic>;
37 compatible = "arm,cortex-a15";
42 compatible = "arm,cortex-a15";
48 compatible = "arm,armv7-timer";
49 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
50 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
51 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
52 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
55 gic: interrupt-controller@48211000 {
56 compatible = "arm,cortex-a15-gic";
58 #interrupt-cells = <3>;
59 reg = <0x48211000 0x1000>,
63 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
67 * The soc node represents the soc top level view. It is uses for IPs
68 * that are not memory mapped in the MPU view or for the MPU itself.
71 compatible = "ti,omap-infra";
73 compatible = "ti,omap5-mpu";
79 * XXX: Use a flat representation of the SOC interconnect.
80 * The real OMAP interconnect network is quite complex.
81 * Since that will not bring real advantage to represent that in DT for
82 * the moment, just use a fake OCP bus entry to represent the whole bus
86 compatible = "ti,omap4-l3-noc", "simple-bus";
90 ti,hwmods = "l3_main_1", "l3_main_2";
91 reg = <0x44000000 0x2000>,
93 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
94 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
96 counter32k: counter@4ae04000 {
97 compatible = "ti,omap-counter32k";
98 reg = <0x4ae04000 0x40>;
99 ti,hwmods = "counter_32k";
102 dra7_pmx_core: pinmux@4a003400 {
103 compatible = "pinctrl-single";
104 reg = <0x4a003400 0x0464>;
105 #address-cells = <1>;
107 pinctrl-single,register-width = <32>;
108 pinctrl-single,function-mask = <0x3fffffff>;
111 sdma: dma-controller@4a056000 {
112 compatible = "ti,omap4430-sdma";
113 reg = <0x4a056000 0x1000>;
114 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
115 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
116 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
117 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
119 #dma-channels = <32>;
120 #dma-requests = <127>;
123 gpio1: gpio@4ae10000 {
124 compatible = "ti,omap4-gpio";
125 reg = <0x4ae10000 0x200>;
126 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
130 interrupt-controller;
131 #interrupt-cells = <1>;
134 gpio2: gpio@48055000 {
135 compatible = "ti,omap4-gpio";
136 reg = <0x48055000 0x200>;
137 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
141 interrupt-controller;
142 #interrupt-cells = <1>;
145 gpio3: gpio@48057000 {
146 compatible = "ti,omap4-gpio";
147 reg = <0x48057000 0x200>;
148 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
152 interrupt-controller;
153 #interrupt-cells = <1>;
156 gpio4: gpio@48059000 {
157 compatible = "ti,omap4-gpio";
158 reg = <0x48059000 0x200>;
159 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
163 interrupt-controller;
164 #interrupt-cells = <1>;
167 gpio5: gpio@4805b000 {
168 compatible = "ti,omap4-gpio";
169 reg = <0x4805b000 0x200>;
170 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
174 interrupt-controller;
175 #interrupt-cells = <1>;
178 gpio6: gpio@4805d000 {
179 compatible = "ti,omap4-gpio";
180 reg = <0x4805d000 0x200>;
181 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
185 interrupt-controller;
186 #interrupt-cells = <1>;
189 gpio7: gpio@48051000 {
190 compatible = "ti,omap4-gpio";
191 reg = <0x48051000 0x200>;
192 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
196 interrupt-controller;
197 #interrupt-cells = <1>;
200 gpio8: gpio@48053000 {
201 compatible = "ti,omap4-gpio";
202 reg = <0x48053000 0x200>;
203 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
207 interrupt-controller;
208 #interrupt-cells = <1>;
211 uart1: serial@4806a000 {
212 compatible = "ti,omap4-uart";
213 reg = <0x4806a000 0x100>;
214 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
216 clock-frequency = <48000000>;
220 uart2: serial@4806c000 {
221 compatible = "ti,omap4-uart";
222 reg = <0x4806c000 0x100>;
223 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
225 clock-frequency = <48000000>;
229 uart3: serial@48020000 {
230 compatible = "ti,omap4-uart";
231 reg = <0x48020000 0x100>;
232 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
234 clock-frequency = <48000000>;
238 uart4: serial@4806e000 {
239 compatible = "ti,omap4-uart";
240 reg = <0x4806e000 0x100>;
241 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
243 clock-frequency = <48000000>;
247 uart5: serial@48066000 {
248 compatible = "ti,omap4-uart";
249 reg = <0x48066000 0x100>;
250 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
252 clock-frequency = <48000000>;
256 uart6: serial@48068000 {
257 compatible = "ti,omap4-uart";
258 reg = <0x48068000 0x100>;
259 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
261 clock-frequency = <48000000>;
265 uart7: serial@48420000 {
266 compatible = "ti,omap4-uart";
267 reg = <0x48420000 0x100>;
269 clock-frequency = <48000000>;
273 uart8: serial@48422000 {
274 compatible = "ti,omap4-uart";
275 reg = <0x48422000 0x100>;
277 clock-frequency = <48000000>;
281 uart9: serial@48424000 {
282 compatible = "ti,omap4-uart";
283 reg = <0x48424000 0x100>;
285 clock-frequency = <48000000>;
289 uart10: serial@4ae2b000 {
290 compatible = "ti,omap4-uart";
291 reg = <0x4ae2b000 0x100>;
292 ti,hwmods = "uart10";
293 clock-frequency = <48000000>;
297 timer1: timer@4ae18000 {
298 compatible = "ti,omap5430-timer";
299 reg = <0x4ae18000 0x80>;
300 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
301 ti,hwmods = "timer1";
305 timer2: timer@48032000 {
306 compatible = "ti,omap5430-timer";
307 reg = <0x48032000 0x80>;
308 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
309 ti,hwmods = "timer2";
312 timer3: timer@48034000 {
313 compatible = "ti,omap5430-timer";
314 reg = <0x48034000 0x80>;
315 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
316 ti,hwmods = "timer3";
319 timer4: timer@48036000 {
320 compatible = "ti,omap5430-timer";
321 reg = <0x48036000 0x80>;
322 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
323 ti,hwmods = "timer4";
326 timer5: timer@48820000 {
327 compatible = "ti,omap5430-timer";
328 reg = <0x48820000 0x80>;
329 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
330 ti,hwmods = "timer5";
334 timer6: timer@48822000 {
335 compatible = "ti,omap5430-timer";
336 reg = <0x48822000 0x80>;
337 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
338 ti,hwmods = "timer6";
343 timer7: timer@48824000 {
344 compatible = "ti,omap5430-timer";
345 reg = <0x48824000 0x80>;
346 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
347 ti,hwmods = "timer7";
351 timer8: timer@48826000 {
352 compatible = "ti,omap5430-timer";
353 reg = <0x48826000 0x80>;
354 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
355 ti,hwmods = "timer8";
360 timer9: timer@4803e000 {
361 compatible = "ti,omap5430-timer";
362 reg = <0x4803e000 0x80>;
363 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
364 ti,hwmods = "timer9";
367 timer10: timer@48086000 {
368 compatible = "ti,omap5430-timer";
369 reg = <0x48086000 0x80>;
370 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
371 ti,hwmods = "timer10";
374 timer11: timer@48088000 {
375 compatible = "ti,omap5430-timer";
376 reg = <0x48088000 0x80>;
377 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
378 ti,hwmods = "timer11";
382 timer13: timer@48828000 {
383 compatible = "ti,omap5430-timer";
384 reg = <0x48828000 0x80>;
385 ti,hwmods = "timer13";
389 timer14: timer@4882a000 {
390 compatible = "ti,omap5430-timer";
391 reg = <0x4882a000 0x80>;
392 ti,hwmods = "timer14";
396 timer15: timer@4882c000 {
397 compatible = "ti,omap5430-timer";
398 reg = <0x4882c000 0x80>;
399 ti,hwmods = "timer15";
403 timer16: timer@4882e000 {
404 compatible = "ti,omap5430-timer";
405 reg = <0x4882e000 0x80>;
406 ti,hwmods = "timer16";
411 compatible = "ti,omap4-wdt";
412 reg = <0x4ae14000 0x80>;
413 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
414 ti,hwmods = "wd_timer2";
418 compatible = "ti,omap4-i2c";
419 reg = <0x48070000 0x100>;
420 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
421 #address-cells = <1>;
428 compatible = "ti,omap4-i2c";
429 reg = <0x48072000 0x100>;
430 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
431 #address-cells = <1>;
438 compatible = "ti,omap4-i2c";
439 reg = <0x48060000 0x100>;
440 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
441 #address-cells = <1>;
448 compatible = "ti,omap4-i2c";
449 reg = <0x4807a000 0x100>;
450 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
451 #address-cells = <1>;
458 compatible = "ti,omap4-i2c";
459 reg = <0x4807c000 0x100>;
460 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
461 #address-cells = <1>;
468 compatible = "ti,omap4-hsmmc";
469 reg = <0x4809c000 0x400>;
470 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
473 ti,needs-special-reset;
474 dmas = <&sdma 61>, <&sdma 62>;
475 dma-names = "tx", "rx";
480 compatible = "ti,omap4-hsmmc";
481 reg = <0x480b4000 0x400>;
482 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
484 ti,needs-special-reset;
485 dmas = <&sdma 47>, <&sdma 48>;
486 dma-names = "tx", "rx";
491 compatible = "ti,omap4-hsmmc";
492 reg = <0x480ad000 0x400>;
493 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
495 ti,needs-special-reset;
496 dmas = <&sdma 77>, <&sdma 78>;
497 dma-names = "tx", "rx";
502 compatible = "ti,omap4-hsmmc";
503 reg = <0x480d1000 0x400>;
504 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
506 ti,needs-special-reset;
507 dmas = <&sdma 57>, <&sdma 58>;
508 dma-names = "tx", "rx";
512 mcspi1: spi@48098000 {
513 compatible = "ti,omap4-mcspi";
514 reg = <0x48098000 0x200>;
515 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
516 #address-cells = <1>;
518 ti,hwmods = "mcspi1";
528 dma-names = "tx0", "rx0", "tx1", "rx1",
529 "tx2", "rx2", "tx3", "rx3";
533 mcspi2: spi@4809a000 {
534 compatible = "ti,omap4-mcspi";
535 reg = <0x4809a000 0x200>;
536 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
537 #address-cells = <1>;
539 ti,hwmods = "mcspi2";
545 dma-names = "tx0", "rx0", "tx1", "rx1";
549 mcspi3: spi@480b8000 {
550 compatible = "ti,omap4-mcspi";
551 reg = <0x480b8000 0x200>;
552 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
553 #address-cells = <1>;
555 ti,hwmods = "mcspi3";
557 dmas = <&sdma 15>, <&sdma 16>;
558 dma-names = "tx0", "rx0";
562 mcspi4: spi@480ba000 {
563 compatible = "ti,omap4-mcspi";
564 reg = <0x480ba000 0x200>;
565 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
566 #address-cells = <1>;
568 ti,hwmods = "mcspi4";
570 dmas = <&sdma 70>, <&sdma 71>;
571 dma-names = "tx0", "rx0";