2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h>
13 #include "skeleton.dtsi"
19 compatible = "ti,dra7xx";
20 interrupt-parent = <&gic>;
42 compatible = "arm,cortex-a15";
51 clocks = <&dpll_mpu_ck>;
54 clock-latency = <300000>; /* From omap-cpufreq driver */
58 compatible = "arm,cortex-a15";
64 compatible = "arm,armv7-timer";
65 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
66 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
67 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
68 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
71 gic: interrupt-controller@48211000 {
72 compatible = "arm,cortex-a15-gic";
74 #interrupt-cells = <3>;
75 reg = <0x48211000 0x1000>,
79 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
83 * The soc node represents the soc top level view. It is uses for IPs
84 * that are not memory mapped in the MPU view or for the MPU itself.
87 compatible = "ti,omap-infra";
89 compatible = "ti,omap5-mpu";
95 * XXX: Use a flat representation of the SOC interconnect.
96 * The real OMAP interconnect network is quite complex.
97 * Since that will not bring real advantage to represent that in DT for
98 * the moment, just use a fake OCP bus entry to represent the whole bus
102 compatible = "ti,omap4-l3-noc", "simple-bus";
103 #address-cells = <1>;
106 ti,hwmods = "l3_main_1", "l3_main_2";
107 reg = <0x44000000 0x2000>,
109 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
110 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
113 compatible = "ti,dra7-prm";
114 reg = <0x4ae06000 0x3000>;
117 #address-cells = <1>;
121 prm_clockdomains: clockdomains {
125 cm_core_aon: cm_core_aon@4a005000 {
126 compatible = "ti,dra7-cm-core-aon";
127 reg = <0x4a005000 0x2000>;
129 cm_core_aon_clocks: clocks {
130 #address-cells = <1>;
134 cm_core_aon_clockdomains: clockdomains {
138 cm_core: cm_core@4a008000 {
139 compatible = "ti,dra7-cm-core";
140 reg = <0x4a008000 0x3000>;
142 cm_core_clocks: clocks {
143 #address-cells = <1>;
147 cm_core_clockdomains: clockdomains {
151 counter32k: counter@4ae04000 {
152 compatible = "ti,omap-counter32k";
153 reg = <0x4ae04000 0x40>;
154 ti,hwmods = "counter_32k";
157 dra7_pmx_core: pinmux@4a003400 {
158 compatible = "pinctrl-single";
159 reg = <0x4a003400 0x0464>;
160 #address-cells = <1>;
162 pinctrl-single,register-width = <32>;
163 pinctrl-single,function-mask = <0x3fffffff>;
166 sdma: dma-controller@4a056000 {
167 compatible = "ti,omap4430-sdma";
168 reg = <0x4a056000 0x1000>;
169 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
170 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
171 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
174 #dma-channels = <32>;
175 #dma-requests = <127>;
178 gpio1: gpio@4ae10000 {
179 compatible = "ti,omap4-gpio";
180 reg = <0x4ae10000 0x200>;
181 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
185 interrupt-controller;
186 #interrupt-cells = <1>;
189 gpio2: gpio@48055000 {
190 compatible = "ti,omap4-gpio";
191 reg = <0x48055000 0x200>;
192 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
196 interrupt-controller;
197 #interrupt-cells = <1>;
200 gpio3: gpio@48057000 {
201 compatible = "ti,omap4-gpio";
202 reg = <0x48057000 0x200>;
203 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
207 interrupt-controller;
208 #interrupt-cells = <1>;
211 gpio4: gpio@48059000 {
212 compatible = "ti,omap4-gpio";
213 reg = <0x48059000 0x200>;
214 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
218 interrupt-controller;
219 #interrupt-cells = <1>;
222 gpio5: gpio@4805b000 {
223 compatible = "ti,omap4-gpio";
224 reg = <0x4805b000 0x200>;
225 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
229 interrupt-controller;
230 #interrupt-cells = <1>;
233 gpio6: gpio@4805d000 {
234 compatible = "ti,omap4-gpio";
235 reg = <0x4805d000 0x200>;
236 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
240 interrupt-controller;
241 #interrupt-cells = <1>;
244 gpio7: gpio@48051000 {
245 compatible = "ti,omap4-gpio";
246 reg = <0x48051000 0x200>;
247 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
251 interrupt-controller;
252 #interrupt-cells = <1>;
255 gpio8: gpio@48053000 {
256 compatible = "ti,omap4-gpio";
257 reg = <0x48053000 0x200>;
258 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
262 interrupt-controller;
263 #interrupt-cells = <1>;
266 uart1: serial@4806a000 {
267 compatible = "ti,omap4-uart";
268 reg = <0x4806a000 0x100>;
269 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
271 clock-frequency = <48000000>;
275 uart2: serial@4806c000 {
276 compatible = "ti,omap4-uart";
277 reg = <0x4806c000 0x100>;
278 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
280 clock-frequency = <48000000>;
284 uart3: serial@48020000 {
285 compatible = "ti,omap4-uart";
286 reg = <0x48020000 0x100>;
287 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
289 clock-frequency = <48000000>;
293 uart4: serial@4806e000 {
294 compatible = "ti,omap4-uart";
295 reg = <0x4806e000 0x100>;
296 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
298 clock-frequency = <48000000>;
302 uart5: serial@48066000 {
303 compatible = "ti,omap4-uart";
304 reg = <0x48066000 0x100>;
305 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
307 clock-frequency = <48000000>;
311 uart6: serial@48068000 {
312 compatible = "ti,omap4-uart";
313 reg = <0x48068000 0x100>;
314 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
316 clock-frequency = <48000000>;
320 uart7: serial@48420000 {
321 compatible = "ti,omap4-uart";
322 reg = <0x48420000 0x100>;
324 clock-frequency = <48000000>;
328 uart8: serial@48422000 {
329 compatible = "ti,omap4-uart";
330 reg = <0x48422000 0x100>;
332 clock-frequency = <48000000>;
336 uart9: serial@48424000 {
337 compatible = "ti,omap4-uart";
338 reg = <0x48424000 0x100>;
340 clock-frequency = <48000000>;
344 uart10: serial@4ae2b000 {
345 compatible = "ti,omap4-uart";
346 reg = <0x4ae2b000 0x100>;
347 ti,hwmods = "uart10";
348 clock-frequency = <48000000>;
352 timer1: timer@4ae18000 {
353 compatible = "ti,omap5430-timer";
354 reg = <0x4ae18000 0x80>;
355 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
356 ti,hwmods = "timer1";
360 timer2: timer@48032000 {
361 compatible = "ti,omap5430-timer";
362 reg = <0x48032000 0x80>;
363 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
364 ti,hwmods = "timer2";
367 timer3: timer@48034000 {
368 compatible = "ti,omap5430-timer";
369 reg = <0x48034000 0x80>;
370 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
371 ti,hwmods = "timer3";
374 timer4: timer@48036000 {
375 compatible = "ti,omap5430-timer";
376 reg = <0x48036000 0x80>;
377 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
378 ti,hwmods = "timer4";
381 timer5: timer@48820000 {
382 compatible = "ti,omap5430-timer";
383 reg = <0x48820000 0x80>;
384 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
385 ti,hwmods = "timer5";
389 timer6: timer@48822000 {
390 compatible = "ti,omap5430-timer";
391 reg = <0x48822000 0x80>;
392 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
393 ti,hwmods = "timer6";
398 timer7: timer@48824000 {
399 compatible = "ti,omap5430-timer";
400 reg = <0x48824000 0x80>;
401 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
402 ti,hwmods = "timer7";
406 timer8: timer@48826000 {
407 compatible = "ti,omap5430-timer";
408 reg = <0x48826000 0x80>;
409 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
410 ti,hwmods = "timer8";
415 timer9: timer@4803e000 {
416 compatible = "ti,omap5430-timer";
417 reg = <0x4803e000 0x80>;
418 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
419 ti,hwmods = "timer9";
422 timer10: timer@48086000 {
423 compatible = "ti,omap5430-timer";
424 reg = <0x48086000 0x80>;
425 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
426 ti,hwmods = "timer10";
429 timer11: timer@48088000 {
430 compatible = "ti,omap5430-timer";
431 reg = <0x48088000 0x80>;
432 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
433 ti,hwmods = "timer11";
437 timer13: timer@48828000 {
438 compatible = "ti,omap5430-timer";
439 reg = <0x48828000 0x80>;
440 ti,hwmods = "timer13";
444 timer14: timer@4882a000 {
445 compatible = "ti,omap5430-timer";
446 reg = <0x4882a000 0x80>;
447 ti,hwmods = "timer14";
451 timer15: timer@4882c000 {
452 compatible = "ti,omap5430-timer";
453 reg = <0x4882c000 0x80>;
454 ti,hwmods = "timer15";
458 timer16: timer@4882e000 {
459 compatible = "ti,omap5430-timer";
460 reg = <0x4882e000 0x80>;
461 ti,hwmods = "timer16";
466 compatible = "ti,omap4-wdt";
467 reg = <0x4ae14000 0x80>;
468 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
469 ti,hwmods = "wd_timer2";
472 hwspinlock: spinlock@4a0f6000 {
473 compatible = "ti,omap4-hwspinlock";
474 reg = <0x4a0f6000 0x1000>;
475 ti,hwmods = "spinlock";
480 compatible = "ti,omap5-dmm";
481 reg = <0x4e000000 0x800>;
482 interrupts = <0 113 0x4>;
487 compatible = "ti,omap4-i2c";
488 reg = <0x48070000 0x100>;
489 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
490 #address-cells = <1>;
497 compatible = "ti,omap4-i2c";
498 reg = <0x48072000 0x100>;
499 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
500 #address-cells = <1>;
507 compatible = "ti,omap4-i2c";
508 reg = <0x48060000 0x100>;
509 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
510 #address-cells = <1>;
517 compatible = "ti,omap4-i2c";
518 reg = <0x4807a000 0x100>;
519 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
520 #address-cells = <1>;
527 compatible = "ti,omap4-i2c";
528 reg = <0x4807c000 0x100>;
529 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
530 #address-cells = <1>;
537 compatible = "ti,omap4-hsmmc";
538 reg = <0x4809c000 0x400>;
539 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
542 ti,needs-special-reset;
543 dmas = <&sdma 61>, <&sdma 62>;
544 dma-names = "tx", "rx";
549 compatible = "ti,omap4-hsmmc";
550 reg = <0x480b4000 0x400>;
551 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
553 ti,needs-special-reset;
554 dmas = <&sdma 47>, <&sdma 48>;
555 dma-names = "tx", "rx";
560 compatible = "ti,omap4-hsmmc";
561 reg = <0x480ad000 0x400>;
562 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
564 ti,needs-special-reset;
565 dmas = <&sdma 77>, <&sdma 78>;
566 dma-names = "tx", "rx";
571 compatible = "ti,omap4-hsmmc";
572 reg = <0x480d1000 0x400>;
573 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
575 ti,needs-special-reset;
576 dmas = <&sdma 57>, <&sdma 58>;
577 dma-names = "tx", "rx";
581 abb_mpu: regulator-abb-mpu {
582 compatible = "ti,abb-v3";
583 regulator-name = "abb_mpu";
584 #address-cells = <0>;
586 clocks = <&sys_clkin1>;
587 ti,settling-time = <50>;
588 ti,clock-cycles = <16>;
590 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
591 <0x4ae06014 0x4>, <0x4a003b20 0x8>,
593 reg-names = "setup-address", "control-address",
594 "int-address", "efuse-address",
596 ti,tranxdone-status-mask = <0x80>;
597 /* LDOVBBMPU_FBB_MUX_CTRL */
598 ti,ldovbb-override-mask = <0x400>;
599 /* LDOVBBMPU_FBB_VSET_OUT */
600 ti,ldovbb-vset-mask = <0x1F>;
603 * NOTE: only FBB mode used but actual vset will
604 * determine final biasing
607 /*uV ABB efuse rbb_m fbb_m vset_m*/
608 1060000 0 0x0 0 0x02000000 0x01F00000
609 1160000 0 0x4 0 0x02000000 0x01F00000
610 1210000 0 0x8 0 0x02000000 0x01F00000
614 abb_ivahd: regulator-abb-ivahd {
615 compatible = "ti,abb-v3";
616 regulator-name = "abb_ivahd";
617 #address-cells = <0>;
619 clocks = <&sys_clkin1>;
620 ti,settling-time = <50>;
621 ti,clock-cycles = <16>;
623 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
624 <0x4ae06010 0x4>, <0x4a0025cc 0x8>,
626 reg-names = "setup-address", "control-address",
627 "int-address", "efuse-address",
629 ti,tranxdone-status-mask = <0x40000000>;
630 /* LDOVBBIVA_FBB_MUX_CTRL */
631 ti,ldovbb-override-mask = <0x400>;
632 /* LDOVBBIVA_FBB_VSET_OUT */
633 ti,ldovbb-vset-mask = <0x1F>;
636 * NOTE: only FBB mode used but actual vset will
637 * determine final biasing
640 /*uV ABB efuse rbb_m fbb_m vset_m*/
641 1055000 0 0x0 0 0x02000000 0x01F00000
642 1150000 0 0x4 0 0x02000000 0x01F00000
643 1250000 0 0x8 0 0x02000000 0x01F00000
647 abb_dspeve: regulator-abb-dspeve {
648 compatible = "ti,abb-v3";
649 regulator-name = "abb_dspeve";
650 #address-cells = <0>;
652 clocks = <&sys_clkin1>;
653 ti,settling-time = <50>;
654 ti,clock-cycles = <16>;
656 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
657 <0x4ae06010 0x4>, <0x4a0025e0 0x8>,
659 reg-names = "setup-address", "control-address",
660 "int-address", "efuse-address",
662 ti,tranxdone-status-mask = <0x20000000>;
663 /* LDOVBBDSPEVE_FBB_MUX_CTRL */
664 ti,ldovbb-override-mask = <0x400>;
665 /* LDOVBBDSPEVE_FBB_VSET_OUT */
666 ti,ldovbb-vset-mask = <0x1F>;
669 * NOTE: only FBB mode used but actual vset will
670 * determine final biasing
673 /*uV ABB efuse rbb_m fbb_m vset_m*/
674 1055000 0 0x0 0 0x02000000 0x01F00000
675 1150000 0 0x4 0 0x02000000 0x01F00000
676 1250000 0 0x8 0 0x02000000 0x01F00000
680 abb_gpu: regulator-abb-gpu {
681 compatible = "ti,abb-v3";
682 regulator-name = "abb_gpu";
683 #address-cells = <0>;
685 clocks = <&sys_clkin1>;
686 ti,settling-time = <50>;
687 ti,clock-cycles = <16>;
689 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
690 <0x4ae06010 0x4>, <0x4a003b08 0x8>,
692 reg-names = "setup-address", "control-address",
693 "int-address", "efuse-address",
695 ti,tranxdone-status-mask = <0x10000000>;
696 /* LDOVBBGPU_FBB_MUX_CTRL */
697 ti,ldovbb-override-mask = <0x400>;
698 /* LDOVBBGPU_FBB_VSET_OUT */
699 ti,ldovbb-vset-mask = <0x1F>;
702 * NOTE: only FBB mode used but actual vset will
703 * determine final biasing
706 /*uV ABB efuse rbb_m fbb_m vset_m*/
707 1090000 0 0x0 0 0x02000000 0x01F00000
708 1210000 0 0x4 0 0x02000000 0x01F00000
709 1280000 0 0x8 0 0x02000000 0x01F00000
713 mcspi1: spi@48098000 {
714 compatible = "ti,omap4-mcspi";
715 reg = <0x48098000 0x200>;
716 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
717 #address-cells = <1>;
719 ti,hwmods = "mcspi1";
729 dma-names = "tx0", "rx0", "tx1", "rx1",
730 "tx2", "rx2", "tx3", "rx3";
734 mcspi2: spi@4809a000 {
735 compatible = "ti,omap4-mcspi";
736 reg = <0x4809a000 0x200>;
737 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
738 #address-cells = <1>;
740 ti,hwmods = "mcspi2";
746 dma-names = "tx0", "rx0", "tx1", "rx1";
750 mcspi3: spi@480b8000 {
751 compatible = "ti,omap4-mcspi";
752 reg = <0x480b8000 0x200>;
753 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
754 #address-cells = <1>;
756 ti,hwmods = "mcspi3";
758 dmas = <&sdma 15>, <&sdma 16>;
759 dma-names = "tx0", "rx0";
763 mcspi4: spi@480ba000 {
764 compatible = "ti,omap4-mcspi";
765 reg = <0x480ba000 0x200>;
766 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
767 #address-cells = <1>;
769 ti,hwmods = "mcspi4";
771 dmas = <&sdma 70>, <&sdma 71>;
772 dma-names = "tx0", "rx0";
778 /include/ "dra7xx-clocks.dtsi"