2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include "dra72x.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
15 compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
18 device_type = "memory";
19 reg = <0x80000000 0x40000000>; /* 1024 MB */
26 evm_3v3: fixedregulator-evm_3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "evm_3v3";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
33 extcon_usb1: extcon_usb1 {
34 compatible = "linux,extcon-usb-gpio";
35 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
38 extcon_usb2: extcon_usb2 {
39 compatible = "linux,extcon-usb-gpio";
40 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
44 compatible = "hdmi-connector";
50 hdmi_connector_in: endpoint {
51 remote-endpoint = <&tpd12s015_out>;
57 compatible = "ti,tpd12s015";
59 pinctrl-names = "default";
60 pinctrl-0 = <&tpd12s015_pins>;
62 gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
63 <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
64 <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
73 tpd12s015_in: endpoint {
74 remote-endpoint = <&hdmi_out>;
81 tpd12s015_out: endpoint {
82 remote-endpoint = <&hdmi_connector_in>;
90 i2c1_pins: pinmux_i2c1_pins {
91 pinctrl-single,pins = <
92 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
93 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
97 i2c5_pins: pinmux_i2c5_pins {
98 pinctrl-single,pins = <
99 0x2b4 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
100 0x2b8 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
104 nand_default: nand_default {
105 pinctrl-single,pins = <
106 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
107 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
108 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
109 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
110 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
111 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
112 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
113 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
114 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
115 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
116 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
117 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
118 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
119 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
120 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
121 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
122 0xb4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */
123 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
124 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
125 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
126 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */
127 0xd8 (PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */
131 usb1_pins: pinmux_usb1_pins {
132 pinctrl-single,pins = <
133 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
137 usb2_pins: pinmux_usb2_pins {
138 pinctrl-single,pins = <
139 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
143 tps65917_pins_default: tps65917_pins_default {
144 pinctrl-single,pins = <
145 0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
149 mmc1_pins_default: mmc1_pins_default {
150 pinctrl-single,pins = <
151 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
152 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
153 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
154 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
155 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
156 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
157 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
161 mmc2_pins_default: mmc2_pins_default {
162 pinctrl-single,pins = <
163 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
164 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
165 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
166 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
167 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
168 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
169 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
170 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
171 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
172 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
176 dcan1_pins_default: dcan1_pins_default {
177 pinctrl-single,pins = <
178 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
179 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
183 dcan1_pins_sleep: dcan1_pins_sleep {
184 pinctrl-single,pins = <
185 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
186 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
190 qspi1_pins: pinmux_qspi1_pins {
191 pinctrl-single,pins = <
192 0x74 (PIN_OUTPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
193 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
194 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
195 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
196 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
197 0x88 (PIN_OUTPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
198 0xb8 (PIN_OUTPUT | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
202 hdmi_pins: pinmux_hdmi_pins {
203 pinctrl-single,pins = <
204 0x408 (PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
205 0x40c (PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
209 tpd12s015_pins: pinmux_tpd12s015_pins {
210 pinctrl-single,pins = <
211 0x3b8 (PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */
218 pinctrl-names = "default";
219 pinctrl-0 = <&i2c1_pins>;
220 clock-frequency = <400000>;
222 tps65917: tps65917@58 {
223 compatible = "ti,tps65917";
226 pinctrl-names = "default";
227 pinctrl-0 = <&tps65917_pins_default>;
229 interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
230 interrupt-controller;
231 #interrupt-cells = <2>;
233 ti,system-power-controller;
236 compatible = "ti,tps65917-pmic";
241 regulator-name = "smps1";
242 regulator-min-microvolt = <850000>;
243 regulator-max-microvolt = <1250000>;
250 regulator-name = "smps2";
251 regulator-min-microvolt = <850000>;
252 regulator-max-microvolt = <1060000>;
258 /* VDD_GPU IVA DSPEVE */
259 regulator-name = "smps3";
260 regulator-min-microvolt = <850000>;
261 regulator-max-microvolt = <1250000>;
268 regulator-name = "smps4";
269 regulator-min-microvolt = <1800000>;
270 regulator-max-microvolt = <1800000>;
277 regulator-name = "smps5";
278 regulator-min-microvolt = <1350000>;
279 regulator-max-microvolt = <1350000>;
285 /* LDO1_OUT --> SDIO */
286 regulator-name = "ldo1";
287 regulator-min-microvolt = <1800000>;
288 regulator-max-microvolt = <3300000>;
293 /* LDO2_OUT --> TP1017 (UNUSED) */
294 regulator-name = "ldo2";
295 regulator-min-microvolt = <1800000>;
296 regulator-max-microvolt = <3300000>;
301 regulator-name = "ldo3";
302 regulator-min-microvolt = <1800000>;
303 regulator-max-microvolt = <1800000>;
310 regulator-name = "ldo5";
311 regulator-min-microvolt = <1800000>;
312 regulator-max-microvolt = <1800000>;
318 /* VDDA_3V_USB: VDDA_USBHS33 */
319 regulator-name = "ldo4";
320 regulator-min-microvolt = <3300000>;
321 regulator-max-microvolt = <3300000>;
327 tps65917_power_button {
328 compatible = "ti,palmas-pwrbutton";
329 interrupt-parent = <&tps65917>;
330 interrupts = <1 IRQ_TYPE_NONE>;
332 ti,palmas-long-press-seconds = <6>;
336 pcf_gpio_21: gpio@21 {
337 compatible = "ti,pcf8575";
339 lines-initial-states = <0x1408>;
342 interrupt-parent = <&gpio6>;
343 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
344 interrupt-controller;
345 #interrupt-cells = <2>;
351 pinctrl-names = "default";
352 pinctrl-0 = <&i2c5_pins>;
353 clock-frequency = <400000>;
355 pcf_hdmi: pcf8575@26 {
356 compatible = "nxp,pcf8575";
361 * initial state is used here to keep the mdio interface
362 * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
363 * VIN2_S0 driven high otherwise Ethernet stops working
364 * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
366 lines-initial-states = <0x0f2b>;
380 pinctrl-names = "default";
381 pinctrl-0 = <&nand_default>;
382 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
384 /* To use NAND, DIP switch SW5 must be set like so:
385 * SW5.1 (NAND_SELn) = ON (LOW)
386 * SW5.9 (GPMC_WPN) = OFF (HIGH)
388 reg = <0 0 4>; /* device IO registers */
389 ti,nand-ecc-opt = "bch8";
391 nand-bus-width = <16>;
392 gpmc,device-width = <2>;
393 gpmc,sync-clk-ps = <0>;
395 gpmc,cs-rd-off-ns = <80>;
396 gpmc,cs-wr-off-ns = <80>;
397 gpmc,adv-on-ns = <0>;
398 gpmc,adv-rd-off-ns = <60>;
399 gpmc,adv-wr-off-ns = <60>;
400 gpmc,we-on-ns = <10>;
401 gpmc,we-off-ns = <50>;
403 gpmc,oe-off-ns = <40>;
404 gpmc,access-ns = <40>;
405 gpmc,wr-access-ns = <80>;
406 gpmc,rd-cycle-ns = <80>;
407 gpmc,wr-cycle-ns = <80>;
408 gpmc,bus-turnaround-ns = <0>;
409 gpmc,cycle2cycle-delay-ns = <0>;
410 gpmc,clk-activation-ns = <0>;
411 gpmc,wait-monitoring-ns = <0>;
412 gpmc,wr-data-mux-bus-ns = <0>;
413 /* MTD partition table */
414 /* All SPL-* partitions are sized to minimal length
415 * which can be independently programmable. For
416 * NAND flash this is equal to size of erase-block */
417 #address-cells = <1>;
421 reg = <0x00000000 0x000020000>;
424 label = "NAND.SPL.backup1";
425 reg = <0x00020000 0x00020000>;
428 label = "NAND.SPL.backup2";
429 reg = <0x00040000 0x00020000>;
432 label = "NAND.SPL.backup3";
433 reg = <0x00060000 0x00020000>;
436 label = "NAND.u-boot-spl-os";
437 reg = <0x00080000 0x00040000>;
440 label = "NAND.u-boot";
441 reg = <0x000c0000 0x00100000>;
444 label = "NAND.u-boot-env";
445 reg = <0x001c0000 0x00020000>;
448 label = "NAND.u-boot-env.backup1";
449 reg = <0x001e0000 0x00020000>;
452 label = "NAND.kernel";
453 reg = <0x00200000 0x00800000>;
456 label = "NAND.file-system";
457 reg = <0x00a00000 0x0f600000>;
463 phy-supply = <&ldo4_reg>;
467 phy-supply = <&ldo4_reg>;
471 extcon = <&extcon_usb1>;
475 extcon = <&extcon_usb2>;
479 dr_mode = "peripheral";
480 pinctrl-names = "default";
481 pinctrl-0 = <&usb1_pins>;
486 pinctrl-names = "default";
487 pinctrl-0 = <&usb2_pins>;
492 pinctrl-names = "default";
493 pinctrl-0 = <&mmc1_pins_default>;
495 vmmc-supply = <&ldo1_reg>;
498 * SDCD signal is not being used here - using the fact that GPIO mode
499 * is a viable alternative
501 cd-gpios = <&gpio6 27 0>;
505 /* SW5-3 in ON position */
507 pinctrl-names = "default";
508 pinctrl-0 = <&mmc2_pins_default>;
510 vmmc-supply = <&evm_3v3>;
516 cpsw_default: cpsw_default {
517 pinctrl-single,pins = <
519 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
520 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
521 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
522 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
523 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
524 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
525 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
526 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
527 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
528 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
529 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
530 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
535 cpsw_sleep: cpsw_sleep {
536 pinctrl-single,pins = <
553 davinci_mdio_default: davinci_mdio_default {
554 pinctrl-single,pins = <
556 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
557 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
561 davinci_mdio_sleep: davinci_mdio_sleep {
562 pinctrl-single,pins = <
571 pinctrl-names = "default", "sleep";
572 pinctrl-0 = <&cpsw_default>;
573 pinctrl-1 = <&cpsw_sleep>;
577 phy_id = <&davinci_mdio>, <3>;
582 pinctrl-names = "default", "sleep";
583 pinctrl-0 = <&davinci_mdio_default>;
584 pinctrl-1 = <&davinci_mdio_sleep>;
590 pinctrl-names = "default", "sleep", "active";
591 pinctrl-0 = <&dcan1_pins_sleep>;
592 pinctrl-1 = <&dcan1_pins_sleep>;
593 pinctrl-2 = <&dcan1_pins_default>;
598 pinctrl-names = "default";
599 pinctrl-0 = <&qspi1_pins>;
601 spi-max-frequency = <48000000>;
603 compatible = "s25fl256s1";
604 spi-max-frequency = <48000000>;
606 spi-tx-bus-width = <1>;
607 spi-rx-bus-width = <4>;
610 #address-cells = <1>;
613 /* MTD partition table.
614 * The ROM checks the first four physical blocks
615 * for a valid file to boot and the flash here is
620 reg = <0x00000000 0x000010000>;
623 label = "QSPI.SPL.backup1";
624 reg = <0x00010000 0x00010000>;
627 label = "QSPI.SPL.backup2";
628 reg = <0x00020000 0x00010000>;
631 label = "QSPI.SPL.backup3";
632 reg = <0x00030000 0x00010000>;
635 label = "QSPI.u-boot";
636 reg = <0x00040000 0x00100000>;
639 label = "QSPI.u-boot-spl-os";
640 reg = <0x00140000 0x00080000>;
643 label = "QSPI.u-boot-env";
644 reg = <0x001c0000 0x00010000>;
647 label = "QSPI.u-boot-env.backup1";
648 reg = <0x001d0000 0x0010000>;
651 label = "QSPI.kernel";
652 reg = <0x001e0000 0x0800000>;
655 label = "QSPI.file-system";
656 reg = <0x009e0000 0x01620000>;
664 vdda_video-supply = <&ldo5_reg>;
669 vdda-supply = <&ldo3_reg>;
671 pinctrl-names = "default";
672 pinctrl-0 = <&hdmi_pins>;
676 remote-endpoint = <&tpd12s015_in>;